PL611S-08-XXXTIR

( Preliminary) PL611s-08 L ow-Power Programmable Quick Turn Clock T M F EATURES • A dvanced low-power, space saving programmable PLL design • Very low Jitter and Phase Noise (30-70ps Pk-Pk typical) • U p to 2 programmable clock outputs • O utput frequency up to 75MHz. • A ccepts Crystal or Ref Clock input o F undamental Crystal: 10MHz-50MHz o R eference Input: 1MHz to 100MHz • A ccepts > 0.1V reference signal input voltage • S ingle 1.8V, 2.5V, or 3.3V ± 10% power supply • O perating temperature range from -40C to 85 ° C • A vailable in 6-pin TDFN, SC70, and SOT23, GREEN / RoHS compliant packages D ESCRIPTION T he PL611s-08 is a low-power general purpose frequency synthesizer and a member of PhaseLink’s Programmable ‘Quick Turn Clock (QTC)’ family. PhaseLink’s PL611s-08 can generate two system clock frequencies of up to 75MHz from a 10MHz to 50MHz fundamental crystal or a 1MHz to 100MHz Reference clock source. The PL611s-08 offers the best phase noise and jitter performance, and power consumption of its rivals. Cascading of the ICs to produce additional clock frequencies is also supported. P ACKAGE PIN CONFIGURATION OE, CLK1 GND PL611s-08 PL611s-08 PL611s-08 1 2 3 6 5 4 CLK0 VDD XOUT GND XIN, FIN 1 2 3 6 5 4 CLK0 VDD XOUT PL611s-08 PL611s-08 PL611s-08 PL611s-08 XIN, FIN OE, CLK1 GND 1 2 3 6 5 4 XOUT VDD OE, CLK1 CLK0 XIN, FIN DFNDFN-6L (2.0mmx1.3mmx0.6mm) mmx1 mmx0 mm) SC70SC70-6L 70 (2.3mmx2.25mmx1.0mm) mmx2 25mmx1 mm) mmx SOT23SOT23-6L 23 (3.0mmx3.0mmx1.35mm) mmx3 mmx1 35mm) mm BLOCK DIAGRAM XIN/FIN XOUT XTAL OSC Programmable CLoad FREF R-Counter (8-bit) M-Counter (11-bit) Phase Detector Charge Pump Loop Filter F VCO = F REF * (2 * M/R) VCO P-Counter (5-bit) FOUT = F VCO / (2 * P) Programmable Function CLK0 Programming Logic OE, CLK1 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 12/12/06 Page 1 ( Preliminary) PL611s-08 L ow-Power Programmable Quick Turn Clock T M K EY PROGRAMMING PARAMETERS CLK Output Frequency FOUT = FREF * M / (R * P) Where M = 11 bit R = 8 bit P = 5 bit CLK0 = FOUT, FREF or FREF / (2*P) CLK1 = FREF, FREF/2, CLK0 or CLK0/2 Output Drive Strength Three optional drive strengths to choose from: • Low: 4mA • Std: 8mA (default) • High: 16mA Programmable Input/Output One output pin can be configured as: • OE - input • CLK1 – output P ACKAGE PIN ASSIGNMENT N ame P in Assignment SOT SC70 DFN Pin # Pin# Pin# 1 2 3 4 5 6 4 2, 5 6 1 3 2 3 1 6 5 4 Type Description This programmable I/O pin can be configured as an Output Enable (OE) input, or CLK1 output. This pin has an internal 60K pull up resistor ( OE Function Only ). GND connection Crystal or Reference input pin C rystal Output pin X OUT V DD C LK0 O Do Not Connect (DNC ) when FIN is present P O VDD connection Programmable Clock Output O E, CLK1 G ND X IN, FIN B P I 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 12/12/06 Page 2 ( Preliminary) PL611s-08 L ow-Power Programmable Quick Turn Clock T M F UNCTIONAL DESCRIPTION P L611s-08 is a highly featured, very flexible, advanced programmable PLL design for high performance, lowpower, small form-factor applications. The PL611s-08 accepts a fundamental input crystal of 10MHz to 50MHz or reference clock input of 1MHz to 100MHz and is capable of producing two outputs up to 75MHz. This flexible design allows the PL611s-08 to deliver any PLL generated frequency, F REF ( Crystal or Ref Clk) frequency or F REF /2 to CLK0 and/or CLK1. Some of the design features of the PL611s-08 are mentioned below: P LL Programming T he PLL in the PL611s-08 is fully programmable. The PLL is equipped with an 8-bit input frequency divider (R-Counter), and an 11-bit VCO frequency feedback loop divider (M-Counter). The output of the PLL is transferred to a 5-bit post VCO divider (PCounter). The output frequency is determined by the following formula [F OUT = F REF * M / ( R * P) ]. C lock Output (CLK0) C LK0 is the main clock output. The PL611s-08 can also be programmed to provide a second clock output, CLK1, on the programmable I/O pin (see OE /CLK1 pin description below). The output of CLK0 can be configured as the PLL output (F VCO /(2*P)), F REF ( Crystal or Ref Clk Frequency) output, or F REF /2 output. The output drive level can be programmed to Low Drive (4mA), Standard Drive (8mA) or High Drive (16mA). The maximum output frequency is 75MHz. P rogrammable I/O (OE/CLK1) T he PL611s-08 provides one programmable I/O pin which can be configured as one of the following functions: Output Enable (OE) The Output Enable feature allows the user to enable and disable the clock output(s) by toggling the OE pin. The OE pin incorporates a 60k pull up resistor giving a default condition of logic “1”. Clock Output (CLK1) T he CLK1 feature allows the PL611s-08 to have an additional clock output. This output can be programmed to one of the following: FREF - Reference ( Crystal or Ref Clk ) Frequency FREF / 2 CLK0 CLK0 / 2 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 12/12/06 Page 3 ( Preliminary) PL611s-08 L ow-Power Programmable Quick Turn Clock T M E LECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS P ARAMETERS S upply Voltage Range I nput Voltage Range O utput Voltage Range S oldering Temperature (Green package) D ata Retention @ 85 ° C S torage Temperature A mbient Operating Temperature* SYMBOL V DD VI VO MIN. MAX. 7 V DD + 0.5 V DD + 0.5 260 150 85 UNITS V V V °C Year °C °C - 0.5 - 0.5 - 0.5 10 TS - 65 -40 Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only. AC SPECIFICATIONS PARAMETERS C rystal Input Frequency (XIN) I nput (FIN) Frequency I nput (FIN) Signal Amplitude I nput (FIN) Signal Amplitude CONDITIONS Fundamental Crystal Reference Clock Internally AC coupled (High Frequency) Internally AC coupled (Low Frequency) 3.3V < 50MHz, 2.5V < 40MHz, 1.8V < 15MHz @ VDD = 3.3V @ VDD = 2.5V @ VDD = 1.8V MIN. 10 1 0.9 0.1 TYP. MAX. 50 100 VDD VDD UNITS MHz MHz V pp V pp MHz O utput Frequency 75 MHz MHz S ettling Time O utput Enable Time V DD Sensitivity O utput Rise Time O utput Fall Time At power-up (after VDD i ncreases over 1.62V) O E Function; Ta=25º C, 15pF Load PDB Function; Ta=25º C, 15pF Load Frequency vs. VDD + /-10% 15pF Load, 10/90% VDD, High Drive, 3.3V 15pF Load, 90/10% VDD, High Drive, 3.3V 45 -2 1.2 1.2 50 70 2 10 2 2 1.7 1.7 55 ms ns ms ppm ns ns % ps D uty Cycle PLL Enabled, @ VDD / 2 P eriod Jitter,Pk-to-Pk* With capacitive decoupling between VDD a nd (measured from 10,000 GND. samples) * N ote: Jitter performance depends on the programming parameters. 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 12/12/06 Page 4 ( Preliminary) PL611s-08 L ow-Power Programmable Quick Turn Clock T M D C SPECIFICATIONS PARAMETERS S upply Current, Dynamic, with Loaded CMOS Outputs S upply Current, Dynamic, with Loaded CMOS Outputs S upply Current, Dynamic with Loaded CMOS Outputs S upply Current, Dynamic, with Loaded Outputs O perating Voltage O utput Low Voltage O utput High Voltage O utput Current, Low Drive O utput Current, Standard Drive O utput Current, High Drive S hort-Circuit Current SYMBOL I DD I DD I DD I DD V DD V OL V OH I OSD I OSD I OHD IS CONDITIONS @ VDD = 3.3V, 27MHz, load=15pF @ VDD = 2.5V, 27MHz, load=15pF @ VDD = 1.8V,27MHz, load=5pF W hen PDB=0 MIN. TYP. 5.5 3.5 1.8* MAX. UNITS mA mA mA 1 inch) to a CMOS output, it is important to design the traces as a transmission line or ‘stripline’, to avoid reflections or ringing. In this case, the CMOS output needs to be matched to the trace impedance. Usually ‘striplines’ are designed for 50 impedance and CMOS outputs usually have lower than 50 impedance so matching can be achieved by adding a resistor in series with the CMOS output pin to the ‘stripline’ trace. - Please contact PhaseLink for additional information on how to design outputs driving long traces or for additional application assistance. D FN-6L Evaluation Board 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 12/12/06 Page 6 ( Preliminary) PL611s-08 L ow-Power Programmable Quick Turn Clock T M PACKAGE DRAWINGS ( GREEN P ACKAGE COMPLIANT) SOT23-6L Symbol A A1 A2 b c D E H L e SC70-6L Symbol A A1 A2 b c D E H L e DFN-6L D1 Dimension in MM Min. Max. 1.05 1.35 0.05 0.15 1.00 1.20 0.30 0.50 0.08 0.20 2.80 3.00 1.50 1.70 2.60 3.0 0.35 0.55 0.95 BSC Pin1 Dot E H D A2 A A1 e b C L Dimension in MM Min. Max. 0.80 1.00 0.00 0.09 0.80 0.91 0.15 0.30 0.08 0.25 1.85 2.25 1.15 1.35 2.00 2.30 0.21 0.41 0.65BSC Pin1 Dot E H D A2 A A1 e b C L Symbol A A1 A3 b e D E D1 E1 L Dimension in MM Min. Max. 0.50 0.60 0.00 0.05 0.152 0.152 0.15 0.25 0.40BSC 1.25 1.35 1.95 2.05 0.75 0.85 0.95 1.05 0.20 0.30 b e Pin 6 ID Chamfer E1 E D L Pin1 Dot A A1 A3 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 12/12/06 Page 7 ( Preliminary) PL611s-08 L ow-Power Programmable Quick Turn Clock T M O RDERING INFORMATION ( GREEN P ACKAGE COMPLIANT) For part ordering, please contact our Sales Department: 4 7745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 P ART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range P L611s-08-XXX X X X P ART NUMBER 3 DIGIT ID Code * (will be assigned at programming time) PACKAGE TYPE G=DFN-6L U=SC70-6L T=SOT-6L Part Number/Order Number PL611s-08-XXXGC-R PL611s-08-XXXUC-R PL611s-08-XXXTC-R † NONE= TUBE R=TAPE and REEL T EMPERATURE C=COMMERCIAL I=INDUSTRIAL Marking† XXX XXX 08XXX Package Option 6-Pin DFN (Tape and Reel) 6-Pin SC70 (Tape and Reel) 6-Pin SOT23 (Tape and Reel) N ote: ‘XXX’ designates marking identifier that could be independent of the part number. P haseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. L IFE SUPPORT POLICY : PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. S older reflow profile available at w ww.phaselink.com/QA/solderingGreen.pdf 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 12/12/06 Page 8