PL611S-16-XXXGC-R

( Preliminary) PL611s-16 1 .8V-3.3V PicoPLL TM 3 2K Programmable Clock F EATURES • D esigned for Very Low-Power applications o < 1.2mA @ 27MHz o < 5µA when PDB is activated • I nput Frequency: 10KHz – 200MHz • O TP selectable AC/DC Ref. Coupling. • A ccepts 10KHz and produce a clock output in the MHz range, as shown in the diagram ‘1’, below. However, to save costs in consumer product system designs and for greater area optimization, it is possible to use the XOUT of the RTC crystal (32.768KHz) as the reference input to the PL611s-16, as shown in diagram ‘2’, below. XIN REFIN C1 LF LPGND MHZ CLK (Any Frequency PL611s15 XIN 32.768K Hz ASIC C2 XOUT XOUT 1.8~3.3V REFIN LF LPGND MHZ CLK (Any Frequency) PL611s15 1.8~3.3V D iagram ‘1’ N ote: An AC Coupling Cap may be required if RTC Clock amplitude is too small. D iagram ‘2’ 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 07/18/06 Page 2 ( Preliminary) PL611s-16 1 .8V-3.3V PicoPLL TM 3 2K Programmable Clock E LECTRICAL SPECIFICATIONS A BSOLUTE MAXIMUM RATINGS P ARAMETERS S upply Voltage Range I nput Voltage Range O utput Voltage Range D ata Retention @ 85 ° C S torage Temperature A mbient Operating Temperature TS SYMBOL V DD VI VO MIN. MAX. 4.6 V DD + 0.5 V DD + 0.5 UNITS V V V Year - 0.5 - 0.5 - 0.5 10 - 65 -40 150 85 °C °C Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. A C SPECIFICATIONS PARAMETERS I nput Frequency (FIN) O utput Frequency O utput Frequency O utput Frequency S ettling Time I nput (FIN) Signal Amplitude O utput Rise Time O utput Fall Time D uty Cycle CONDITIONS Reference Clock Input @ Vdd=3.3V @ Vdd=2.5V @ Vdd=1.8V At power-up (after VDD increases over 1.62V) Internally AC coupled 15pF Load, 10/90%VDD, High Drive, 3.3V 15pF Load, 90/10%VDD, High Drive, 3.3V VDD/2 MIN. 10KHz 1 1 1 TYP. MAX. 200 55 45 35 2 UNITS MHz MHz MHz MHz ms Vpp ns ns % 0.9 1 1 45 50 VDD 1.2 1.2 55 * N ote: Jitter performance depends on the programming parameters. 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 07/18/06 Page 3 ( Preliminary) PL611s-16 1 .8V-3.3V PicoPLL TM 3 2K Programmable Clock D C SPECIFICATIONS PARAMETERS S upply Current, Dynamic, with Loaded CMOS Outputs S upply Current, Dynamic, with Loaded CMOS Outputs S upply Current, Dynamic with Loaded CMOS Outputs O perating Voltage O utput Low Voltage O utput High Voltage O utput Current, Low drive O utput Current, Standard drive O utput Current, High drive S hort-circuit Current SYMBOL I DD I DD I DD V DD V OL V OH I OSD I OSD I OHD IS CONDITIONS @ Vdd=3.3V, 27MHz, load=15pF @ Vdd=2.5V, 27MHz, load=15pF @ Vdd=1.8V,27MHz, load=5pF MIN. TYP. 4.0 2.7 1.2 MAX. UNITS mA mA mA 1 .62 I OL = + 4mA Standard Drive I OH = - 4mA Standard Drive V OL = 0 .4V, V OH = 2 .4V V OL = 0 .4V, V OH = 2 .4V V OL = 0 .4V, V OH = 2 .4V V DD – 0 .4 3.3 3.63 0.4 4 8 16 V V V mA mA mA mA ± 50 PCB LAYOUT CONSIDERATIONS FOR PERFORMANCE OPTIMIZATION The following guidelines are to assist you with a performance optimized PCB design: - Keep all the PCB traces to PL611s-16 as short as possible, as well as keeping all other traces as far away from it as possible. - When a reference input clock is generated from a crystal (see diagram above), place the PL611s-16 ‘FIN’ as close as possible to the ‘Xout’ crystal pin. This will reduce the crosstalk between the reference input and the other signals. - Place the Loop Filter (LF) components as close to the package pin of PL611s-16 as possible. - Place a 0.01µF~0.1µF decoupling capacitor between VDD and GND, on the component side of the PCB, close to the VDD pin. It is not recommended to place this component on the backside of the PCB. Going through vias will reduce the signal integrity, causing additional jitter and phase noise. - It is highly recommended to keep the VDD and GND traces as short as possible. - When connecting long traces (> 1 inch) to a CMOS output, it is important to design the traces as a transmission line or ‘stripline’, to avoid reflections or ringing. In this case, the CMOS output needs to be matched to the trace impedance. Usually ‘striplines’ are designed for 50Ω impedance and CMOS outputs usually have lower than 50Ω impedance so matching can be achieved by adding a resistor in series with the CMOS output pin to the ‘stripline’ trace. - Please contact PhaseLink for the application note on how to design outputs driving long traces or the Gerber files for the PL611s-16 layout. 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 07/18/06 Page 4 ( Preliminary) PL611s-16 1 .8V-3.3V PicoPLL TM 3 2K Programmable Clock P ACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT) SOT23-6 L Symbol A A1 A2 b c D E H L e SC70-6L Symbol A A1 A2 b c D E H L e DFN-6L D1 Dimension in MM Min. Max. 1.05 1.35 0.05 0.15 1.00 1.20 0.30 0.50 0.08 0.20 2.80 3.00 1.50 1.70 2.60 3.0 0.35 0.55 0.95 BSC Pin1 Dot E H D A2 A A1 e b C L Dimension in MM Min. Max. 0.80 1.00 0.00 0.09 0.80 0.91 0.15 0.30 0.08 0.25 1.85 2.25 1.15 1.35 2.00 2.30 0.21 0.41 0.65BSC Pin1 Dot E H D A2 A A1 e b C L Symbol A A1 A3 b e D E D1 E1 L Dimension in MM Min. Max. 0.50 0.60 0.00 0.05 0.152 0.152 0.15 0.25 0.40BSC 1.25 1.35 1.95 2.05 0.75 0.85 0.95 1.05 0.20 0.30 b e Pin 6 ID Chamfer E1 E D L Pin1 Dot A A1 A3 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 07/18/06 Page 5 ( Preliminary) PL611s-16 1 .8V-3.3V PicoPLL TM 3 2K Programmable Clock O RDERING INFORMATION (GREEN PACKAGE COMPLIANT) For part ordering, please contact our Sales Department: 4 7745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 P ART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range P L611s-XXX X X X P ART NUMBER 3 DIGIT ID Code * (will be assigned at programming time) PACKAGE TYPE T=SOT U=SC70 G=DFN Part Number PL611s-XXX PL611s-XXX PL611s-XXX † NONE= TUBE R=TAPE and REEL T EMPERATURE C=COMMERCIAL I = INDUSTRIAL Marking† 16XXX 16XXX 16XXX Package Option 6-Pin SC70 (Tape and Reel) 6-Pin SC70 (Tape and Reel) 6-Pin SOT-23 (Tape and Reel) Order Number PL611s-16-XXXGC-R PL611s-16-XXXUC-R PL611s-16-XXXTC-R N ote: ‘XXX’ designates marking identifier that could be independent of the part number. P haseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. L IFE SUPPORT POLICY : PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 07/18/06 Page 6