PL611S-18-XXXUC

( Preliminary) PL611s-18 0 .5kHz-125MHz MHz to KHz Programmable Clock T M F EATURES • D esigned for Very Low-Power applications • O ffered in Tiny GREEN/RoHS compliant packages o 6 -pin DFN (2.0mmx1.3mmx0.6mm) o 6 -pin SC70 (2.3mmx2.25mmx1.0mm) o 6 -pin SOT23 (3.0mmx3.0mmx1.35mm) • A ccepts Crystal or Reference Clock inputs • I nput Frequency: o F undamental crystal: 10MHz to 50MHz o R eference Input: 1MHz to 125MHz • A ccepts >0.1V reference signal input voltage • O utput Frequency 0.5kHz to 125MHz CMOS. o 6 5MHz @ 1.8V operation o 9 0MHz @ 2.5V operation o 1 25MHz @ 3.3V operation • O ne programmable I/O pin can be configured as OE, PDB, FSEL or CLK1 • L ow current consumption: o < 1.0mA with 27MHz & 32kHz outputs o < 5 A when PDB is activated • S ingle 1.8V, 2.5V, or 3.3V ± 10% power supply • O perating temperature range from -40 ° C to 85 ° C D ESCRIPTION T he PL611s-18 is a low-cost general purpose frequency synthesizer and a member of PhaseLink’s PicoPLL family, the worlds smallest programmable clocks. PhaseLink’s PL611s-18 offers the versatility of using a single Crystal (MHz) or Reference Clock input and producing up to two (kHz/MHz) system clocks, or a combination of Reference and low frequency outputs. The PL611s-18 is designed for low-power applications with very stringent space requirements and consumes ~1.0mA, while producing 2 distinct outputs of 27MHz and 32kHz. The power down feature of PL611s-18, when activated, allows the IC to consume less than 5 A of power. The PL611s-18 fits in a small DFN, SC70, or SOT23 package. Cascading of the PL611s-18 with other PhaseLink programmable clocks allow generating system level clocking requirements, thereby reducing the overall system implementation cost. In addition, one programmable I/O pin can be configured as Output Enable (OE), Frequency switching (FSEL), Power Down (PDB) input, or CLK1 (CLK0, F REF , F REF /2) output. B LOCK DIAGRAM XIN/FIN XOUT XTAL OSC Programmable CLoad FREF R-Counter (5-bit) M-Counter (8-bit) Phase Detector Charge Pump Loop Filter F VCO = F REF * (2 * M/R) VCO FOUT = F VCO / (2 * P) Programmable Function P-Counter (14-bit) CLK Programming Logic OE, PDB, FSEL, CLK1 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 2/23/07 Page 1 ( Preliminary) PL611s-18 0 .5kHz-125MHz MHz to KHz Programmable Clock T M K EY PROGRAMMING PARAMETERS CLK Output Frequency FOUT = FREF * M / (R * P) Where M=8 bit R= 5 bit P= 14 bit CLK0 = FOUT, FREF or FREF / (2*P) CLK1 = FREF, FREF/2, CLK0 or CLK0/2 Output Drive Strength Three optional drive strengths to choose from: • Low: 4mA • Std: 8mA (default) • High: 16mA Programmable Input/Output One output pin can be configured as: • • • • • OE - input FSEL - input PDB – input CLK1 – output Programmable CLoad P ACKAGE PIN CONFIGURATION AND ASSIGNMENT CLK0 CLK0 PL611s-18 PL611s-18 PL611s-18 1 2 3 6 5 4 1 2 3 6 5 4 VDD OE, PDB, FSEL, CLK1 PL611s-18 PL611s-18 PL611s-18 PL611s-18 VDD OE, PDB, FSEL, CLK1 PL611s-18 PL611s-18 PL611s-18 PL611s-18 XIN/FIN GND CLK0 1 2 3 6 5 4 XOUT OE,PDB,FSEL,CLK1 GND XIN/FIN GND XIN/FIN VDD XOUT XOUT SOT23 23SOT23-6L (3.0mmx3.0mmx1.35mm) mmx3 mmx1 35mm) mm DFNDFN-6L (2.0mmx1.3mmx0.6mm) mmx1 mmx0 mm) SC70 70SC70-6L (2.3mmx2.25mmx1.0mm) mmx2 25mmx1 mm) mmx N ame X IN, FIN G ND C LK0 V DD P in Assignment DFN SC70 SOT Pin # Pin# Pin# 1 2 3 4 3 2 1 6 3 2 1 6 Type I P O P Description Crystal or Reference input pin. GND connection Programmable Clock Output VDD connection This programmable I/O pin can be configured as an Output Enable (OE) input, Power Down input (PDB), Frequency Select input (FSEL) or CLK1 output. This pin has an internal 60K pull up resistor on OE, PDB and FSEL. S tate 0 1 ( default) OE T ri-state CLK Operating mode PDB Power Down Mode Operating mode FSEL Bank 0 Bank 1 O E, PDB, FSEL, CLK1 5 5 5 I/O X OUT 6 4 4 O Crystal Output pin. Do Not Connect if FIN is used. 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 2/23/07 Page 2 ( Preliminary) PL611s-18 0 .5kHz-125MHz MHz to KHz Programmable Clock T M F UNCTIONAL DESCRIPTION P L611s-18 is a highly featured, very flexible, advanced programmable PLL design for high performance, lowpower, small form-factor applications. The PL611s-18 accepts a crystal input of 10MHz to 50MHz or a reference clock input of 1MHz to 125MHz and is capable of producing two outputs up to 125MHz. This flexible design allows the PL611s-18 to deliver any PLL generated frequency, F REF ( Crystal or Ref Clk) frequency or F REF / (2*P) to CLK0 and/or CLK1. Some of the design features of the PL611s-18 are mentioned below: P LL Programming T he PLL in the PL611s-18 is fully programmable. The PLL is equipped with an 5-bit input frequency divider (R-Counter), and an 8-bit VCO frequency feedback loop divider (M-Counter). The output of the PLL is transferred to a 14-bit post VCO divider (P-Counter). The output frequency is determined by the following formula [FOUT = FREF * M / (R * P) ]. C lock Output (CLK0) C LK0 is the main clock output. The PL611s-18 can also be programmed to provide a second clock output, CLK1, on the programmable I/O pin (see OE/PDB/FSEL/CLK1 pin description below). The output of CLK0 can be configured as the PLL output (F VCO /(2*P)), F REF ( Ref Clk Frequency) output, or F REF /(2*P) output. The output drive level can be programmed to Low Drive (4mA), Standard Drive (8mA) or High Drive (16mA). The maximum output frequency is 125MHz. Clock Output (CLK1) T he CLK1 feature allows the PL611s-18 to have an additional clock output. This output can be programmed to one of the following: FREF FREF / 2 CLK0 CLK0 / 2 Output Enable (OE) T he Output Enable feature allows the user to enable and disable the clock output(s) by toggling the OE pin. The OE pin incorporates a 60k pull up resistor giving a default condition of logic “1”. Pulling the OE pin low “0” will tri-state the output buffers. Power-Down Control (PDB) T he Power Down (PDB) feature allows the user to put the PL611s-18 into “Sleep Mode”. When activated (logic ‘0’), PDB ‘Disables the PLL, the oscillator circuitry, counters, and all other active circuitry and tri-state the output buffers. In Power Down mode the IC consumes 50MHz. Typical CMOS termination Place Series Resistor as close as possible to CMOS output CMOS Output Buffer ( Typical buffer impedance 20 Ω ) 50Ω line To CMOS Input Series Resistor Use value to match output buffer impedance to 50 Ω trace. Typical value 30 Ω 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 2/23/07 Page 6 ( Preliminary) PL611s-18 0 .5kHz-125MHz MHz to KHz Programmable Clock T M C rystal Tuning Circuit Series and parallel capacitors used to fine tune the crystal load to the circuit load . Crystal Cst XIN 1 Cpt 8 Cpt XOUT CST – Series Capacitor, used to lower circuit load to match crystal load . Raises frequency offset. This can be eliminated by using a crystal with a Cload of equal or greater value than the oscillator. CPT – Parallel Capacitors , Used to raise the circuit load to match the crystal load. Lowers frequency offset . 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 2/23/07 Page 7 ( Preliminary) PL611s-18 0 .5kHz-125MHz MHz to KHz Programmable Clock T M PACKAGE DRAWINGS ( GREEN P ACKAGE COMPLIANT) SOT23-6L Symbol A A1 A2 b c D E H L e SC70-6L Symbol A A1 A2 b c D E H L e DFN-6L D1 Dimension in MM Min. Max. 1.05 1.35 0.05 0.15 1.00 1.20 0.30 0.50 0.08 0.20 2.80 3.00 1.50 1.70 2.60 3.0 0.35 0.55 0.95 BSC Pin1 Dot E H D A2 A A1 e b C L Dimension in MM Min. Max. 0.80 1.00 0.00 0.09 0.80 0.91 0.15 0.30 0.08 0.25 1.85 2.25 1.15 1.35 2.00 2.30 0.21 0.41 0.65BSC Pin1 Dot E H D A2 A A1 e b C L Symbol A A1 A3 b e D E D1 E1 L Dimension in MM Min. Max. 0.50 0.60 0.00 0.05 0.152 0.152 0.15 0.25 0.40BSC 1.25 1.35 1.95 2.05 0.75 0.85 0.95 1.05 0.20 0.30 b e Pin 6 ID Chamfer E1 E D L Pin1 Dot A A1 A3 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 2/23/07 Page 8 ( Preliminary) PL611s-18 0 .5kHz-125MHz MHz to KHz Programmable Clock T M O RDERING INFORMATION ( GREEN P ACKAGE) For part ordering, please contact our Sales Department: 4 7745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 P ART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range P L611s-18-XXX X X X P ART NUMBER 3 DIGIT ID Code * (will be assigned at programming time) PACKAGE TYPE G=DFN-6L U=SC70-6L T=SOT-6L Part /Order Number PL611s-18-XXXGC-R PL611s-18-XXXUC-R PL611s-18-XXXTC-R † NONE= TUBE R=TAPE and REEL T EMPERATURE C=COMMERCIAL I = INDUSTRIAL Marking† XXX XXX 18XXX Package Option 6-Pin DFN (Tape and Reel) 6-Pin SC70 (Tape and Reel) 6-Pin SOT23 (Tape and Reel) N ote: ‘XXX’ designates marking identifier that, at times, could be independent of the part number. Please consult your PhaseLink sales for marking information. P haseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. L IFE SUPPORT POLICY : PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. S older reflow profile available at w ww.phaselink.com/QA/solderingGreen.pdf 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 2/23/07 Page 9