PL611S-28-XXXTC-R

( Preliminary) PL611s-28 1 .8V-3.3V PicoPLL TM , World’s Smallest Programmable Clock F EATURES • D esigned for Very Low-Power applications • O ffered in Tiny G REEN /RoHS compliant packages o 6 -pin DFN (2.0mmx1.3mmx0.6mm) o 6 -pin SC70 (2.3mmx2.25mmx1.0mm) o 6 -pin SOT23 (3.0mmx3.0mmx1.35mm) • I nput Frequency: o F undamental Crystal: 10MHz to 50MHz o R eference Input: 1MHz to 200MHz • A ccepts >0.1V reference signal input voltage • O utput Frequency: o < 65MHz @ 1.8V operation o < 90MHz @ 2.5V operation o < 125MHz @ 3.3V operation • D isabled outputs programmable as HiZ or Active Low. • L ow current consumption: o < 1.2mA @ 27MHz o < 5 A when PDB is activated • S ingle 1.8V, 2.5V, or 3.3V ± 10% power supply • O perating temperature range from -40 ° C to 85 ° C D ESCRIPTION T he PL611s-28 consumes very low-power while producing high performance clock outputs of up to 55MHz. Designed for low-power applications with very stringent space requirement, PL611s-28 consumes about 1.2mA, while producing 2 distinct outputs of 27MHz and 13.5MHz. Designed to fit in a small SOT, SC70, or SOT23 package for high performance applications, the PL611s-28 offers excellent phase noise and jitter performance. The power down feature of PL611s-28, when activated, allows the IC to consume less than 5 A of power, while its programming flexibility allows generating any output, using a low-cost crystal or reference input. In addition, one programmable I/O pin can be configured as Output Enable (OE), Frequency switching (FSEL), Power Down (PDB) input, or CLK1 (F OUT , F REF , F REF /2) output. P ACKAGE PIN CONFIGURATION GND XIN/FIN OE, PDB, FSEL, CLK1 GND 1 2 3 6 5 4 CLK0 VDD XOUT OE, PDB, FSEL, CLK1 GND XIN/FIN 1 2 3 6 5 4 CLK0 VDD XOUT PL611s-28 PL611s-28 PL611s-28 PL611s-28 PL611s-28 PL611s-28 PL611s-28 PL611s-28 1 2 3 6 5 4 XOUT VDD CLK0 OE, PDB, FSEL, CLK1 XIN/FIN DFNDFN-6L (2.0mmx1.3mmx0.6mm) mmx1 mmx0 mm) BLOCK DIAGRAM XIN/FIN XOUT XTAL F ref R-counter (8-Bit) OSC M-counter (11-Bit) Programmable CLoad Programmable Function 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 3/9/07 Page 1 PL611s-28 SC70 70SC70-6L (2.3mmx2.25mmx1.0mm) mmx2 25mmx1 mm) mmx SOT23 23SOT23-6L (3.0mmx3.0mmx1.35mm) mmx3 mmx1 35mm) mm Phase Detector Charge Pump Loop Filter Fvco= Fref * (2 * M / R) VCO Fout= Fvco / (2 * P) P-counter (5-Bit) CLK0 Programming Logic OE, FSEL, PDB, CLK1 ( Preliminary) PL611s-28 1 .8V-3.3V PicoPLL TM , World’s Smallest Programmable Clock K EY PROGRAMMING PARAMETERS CLK[0:1] Output Frequency FOUT = FREF * M / (R * P) Where M = 11 bit R = 8 bit P = 5 bit CLK0 = FOUT, FREF or FREF / (2*P) CLK1 = FREF, FREF/2, CLK0 or CLK0/2 Output Drive Strength Three optional drive strengths to choose from: • Low: 4mA • Std: 8mA (default) • High: 16mA Programmable Input/Output One output pin can be configured as: • • • • OE - input PDB - input FSEL – input HiZ or Active Low disabled state P ACKAGE PIN ASSIGNMENT N ame P in Assignment SOT SC70 DFN Pin # Pin# Pin# Type Description This programmable I/O pin can be configured as an Output Enable (OE) input, Power Down (PDB) input, On-the-Fly Frequency Switching Selector (FSEL)input or CLK1 clock output. This pin has an internal 60K pull up resistor (OE, PDB & FSEL Only). O E, PDB, FSEL, CLK1 1 2 2 I/O The OE and PDB features can be programmed to allow the output to float (Hi Z), or to operate in the ‘Active low’ mode. S tate 0 1 ( default) G ND X IN, FIN X OUT V DD C LK0 2 3 4 5 6 1 3 4 5 6 3 1 6 5 4 P I O P O GND connection Crystal or Reference input pin C rystal Output pin Do Not Connect (DNC ) when FIN is present VDD connection Programmable Clock Output OE D isable CLK Normal mode PDB Power Down Mode Normal mode FSEL Frequency ‘2’ Frequency ‘1’ 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 3/9/07 Page 2 ( Preliminary) PL611s-28 1 .8V-3.3V PicoPLL TM , World’s Smallest Programmable Clock F UNCTIONAL DESCRIPTION P L611s-28 is a highly featured, very flexible, advanced programmable PLL design for high performance, lowpower, small form-factor applications. The PL611s-28 accepts a fundamental input crystal of 10MHz to 50MHz or reference clock input of 1MHz to 200MHz and is capable of producing two outputs up to 125MHz. This flexible design allows the PL611s-28 to deliver any PLL generated frequency, F REF ( Crystal or Ref Clk) frequency or F REF / (2*P) to CLK0 and/or CLK1. Some of the design features of the PL611s-28 are mentioned below: P LL Programming T he PLL in the PL611s-28 is fully programmable. The PLL is equipped with an 8-bit input frequency divider (R-Counter), and an 11-bit VCO frequency feedback loop divider (M-Counter). The output of the PLL is transferred to a 5-bit post VCO divider (PCounter). The output frequency is determined by the following formula [F OUT = F REF * M / ( R * P) ]. C lock Output (CLK0) C LK0 is the main clock output. The output of CLK0 can be configured as the PLL output (F VCO /(2*P)), F REF ( Crystal or Ref Clk Frequency) output, or F REF /(2*P) output. Clock Output (CLK1) T he CLK1 feature allows the PL611s-28 to have an additional clock output. This output can be programmed to one of the following: FREF - Reference (Crystal or Ref Clk) Frequency FREF / 2 CLK0 CLK0 / 2 The output drive level can be programmed to Low Drive (4mA), Standard Drive (8mA) or High Drive (16mA) for each clock independently. The maximum output frequency is 125MHz. Output Enable (OE) T he Output Enable feature allows the user to enable and disable the clock output(s) by toggling the OE pin. The OE pin incorporates a 60k pull up resistor giving a default condition of logic “1”. The OE feature can be programmed to allow the output to float (Hi Z), or to operate in the ‘Active low’ mode. Power-Down Control (PDB) T he Power Down (PDB) feature allows the user to put the PL611s-28 into “Sleep Mode”. When activated (logic ‘0’), PDB ‘Disables the PLL, the oscillator circuitry, counters, and all other active circuitry. In Power Down mode the IC consumes 50MHz. Typical CMOS termination Place Series Resistor as close as possible to CMOS output CMOS Output Buffer ( Typical buffer impedance 20 50 line To CMOS Input Series Resistor Use value to match output buffer impedance to 50 trace. Typical value 30 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 3/9/07 Page 6 ( Preliminary) PL611s-28 1 .8V-3.3V PicoPLL TM , World’s Smallest Programmable Clock 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 3/9/07 Page 7 ( Preliminary) PL611s-28 1 .8V-3.3V PicoPLL TM , World’s Smallest Programmable Clock PACKAGE DRAWINGS ( GREEN P ACKAGE COMPLIANT) SOT23-6L Symbol A A1 A2 b c D E H L e SC70-6L Symbol A A1 A2 b c D E H L e DFN-6L D1 Dimension in MM Min. Max. 1.05 1.35 0.05 0.15 1.00 1.20 0.30 0.50 0.08 0.20 2.80 3.00 1.50 1.70 2.60 3.00 0.35 0.55 0.95 BSC Pin1 Dot E H D A2 A A1 e b C L Dimension in MM Min. Max. 0.80 1.00 0.00 0.09 0.80 0.91 0.15 0.30 0.08 0.25 1.85 2.25 1.15 1.35 2.00 2.30 0.21 0.41 0.65BSC Pin1 Dot E H D A2 A A1 e b C L Symbol A A1 A3 b e D E D1 E1 L Dimension in MM Min. Max. 0.50 0.60 0.00 0.05 0.152 0.152 0.15 0.25 0.40BSC 1.25 1.35 1.95 2.05 0.75 0.85 0.95 1.05 0.20 0.30 b e Pin 6 ID Chamfer E1 E D L Pin1 Dot A A1 A3 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 3/9/07 Page 8 ( Preliminary) PL611s-28 1 .8V-3.3V PicoPLL TM , World’s Smallest Programmable Clock O RDERING INFORMATION ( GREEN P ACKAGE) For part ordering, please contact our Sales Department: 4 7745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 P ART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range P L611s-28-XXX X X X P ART NUMBER 3 DIGIT ID Code * (will be assigned at programming time) PACKAGE TYPE G=DFN-6L U=SC70-6L T=SOT23-6L Part/Order Number PL611s-28-XXXGC-R PL611s-28-XXXUC-R PL611s-28-XXXTC-R † NONE= TUBE R=TAPE and REEL T EMPERATURE C=COMMERCIAL I = INDUSTRIAL Marking† XXX XXX 28XXX Package Option 6-Pin DFN (Tape and Reel) 6-Pin SC70 (Tape and Reel) 6-Pin SOT23 (Tape and Reel) N ote: ‘XXX’ designates marking identifier that, at times, could be independent of the part number. Please consult your PhaseLink sales for marking information. P haseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. L IFE SUPPORT POLICY : PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. S older reflow profile available at w ww.phaselink.com/QA/solderingGreen.pdf 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 3/9/07 Page 9