PL612-05-XXXMCR

( Preliminary ) 1.8V - 3.3V PicoPLL , 2 - PLL, 200MHz, 5 Output Clock IC FEATURES  Designed for PCB space savings with 2 low - power Programmable PLLs and up to 5 clock outputs.  Low - power consumption ( 50MHz. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492 - 0990 Fax (510) 492 - 0991 www.phaselink .com Rev 9/4 /07 Page 4 ( Preliminary ) 1.8V - 3.3V PicoPLL , 2 - PLL, 200MHz, 5 Output Clock IC 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492 - 0990 Fax (510) 492 - 0991 www.phaselink .com Rev 9/4 /07 Page 5 ( Preliminary ) 1.8V - 3.3V PicoPLL , 2 - PLL, 200MHz, 5 Output Clock IC ELECTRICAL SPECIFICATION S ABSOLUTE MAXIMUM RATINGS PARAMETERS Supply Voltage Range Input Voltage Range Output Voltage Range Soldering Temperature (Green package) Data Retention @ 85  C Storage Temperature Ambient Operating Temperature* TS 10 - 65 - 40 150 85 SYMBOL V DD VI VO MIN. - 0.5 - 0.5 - 0.5 MAX. 4.6 V DD +0.5 V DD +0.5 260 UNITS V V V C Year C C Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only. AC S PECIFICATION S PARAMETERS Crystal Input Frequency (XIN) Input (FIN) Frequency Input (FIN) Signal Amplitude Input (FIN) Signal Amplitude @ V DD =3.3V @ V DD =2.5V @ V DD =1.8V Internally AC coupled (High Frequency) Internally AC coupled (Low Frequency) 3.3V < 50MHz, 2.5V < 40MHz, 1.8V < 15MHz @ VDD =3.3V Output Frequency Settling Time Output Enable Time VDD Sensitivity Output Rise Time Output Fall Time Duty Cycle Period Jitter, Pk - to - Pk* (10,000 samples) @ VDD =2.5V @ VDD =1.8V At power - up (after VDD increases ove r 1.62V) OE Function; Ta=25 º C, 15pF Load PDB Function; Ta=25 º C, 15pF Load Frequency vs. VDD +/ - 10% 15pF Load, 10/90% VDD, High Drive, 3.3V 15pF Load, 90/10% VDD, High Drive, 3.3V PLL Enabled, @ VDD /2 Input 16MHz fundamental mode crystal, all outputs at 40MHz, 10pF Load, with capacitive decoupling between V DD and GND. 45 -2 1.2 1.2 50 100 0.9 0.1 1 CONDITIONS Fundamental Crystal MIN. 10 TYP. MAX. 50 200 166 133 VDD VDD 200 166 133 2 10 2 2 1.7 1.7 55 120 ms ns ms ppm ns ns % ps MHz Vp p Vpp MHz UNITS MHz * Note: Jitter performance depends on the programming parameters. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492 - 0990 Fax (510) 492 - 0991 www.phaselink .com Rev 9/4 /07 Page 6 ( Preliminary ) 1.8V - 3.3V PicoPLL , 2 - PLL, 200MHz, 5 Output Clock IC DC SPECIFICATION S PARAMETERS Supply Current, Dynamic, with Loaded CMOS Outputs Supply Current, Dynamic, with Loaded CMOS Outputs Supply Current, Dynamic with Loaded CMOS Outputs Supply Current, Dynamic, with Loaded Outputs Operating Voltage Output Low Voltage Output High Voltage Output Current, Low Drive Output Current, St d Drive Output Current, High Drive SYMBOL I DD I DD I DD I DD CONDITIONS All outputs @ 20MHz , 10pF Load, V DD = 3.3V All outputs @ 20MHz , 10pF Load, V DD = 2.5 V All outputs @ 20MHz , 10pF Load, V DD = 1.8V When PDB=0 3.3V Operation V DD V OL V OH I OSD I OSD I OHD 2.5V Operation 1.8V Operation I OL = +4mA Std. Drive I OH = - 4mA Std. D rive V OL = 0.4V, V OH = 2.4V V OL = 0.4V, V OH = 2.4V V OL = 0.4V, V OH = 2.4V V DD – 0.4 4 8 16 2.97 2.25 1.62 3.3 2.5 1.8 MIN. TYP. 13 9 6.5 MAX. 19 14 9