PL66X-XXOCL-R

A nalog Frequency Multiplier P L660 and PL663 X O Families DESCRIPTION PhaseLink’s Analog Frequency Multipliers (AFMs) are the industry’s first “Balanced Oscillator” utilizing analog multiplication of the fundamental frequency (at double or quadruple frequency), combined with an attenuation of the fundamental of the reference crystal, without using a phase-locked loop (PLL), in CMOS technology. PhaseLink’s patent pending PL66x family of AFM products can achieve up to 800 MHz differential PECL, LVDS, or single-ended CMOS output with little jitter or phase noise deterioration. PL66x-xx family of products utilize a low-power CMOS technology and are housed in GREEN/ RoHS compliant 16-pin TSSOP and 3x3 QFN packages. TM FEATURES • • • • • Non-PLL frequency multiplication Input frequency from 30-200 MHz Output frequency from 60-800 MHz Low phase noise and jitter (equivalent to fundamental at the output frequency) Ultra-low jitter o RMS phase jitter < 0.25 ps (12 kHz to 20 MHz) o RMS period jitter < 2.5 ps typ. Low phase noise o -145 dBc/Hz @ 100 kHz offset from 155.52 MHz o -150 dBc/Hz @ 10 MHz offset from 155.52 MHz Low input frequency eliminates the need for expensive crystals Differential PECL/LVDS, or single-ended CMOS output Single 2.5V or 3.3V +/- 10% power supply Optional industrial temperature range (-40°C to +85°C) Available in 16-pin GREEN/RoHS compliant TSSOP, and 16-pin 3x3 QFN packages. • • • • • • Figure 1: 2X AFM Phase Noise at 212.5 MHz (106.25 MHz 3 overtone crystal) rd 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 1 A nalog Frequency Multiplier P L660 and PL663 X O Families L2X OE X IN R XOUT O n ly r e q u ir e d in x 4 d e s ig n s L4X O s c illa t o r A m p lif ie r F re q u e n c y X2 F re q u e n c y X4 QBAR Q Figure 2: Block Diagram of AFM XO Figure 3 shows the period jitter histogram of the 2x Analog Frequency Multiplier at 212.5 MHz, while Figure 4 shows the very low levels of sub-harmonics that correspond to the exceptional performance (i.e. low jitter). Figure 3: Period Jitter Histogram at 212.5MHz A nalog Frequency Multiplier (2x), with 106.25 MHz crystal Figure 4: Spectrum Analysis at 212.5MHz Analog Frequency Multiplier (2x), with sub-harmonics below –69 dBc O E LOGIC SELECTION OUTPUT PECL 1 0 (Default) LVDS or CMOS 1 OESEL 0 (Default) OE 0 (Default) 1 0 1 (Default) 0 1 (Default) 0 (Default) 1 Output State Enabled Tri-state Tri-state Enabled Tri-state Enabled Enabled Tri-state O ESEL and OE: Connect to VDD to set to “1”, connect to GND to set to “0”. [The ‘Default’ state is set by internal pull up/down resistor.] 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 2 A nalog Frequency Multiplier P L660 and PL663 X O Families P RODUCT SELECTOR GUIDE FREQUENCY VERSUS PHASE NOISE PERFORMANCE Part Number Input Frequency Range (MHz) 30 - 80 30 - 80 30 - 80 30 - 80 30 - 80 75 - 140 75 - 140 75 - 140 140 - 160 140 - 160 Analog Frequency Multiplication Factor 4 4 2 2 2 2 2 2 2 2 Output Frequency Range (MHz) 120 - 320 120 - 320 60 - 160 60 - 160 60 - 160 150 - 280 150 - 280 150 - 280 280 - 320 280 - 320 Phase Noise at Frequency Offset From Carrier (dBc/Hz) Output Type Carrier Freq. (MHz) 155.52 155.52 156.25 156.25 156.25 212.5 212.5 212.5 311.04 311.04 10 Hz -72 -72 -75 -75 -75 -70 -70 -70 -60 -60 100 Hz -100 -100 -105 -105 -105 -100 -100 -100 -92 -92 1 KHz -125 -125 -130 -130 -130 -130 -130 -130 -122 -122 10 KHz -132 -132 -140 -140 -140 -140 -140 -140 -140 -140 100 KHz -142 -142 -145 -145 -145 -145 -145 -145 -142 -142 1 MHz -147 -147 -150 -150 -150 -148 -148 -148 -146 -146 10 MHz -149 -149 -150 -150 -150 -148 -148 -148 -146 -148 PL660-08 PL660-09 PL663-07 PL663-08 PL663-09 PL663-17 PL663-18 PL663-19 PL663-28 PL663-29 PECL LVDS CMOS PECL LVDS CMOS PECL LVDS PECL LVDS F REQUENCY VERSUS JITTER, AND SUB-HARMONIC PERFORMANCE RMS Period Jitter (ps) Peak to Peak Period Jitter (ps) RMS Accumulated (L.T.) Jitter (ps) Phase Jitter (12 KHz-20MHz) (ps) Spectral Specifications / Sub-harmonic Content (dBc) Frequency (MHz) Carrier Freq. MHz (Fc) 155.52 155.52 156.25 156.25 156.25 212.50 212.50 212.50 311.04 311.04 @ -75% (Fc) -66 -66 @ -50% (Fc) -61 -61 -70 -70 -70 -70 -70 -70 -65 -65 @ -25% (Fc) @ +25% (Fc) @ +50% (Fc) -67 -67 -75 -75 -75 -75 -75 -75 -70 -70 @ +75% (Fc) -70 -70 Part Number Output Freq. (MHz) Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. PL660-08 PL660-09 PL663-07 PL663-08 PL663-09 PL663-17 PL663-18 PL663-19 PL663-28 PL663-29 155.52 155.52 156.25 156.25 156.25 212.50 212.50 212.50 311.04 311.04 3 3 2 2 2 2.5 2.5 2.5 2.5 2.5 5 5 3 3 3 4 4 4 4 4 21 21 18 18 18 18 18 18 18 18 30 30 20 20 20 20 20 20 20 20 5 5 3 3 3 4 4 4 4 4 0.25 0.25 0.24 0.24 0.24 0.19 0.19 0.19 0.16 0.16 N ote: W avecrest data 10,000 hits. No Filtering was used in Jitter Calculations. Agilent E5500 was used for phase jitter measurements. Spectral specifications were obtained using Agilent E7401A. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 3 A nalog Frequency Multiplier P L660 and PL663 X O Families B OARD LAYOUT CONSIDERATIONS AND CRYSTAL SPECIFICATIONS B OARD LAYOUT CONSIDERATIONS To minimize parasitic effects and improve performance, do the following: • Place the crystal as close as possible to the IC. • Make the board traces that are connected to the crystal pins symmetrical. The board trace symmetry is very important, as it reduces the negative parasitic effects to produce clean frequency multiplication with low jitter. C RYSTAL SPECIFICATIONS Crystal Resonator Frequency (FXIN) 25~75MHz CL (xtal) Mode Typical Fundamental or 3rd overtone Fundamental or 3rd overtone Fundamental or 3rd overtone Fundamental or 3rd overtone Max. Max. Max. ESR(RE) C0 C0/C1 Part Number PL660-08 PL660-09 PL663-07 PL663-08 PL663-09 PL663-17 PL663-18 PL663-19 PL663-28 PL663-29 5 pF 30 Ω 4.5 pF N.A. 30~80MHz 5 pF 30 Ω 4.5 pF N.A. 75~140MHz 5 pF 60 Ω 4.0 pF N.A. 140~200MHz 5 pF 60 Ω 4.0 pF N.A. N ote: N on-specified parameters can be chosen as standard values from crystal suppliers. CL ratings larger than 5pF require a crystal frequency adjustment. Request detailed crystal specifications from PhaseLink. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 4 A nalog Frequency Multiplier P L660 and PL663 X O Families E XTERNAL COMPONENT VALUES INDUCTOR VALUE OPTIMIZATION The required inductor value(s) for the best performance depends on the operating frequency, and the board layout specifications. The listed values in this datasheet are based on the calculated parasitic values from PhaseLink’s evaluation board design. These inductor values provide the user with a starting point to determine the optimum inductor values. Additional fine-tuning may be required to determine the optimal solution. To assist with the inductor value optimization, PhaseLink has developed the “AFM Tuning Assistant” software. You can download this software from PhaseLink’s web site (www.phaselink.com). The software consists of two worksheets. The first worksheet (named L2) is used to fine-tune the ‘L2’ inductor value, and the second worksheet (named L4) is used for fine tuning of the ‘L4’ (used in 4x AFMs only) inductor value. For those designs using PhaseLink’s recommended board layout, you can use the “AFM Tuning Assistant” to determine the optimum values for the required inductors. This software is developed based on the parasitic information from PhaseLink’s board layout and can be used to determine the required inductor and parallel capacitor (see LWB1 and Cstray parameters) values. For those employing a different board layout in their design, we recommend to use the parasitic information of their board layout to calculate the optimized inductor values. Please use the following fine tuning procedure: Figure 5: Diagram Representation of the Related System Inductance and Capacitance DIE SIDE - Cinternal = Based on AFM Device - Cpad = 2.0 pF, Bond pad and its ESD circuitry - C11 = 0.4 pF, The following amplifier stage PCB side - LWB1 = 2 nH, (2 places), Stray inductance - Cstray = 1.0 pF, Stray capacitance - L2X (L4X) = 2x or 4x inductor - C2X (C4X) = range (0.1 to 2.7), Fine tune inductor if used 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 5 A nalog Frequency Multiplier P L660 and PL663 X O Families • There are two default variables that normally will not need to be modified. These are Cpad, and C11 and are found in cells B22 and B27 of ‘AFM Tuning Assistant’, respectively. • LWB1 is the combined stray inductance in the layout. The DIE wire bond is ~ 0.6 nH and in the case of a leaded part an additional 1.0 nH is added. Your layout inductance must be added to these. There are 2 of these and they are assumed to be approximately symmetrical so you only need to enter this inductance once in cell B23. • Enter the stray parasitic capacitance into cell B26. An additional 0.5 pF must be added to this value if a leaded part is used. • Enter the appropriate value for Cinternal into B21 based on the device used (see column D). Use the ‘AFM Tuning Assistant’ software to calculate L2X (and C2X if used) for your resonance frequency. • For 4X AFMs, repeat the same procedure in the L4X worksheet. • See the examples below. DETERMINING STRAY L’s AND C’s IN A LAYOUT Figure 6: Diagram Representation of PL660-08 Board Layout Let’s take the PL660-08 (4x XO) for example, as shown in Figure 6. This takes a crystal input range of 30 to 80 MHz and multiplies this to an output of 120 to 320 MHz. To determine the stray L’s and C’s of the layout we will assemble two test units. One AFM will be tuned to the lower range of the device (120 MHz), and the other to the upper range of the device (320 MHz). 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 6 A nalog Frequency Multiplier P L660 and PL663 X O Families 120 MHz AFM Tuning: Using the “AFM Tuning Assistant” find the PL660-0x in the L2X worksheet. Enter the Cinternal value found next to it into cell B21. In cell B24 enter the closest standard inductor value (see CoilCraft 0603CS series for example) to achieve the closest peak frequency to 60 MHz. Repeat the same procedure for L4X at 120 MHz. Results: L2X = 180 nH, L4X = 82 nH. 320 MHz AFM tuning: Repeat the previous procedure for L2X at 120 MHz and L4X at 320 MHz. Results: L2X = 24 nH, L4X = 10 nH. Proceed and assemble the test units. Measuring 120 MHz L2X: Connect the RF generator and scope probe as shown in Figure 6. While power is applied to the PCB, set the generator output to +12 dBm and the frequency to 30 MHz. Since this is the 2x port, the scope will show 60 MHz with ~ 3V pk-pk amplitude. Vary the generator above and below 30 MHz until the amplitude on the scope is maximum and record the generator frequency. For example peak recorded at 29.8x2 or 59.6 MHz. Measuring 320 MHz L2X: Connect the RF generator and scope probe as shown in Figure 6. While power is applied to the PCB, set the generator output to +12 dBm and the frequency to 80 MHz. Since this is the 2x port the scope will show 160 MHz with ~ 3V pk-pk amplitude. Vary the generator above and below 80 MHz until the amplitude on the scope is maximum and record the generator frequency. For example peak recorded at 78.0 x 2 = 156 MHz In the AFM Tuning Assistant, add the scope’s probe capacitance to the Cstray cell. For our example 0.5 pF + 1.0 pF = 1.5 pF. With L2X at 24 nH adjust LWB1 (cell B23) until the peak frequency reads 156 MHz. Next replace the L2X value with 180 nH and see if it peaks at 59.6 MHz. If it does not, adjust the Cstray until 59.4 MHz is achieved. Again enter 24 nH for L2X and fine tune LWB1 for 156 MHz. Results: LWB1 = 1.6 nH, Cstray = 2.9 pF-0.5 pF = 2.4 pF (subtract scope probe stray) Repeat the same steps for the L4X: Set the generator to 80 MHz. The 82 nH peaks at 118 MHz and the 10 nH peaks at 304 MHz. Results: LWB1 = 1.8 nH, Cstray = 2.5 pF-0.5 pF = 2.0 pF (subtract scope probe stray) Internal Capacitor Selection by Device Device Number PL660-0X PL663-0X PL663-1X PL663-2X Cinternal (pF) 2X 34.125 46.500 14.625 14.625 4X 16.500 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 7 A nalog Frequency Multiplier P L660 and PL663 X O Families E XTERNAL COMPONENT VALUES – 3 RD O VERTONE RESISTOR SELECTIONS (R3rd) This resistor is only required when a third overtone crystal is used. The chart below indicates the calculated and the nearest “E12” resistor values versus frequency. PL660-08/09 Freq. (MHz) 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 R3rd () 12,396 11,442 10,625 9,917 9,297 8,750 8,264 7,829 7,438 7,083 6,761 6,467 6,198 5,950 5,721 5,509 5,313 5,129 4,958 4,798 4,648 4,508 4,375 4,250 4,132 4,020 3,914 E12 Pick K 12 12 10 10 10 8.2 8.2 8.2 6.8 6.8 6.8 6.8 6.8 5.6 5.6 5.6 5.6 4.7 4.7 4.7 4.7 4.7 4.7 3.9 3.9 3.9 3.9 PL663-07/08/09 E12 Freq. R3rd Pick (MHz) () K 30 9,917 10 32 9,297 10 34 8,750 8.2 36 8,264 8.2 38 7,829 8.2 40 7,438 6.8 42 7,083 6.8 44 6,761 6.8 46 6,467 6.8 48 6,198 6.8 50 5,950 5.6 52 5,721 5.6 54 5,509 5.6 56 5,313 5.6 58 5,129 4.7 60 4,958 4.7 62 4,798 4.7 64 4,648 4.7 66 4,508 4.7 68 4,375 4.7 70 4,250 3.9 72 4,132 3.9 74 4,020 3.9 76 3,914 3.9 78 3,814 3.9 80 3,719 3.9 PL663-017/18/19 E12 Freq. R3rd Pick (MHz) () K 75 2,125 2.2 77.5 2,056 2.2 80 1,992 2.2 82.5 1,932 1.8 85 1,875 1.8 87.5 1,821 1.8 90 1,771 1.8 92.5 1,723 1.8 95 1,678 1.8 97.5 1,635 1.5 100 1,594 1.5 102.5 1,555 1.5 105 1,518 1.5 107.5 1,483 1.5 110 1,449 1.5 112.5 1,417 1.5 115 1,386 1.5 117.5 1,356 1.5 120 1,328 1.2 122.5 1,301 1.2 125 1,275 1.2 127.5 1,250 1.2 130 1,226 1.2 132.5 1,203 1.2 135 1,181 1.2 137.5 1,159 1.2 140 1,138 1.2 PL663-28/29 Freq. (MHz) 140.0 142.0 144.0 146.0 148.0 150.0 152.0 154.0 156.0 158.0 160.0 162.0 164.0 166.0 168.0 170.0 172.0 174.0 176.0 178.0 180.0 182.0 184.0 186.0 188.0 190.0 192.0 194.0 196.0 198.0 200.0 R3rd () 915 902 890 878 866 854 843 832 821 811 801 790 780 770 759 749 740 730 720 711 701 692 683 674 665 656 647 639 630 622 614 E24 Pick K 0.91 0.91 0.91 0.91 0.91 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.75 0.75 0.75 0.75 0.75 0.75 0.75 0.68 0.68 0.68 0.68 0.68 0.68 0.68 0.62 0.62 0.62 0.62 0.62 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 8 A nalog Frequency Multiplier P L660 and PL663 X O Families E LECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETERS S upply Voltage I nput Voltage, DC O utput Voltage, DC S torage Temperature I ndustrial Ambient Operating Temperature C ommercial Ambient Operating Temperature J unction Temperature L ead Temperature (soldering, 10s) SYMBOL V DD VI VO TS T A_I T A_C TJ M IN. MAX. 4 .6 UNITS V V V °C °C °C °C °C G ND-0.5 G ND-0.5 - 55 - 40 0 V DD +0.5 V DD +0.5 +150 +85 + 70 1 25 260 E xposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. PECL ELECTRICAL CHARACTERISTICS PARAMETERS Supply Current (with loaded outputs) Operating Supply Voltage Output Clock Duty Cycle Short Circuit Current Output High Voltage Output Low Voltage Clock Rise Time Clock Fall Time VOH VOL tr tf RL = 50 to VDD – 2V RL = 50 to VDD – 2V 0.25 0.25 VDD – 1.025 VDD – 1.620 0.45 0.45 SYMBOL IDD VDD CONDITIONS Fout = 212.5 MHz MIN. 58 2.25 TYP. 65 MAX. 75 3.63 UNITS mA V % mA V V ns ns @ VDD – 1.3V 45 50 ±50 55 @20/80% @80/20% PECL Levels Test Circuit OUT VDD PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% 50Ω 2.0V OUT 80% 50Ω 20% OUT OUT tR tF 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 9 A nalog Frequency Multiplier P L660 and PL663 X O Families L VDS ELECTRICAL CHARACTERISTICS PARAMETERS Supply Current (with loaded outputs) Operating Supply Voltage Output Clock Duty Cycle Output Differential Voltage VDD Magnitude Change Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change Power-off Leakage Output Short Circuit Current Differential Clock Rise Time Differential Clock Fall Time VOD ∆VOD VOH VOL VOS ∆VOS IOXD IOSD tr tf RL = 100 CL = 10 pF (see figure) 0.2 0.2 Vout = VDD or GND VDD = 0V RL = 100 (see figure) SYMBOL IDD VDD @ 1.25V CONDITIONS Fout = 212.5 MHz MIN. 2.25 45 247 -50 1.4 0.9 1.125 0 1.1 1.2 3 ±1 -5.7 0.5 0.5 1.375 25 ±10 -8 0.7 0.7 50 355 TYP. 55 MAX. 60 3.63 55 454 50 1.6 UNITS mA V % mV mV V V V mV A mA ns ns LVDS Transistion Time Waveform LVDS Levels Test Circuit OUT LVDS Switching Test Circuit OUT OUT 0V (Differential) OUT 50Ω CL = 10pF VOD VOS VDIFF RL = 100 Ω 80% VDIFF 0V 20% 80% 50Ω CL = 10pF 20% OUT OUT tR tF 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 10 A nalog Frequency Multiplier P L660 and PL663 X O Families C MOS ELECTRICAL CHARACTERISTICS PARAMETERS S upply Current, Dynamic, with Loaded Outputs O perating Supply Voltage O utput High Voltage (LVTTL) O utput Low Voltage (LVTTL) O utput High Voltage (LVCMOS) O utput High Voltage O utput Low Voltage Output drive current Output Clock Rise/Fall Time Output Clock Duty Cycle Short Circuit Current IS SYMBOL I DD V DD V OH3.3 V OL3.3 V OHC3.3 V OH2.5 V OL2.5 I OSD Tr/Tf I OH = - 8.5mA, 3.3V Supplies I OL = 8 .5mA, 3.3V Supplies I OH = - 4mA, 3.3V Supplies I OH = 1 mA, 2.5V Supplies I OL = 1 mA, 2.5V Supplies V OL = 0 .4V, V OH = 2 .4V (per output) 10% ~ 90% VDD with 10 pF load Measured @ 50% VDD 45 8.5 1.2 50 ±50 1.6 55 V DD – 0 .4 V DD – 0 .2 0.2 CONDITIONS A t 100MHz, load=15pF 2 .25 2.4 0.4 MIN. TYP. 32 MAX. 40 3.63 UNITS mA V V V V V V mA ns % mA 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 11 A nalog Frequency Multiplier P L660 and PL663 X O Families BOARD DESIGN AND LAYOUT CONSIDERATIONS L2X and L4X: Reduce the PCB trace inductance to a minimum by placing L2X and L4X as physically close to their respective pins as possible. Also be sure to bypass each VDD connection especially taking care to place a 0.01 uF bypass at the VDD side of L2X and L4X (see recommended layout). Crystal Connections: Be sure to keep the ground plane under the crystal connections continuous so that the stray capacitace is consistent on both crystal connections. Also be sure to keep the crystal connections symmetrical with respect to one another and the crystal connection pins of the IC. If you chose to use a series capacitance and/or inductor to fine tune the crystal frequency, be sure to put symmetrical pads for this cap on both crystal pins (see Cadj in recommended layout), even if one of the capacitors will be a 0.01 uF and the other is used to tune the frequency. To further maintain a symmetrical balance on a crystal that may have more internal Cstray on one pin or the other, place capacitor pads (Cbal) on each crystal lead to ground (see recommended layout). R3rd is only required if a 3rd overtone crystal is used. VDD and GND: Bypass VDDANA and VDDBUF with separate bypass capacitors and if a VDD plane is used, feed each bypass cap with its own via. Be sure to connect any ground pin including the bypass caps with short via connection to the ground plane. OESEL: J1 is recommended so the same PCB layout can be used for both OESEL settings. P L660 (4x AFM) TSSOP Layout P L663 (2x AFM) TSSOP Layout 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 12 A nalog Frequency Multiplier P L660 and PL663 X O Families PACKAGE PIN DESCRIPTION AND ASSIGNMENT GNDBUF VDDBUF VDDBUF QBAR QBAR GNDBUF 8 7 6 5 Q DNC GNDOSC DNC XIN XOUT OE DNC GNDANA 1 2 16 15 L2X VDDOSC VDDANA OESEL VDDBUF QBAR Q GNDBUF OESEL VDDANA VDDOSC L2X OSCOFFSEL GNDOSC GNDANA DNC OE 1 2 16 15 L2X VDDOSC OESEL VDDANA VDDBUF QBAR OSCOFF SEL GNDOSC Q GNDBUF DNC XIN VDDANA OESEL VDDOSC L2X 1 1 1 9 12 1 0 3 1 4 1 PL660-XX 5 1 61 2 3 4 3 4 5 6 7 8 14 13 12 11 10 9 1 1 1 9 12 1 0 3 1 4 1 PL663-XX 5 1 61 2 3 4 Q 8 7 6 5 VDDOSC L4X OE PL660-XX GNDOSC DNC DNC XIN P IN ASSIGNMENTS Name DNC OSCOFFSEL GNDOSC DNC XIN XOUT OE DNC L4X GNDANA 8 VDDOSC GNDBUF Q QBAR VDDBUF OESEL VDDANA VDDOSC L2X 9 10 11 12 13 14 14 13 15 16 P O O P I P P I P 4X 2X & 4X 2X & 4X 2X & 4X 2X & 4X 2X 4X 2X 4X 2X & 4X 2X & 4X 7 I 1 2 3 4 5 6 I P I I O I N ote: 663-xx devices are 2x multipliers, and 660-xx devices are 4x multipliers. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 13 PL663-XX DNC XIN XOUT OE L4X VDDOSC 3 4 5 6 7 8 14 13 12 11 10 9 XOUT XOUT 2x AFM Package Pin Out 4x AFM Package Pin Out Pin # Type Product 2X 4X 2X & 4X 2X & 4X 2X & 4X 2X & 4X 2X & 4X 2X 4X 2X Description Do Not Connect. Set to “0” (GND) to turn off the oscillator when outputs are disabled (OE). Default (no connect) is OSC always on. GND connection for oscillator. Do Not Connect. Input from crystal oscillator circuitry. Output from crystal oscillator circuitry. Output Enable input. See “OE LOGIC SELECTION TABLE”. Do Not Connect. External inductor connection. The inductor is recommended to be a high Q small size 0402 or 0603 SMD component, and must be placed between L4X and adjacent VDDOSC. Place inductor as close to the IC as possible to minimize parasitic effects and to maintain inductor Q. This inductor is used with 4x AFMs. GND connection. VDD connection for oscillator circuitry. VDDOSC should be separately decoupled from other VDDs whenever possible. GND connection. PECL/LVDS/CMOS output. Complementary PECL/LVDS output or in-phase CMOS. VDD connection for output buffer circuitry. VDDBUF should be separately decoupled from other VDDs whenever possible. Selector input to choose the OE control logic (see “OE SELECTION TABLE”). If no connection is applied, value will be set to default through internal pull-down resistor. VDD connection for analog circuitry.VDDANA should be separately decoupled from other VDDs whenever possible. VDD connection for oscillator. VDD should be separately decoupled from other VDDs whenever possible. External inductor connection. The inductor is recommended to be a high Q small size 0402 or 0603 SMD component, and must be placed between L2X and adjacent VDDOSC. Place inductor as close to the IC as possible to minimize parasitic effects and to maintain inductor Q. A nalog Frequency Multiplier P L660 and PL663 X O Families P ACKAGE INFORMATION 16 PIN TSSOP 16 PIN TSSOP ( mm ) Symbol A A1 B C D E H L e Min. Max. 1.20 0.05 0.15 0.19 0.30 0.09 0.20 4.90 5.10 4.30 4.50 6.40 BSC 0.45 0.75 0.65 BSC E H D A A1 e B C L 1 6 PIN 3x3 QFN 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 14 A nalog Frequency Multiplier P L660 and PL663 X O Families O RDERING INFORMATION To order parts, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PL66X-XX X X X X P ART NUMBER NONE= TUBE R= TAPE AND REEL NONE= NORMAL PACKAGE L= GREEN PACKAGE P ACKAGE TYPE O=TSSOP Q= QFN 3x3 T EMPERATURE C=COMMERCIAL I=INDUSTRIAL O rder Number P L 66X - XXOC P L66X-XXOC-R P L66X-XXOCL P L66X-XXOCL-R P L66X-XXQC P L66X-XXQC-R P L66X-XXQCL P L66X-XXQCL-R M arking P 66X - XX P 66X-XX P 66X-XX P 66X-XX P 66X-XX P 66X-XX P 66X-XX P 66X-XX OC OC OC OC QC QC QC QC P ackage Option T SSOP – T ube T SSOP – Tape and Reel TSSOP (GREEN)– Tube T SSOP (GREEN) – Tape and Reel Q FN – Tube Q FN – Tape and Reel Q FN (GREEN) – Tube Q FN (GREEN) – Tape and Reel P haseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. L IFE SUPPORT POLICY : PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 15