PLL103-02

P LL103-02 D DR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS F EATURES • • • • • • • • • G enerates 24 output buffers from one input. S upports up to four DDR DIMMS. S upports 266MHz DDR SDRAM. O ne additional output for feedback. L ess than 5ns delay. S kew between any outputs is less than 100 ps. 2 .5V Supply range. E nhanced DDR Output Drive selected by I2C. A vailable in 48 pin SSOP. P IN CONFIGURATION FBOUT VDD2.5 GND DDR0T DDR0C DDR1T DDR1C VDD2.5 GND DDR2T DDR2C VDD2.5 BUF_IN DDR0T 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 N/C VDD2.5 GND DDR11T DDR11C DDR10T DDR10C VDD2.5 GND DDR9T DDR9C VDD2.5 PD# GND DDR8T DDR8C VDD2.5 GND DDR7T DDR7C DDR6T DDR6C GND SCLK PLL103-02 B LOCK DIAGRAM SDATA SCLK I2C Control DDR0C DDR1T DDR1C DDR2T DDR2C DDR3T DDR3C DDR4T GND DDR3T DDR3C VDD2.5 GND DDR4T DDR4C DDR5T DDR5C VDD2.5 SDATA N ote: # : Active Low BUF_IN DDR4C DDR5T DDR5C DDR6T DDR6C DDR7T DDR7C DDR8T DDR8C DDR9T DDR9C DDR10T DDR10C DDR11T DDR11C D ESCRIPTION T he PLL103-02 is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 can be used in conjunction with a clock synthesizer for the VIA Pro 266 chipset. The PLL103-02 also has an I2C interface, which can enable or disable each output clock. When powered up, all output clocks are enabled (have internal pull ups). PD# 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 09/09/04 Page 1 P LL103-02 D DR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS P IN DESCRIPTIONS N ame F BOUT B UF_IN PD N /C D DR[0:11]T D DR[0:11]C V DD2.5 G ND Number 1 13 36 48 4,6,10,15,19, 21,28,30,34, 39,43,45 5,7,11,16,20, 22,27,29,33, 38,42,44 2,8,12,17,23, 32,37,41,47 3,9,14,18,26, 31,35,40,46 Type O I I Description Feedback clock for chipset. Reference input from chipset. Power Down Control input. When low, it will tri-state all outputs. Not connected. These outputs provide True copies of BUF_IN. These outputs provide complementary copies of BUF_IN. 2.5V power supply. Ground. O O P P 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 09/09/04 Page 2 P LL103-02 D DR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS I 2C BUS CONFIGURATION SETTING A ddress Assignment S lave Receiver/Transmitter D ata Transfer Rate A6 1 A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W _ Provides both slave write and readback functionality Standard mode at 100kbits/s This serial protocol is designed to allow both blocks write and read from the controller. The bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will terminate the transfer. The write or read block both begins with the master sending a slave address and a write condition (0xD2) or a read condition (0xD3). Following the acknowledge of this address byte, in W rite Mode: t he C ommand Byte a nd B yte Count Byte m ust be sent by the master b ut ignored by the slave, in R ead Mode: t he B yte Count Byte w ill be r ead by the master t hen all other D ata Byte . B yte Count Byte d efault at power-up is = (0x09). D ata Protocol I 2C CONTROL REGISTERS 1 . BYTE 6: Outputs Register ( 1=Enable, 0=Disable) B it B it B it B it B it B it B it B it B it 7 6 5 4 3 2 1 0 Pin# 48 45, 44 43, 42 39, 38 34, 33 Default 1 0 0 0 1 1 1 1 Description Reserved Reserved Enhanced DDR Drive. 1 = Enhanced 25% Reserved DDR11T, DDR11C DDR10T, DDR10C DDR9T, DDR9C DDR8T, DDR8C 2 . BYTE 7: Outputs Register ( 1=Enable, 0=Disable) B it B it B it B it B it B it B it B it B it 7 6 5 4 3 2 1 0 Pin# 30, 28, 21, 19, 15, 10, 6, 4, 29 27 22 20 16 11 7 5 Default 1 1 1 1 1 1 1 1 Description DDR7T, DDR6T, DDR5T, DDR4T, DDR3T, DDR2T, DDR1T, DDR0T, DDR7C DDR6C DDR5C DDR4C DDR3C DDR2C DDR1C DDR0C 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 09/09/04 Page 3 P LL103-02 D DR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS E LECTRICAL SPECIFICATIONS 1 . Absolute Maximum Ratings P ARAMETERS S upply Voltage I nput Voltage, dc O utput Voltage, dc S torage Temperature A mbient Operating Temperature* J unction Temperature L ead Temperature (soldering, 10s) E SD Protection, Human Body Model SYMBOL V DD VI VO TS TA TJ MIN. V SS -0.5 V SS -0.5 - 65 - 40 MAX. 4 .6 V DD +0.5 V DD +0.5 150 85 1 25 260 2 UNITS V V V °C °C °C °C kV E xposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * N ote : Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2 . Operating Conditions P ARAMETERS S upply Voltage I nput Capacitance O utput Capacitance SYMBOL V DD2.5 C IN C OUT MIN. 2 .375 MAX. 2.625 5 6 UNITS V pF pF 3 . Electrical Specifications P ARAMETERS I nput High Voltage I nput Low Voltage I nput High Current I nput Low Current O utput High Voltage O utput Low Voltage O utput High Current O utput Low Current N ote: T BM: To be measured SYMBOL V IH V IL I IH I IL V OH V OL I OH I OL CONDITIONS A ll Inputs except I2C A ll inputs except I2C V IN = V DD V IN = 0 I OL = -12mA, VDD = 2.375V I OL = 12mA, VDD = 2.375V V DD = 2.375V, VOUT=1V V DD = 2.375V, VOUT=1.2V MIN. 2.0 V SS -0.3 TYP. MAX. V DD +0.3 0.8 T BM T BM UNITS V V uA uA V 1.7 0.6 -18 26 -32 35 V mA mA 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 09/09/04 Page 4 P LL103-02 D DR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS 3 . Electrical Specifications (Continued) P ARAMETERS S upply Current O utput Crossing Voltage O utput Voltage Swing D uty Cycle M ax. Operating Frequency R ising Edge Rate F alling Edge Rate C lock Skew ( pin to pin ) S tabilization Time N ote: T BM: To be measured SYMBOL I DDS V OC V OUT DT T OR T OF T SKEW T ST PD = 0 CONDITIONS MIN. ( VDD/2) -0.1 1 .1 TYP. VDD/2 MAX. TBM (VDD/2)+ 0.1 VDD-0.4 55 170 2.0 2.0 100 0 .1 UNITS mA V V % MHz V/ns V/ns ps ms M easured @ 1.5V M easured @ M easured @ 0.4V ~ 2.4V 2.4V ~ 0.4V 45 66 1.0 1.0 50 1.5 1.5 A ll outputs equally loaded 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 09/09/04 Page 5 P LL103-02 D DR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS P ACKAGE INFORMATION 0.400 - 0.410 10.160 - 10.414 0.292 - 0.299 7.417 - 7.959 0.008 - 0.0135 0.203 - 0.343 0.025 0.835 0.015 (0.381) 0.010 - 0.016 (0.25 - 0.41) 45 0 0.620 - 0.630 (15.75 - 16.00) 0.088 - 0.096 (2.250 - 2.450) 0.097 - 0.104 (2.467 - 2.642) 30-60 0.050 MIN (1.346) 0.008 - 0.016 (0.20 - 0.41) 48PIN SSOP ORDERING INFORMATION F or part ordering, please contact our Sales Department: 4 7745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 P ART NUMBER T he order number for this device is a combination of the following: Device number, Package type and Operating temperature range P LL103-02 X C PART NUMBER T EMPERATURE C=COMMERCIAL I=INDUSTRAL P ACKAGE TYPE X=SSOP O rder Number P LL103-02XC-R PLL103-02XC Marking P103-02XC P103-02XC Package Option SSOP - Tape and Reel SSOP - Tube P haseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by PhaseLink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. L IFE SUPPORT POLICY : PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 09/09/04 Page 6