PLL500-17BSC-R

P LL500-17B/27B/37B L ow Power CMOS Output VCXO Family (17MHz to 130MHz) F EATURES • V CXO output for the 17MHz to 130MHz range - P LL500-17B: 17MHz to 36MHz - P LL500-27B: 27MHz to 65MHz - P LL500-37B: 65MHz to 130MHz L ow phase noise (-142 dBc @ 10kHz offset). C MOS output with OE tri-state control. S electable output drive (Standard or High drive). - S tandard: 8mA drive capability at TTL level. - H igh: 24mA drive capability at TTL level. F undamental crystal input. I ntegrated high linearity variable capacitors. + /- 150 ppm pull range, max 5% linearity. L ow jitter (RMS): 2.5ps period jitter. 2 .5 to 3.3V operation. A vailable in 8-Pin SOIC or DIE. P IN CONFIGURATION XIN OE^ VIN GND 1 8 XOUT DS^ VDD* CLK P500-x7B 2 3 4 7 6 5 • • • • • • • • • ^: Denotes internal Pull-up D IE PAD LAYOUT 32 mil (812,986) 8 1 XIN XOUT DRIVSEL^ 7 39 mil D ESCRIPTION T he PLL500-17B/27B/37B are a low cost, high performance, low phase noise, and high linearity VCXO family for the 17 to 130MHz range, providing less than -130dBc at 10kHz offset. The very low jitter (2.5 ps RMS period jitter) makes these chips ideal for applications requiring voltage controlled frequency sources. The IC’s are designed to accept fundamental resonant mode crystals. 2 OE^ VDD 6 3 VCON 4 GND CLK 5 DIE ID:PLL500-17B: C500A0505-05P Y X PLL500-27B: C500A0505-05Q PLL500-37B: C500A0505-05R (0,0) Note: ^ denotes internal pull up F REQUENCY RANGE P ART # P LL500-17B P LL500-27B P LL500-37B MULTIPLIER No PLL No PLL No PLL FREQUENCY 17 – 36 MHz 27 – 65 MHz 65 – 130 MHz DIE SPECIFICATIONS N ame Value S ize R everse side P ad dimensions T hickness 39 x 32 mil GND 80 micron x 80 micron 10 mil B LOCK DIAGRAM XIN X OUT X TAL OSC VARICAP OE V CON 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 12/21/05 Page 1 P LL500-17B/27B/37B L ow Power CMOS Output VCXO Family (17MHz to 130MHz) P IN AND PAD DESCRIPTION N ame X IN OE V CON G ND C LK V DD D RIVSEL X OUT Pin# 1 2 3 4 5 6 7 8 D ie Pad Position X ( µ m) 94.183 94.157 94.183 94.193 715.472 715.307 715.472 476.906 Y ( µ m) 768.599 605.029 331.756 140.379 203.866 455.726 626.716 888.881 Type I I I P O P I I Description Crystal input pin. Output Enable input pin. Disables the output when low. Internal pull-up enables output by default if pin is not connected low. Frequency control voltage input pin. Ground pin. Output clock pin. VDD power supply pin. Output drive select pin. High drive if set to ‘0’. Low drive if set to ‘1’. Internal pull-up. Crystal output pin. Ref clock input. E LECTRICAL SPECIFICATIONS 1 . Absolute Maximum Ratings P ARAMETERS S upply Voltage I nput Voltage, dc O utput Voltage, dc S torage Temperature A mbient Operating Temperature* J unction Temperature L ead Temperature (soldering, 10s) E SD Protection, Human Body Model SYMBOL V DD VI VO TS TA TJ MIN. - 0.5 - 0.5 - 65 - 40 MAX. 4 .6 V DD +0.5 V DD +0.5 150 85 1 25 260 2 UNITS V V V °C °C °C °C kV E xposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * N ote : Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2 . AC Electrical Specifications P ARAMETERS I nput Crystal Frequency SYMBOL CONDITIONS P LL500-17B P LL500-27B P LL500-47B 0 .8V ~ 2.0V with 10 pF load 0 .3V ~ 3.0V with 15 pF load M easured @ 1.4V MIN. 17 27 65 TYP. MAX. 36 65 130 UNITS MHz O utput Clock Rise/Fall Time O utput Clock Duty Cycle S hort Circuit Current 45 0.8 2.5 50 ± 50 ns 55 % mA 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 12/21/05 Page 2 P LL500-17B/27B/37B L ow Power CMOS Output VCXO Family (17MHz to 130MHz) 3 . Voltage Control Crystal Oscillator P ARAMETERS V CXO Stabilization Time * V CXO Tuning Range C LK output pullability V CXO Tuning Characteristic P ull range linearity P ower Supply Rejection V CON pin input impedance V CON modulation BW PWSRR SYMBOL T VCXOSTB CONDITIONS F rom power valid F XIN = 1 2 – 25MHz; XTAL C 0 /C 1 < 2 50 0V ≤ V CON ≤ 3 .3V VCON=1.65V, ± 1.65V MIN. TYP. MAX. 10 UNITS ms ppm ppm ppm/V % ppm kΩ kHz 300 ± 150 1 00 5 F requency change with VDD varied +/- 10% 0 V ≤ V CON ≤ 3 .3V, -3dB -1 2 000 45 +1 N ote: P reliminary Specifications still to be characterized. Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 4 . Jitter and Phase Noise Specifications P ARAMETERS R MS Period Jitter (1 sigma – 10,000 samples) P hase Noise relative to carrier P hase Noise relative to carrier P hase Noise relative to carrier P hase Noise relative to carrier P hase Noise relative to carrier CONDITIONS With capacitive decoupling between VDD and GND. @100Hz offset @1kHz offset @10kHz offset @100kHz offset @1MHz offset MIN. TYP. 2.5 -100 -125 -142 -150 -150 MAX. UNITS ps dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 12/21/05 Page 3 P LL500-17B/27B/37B L ow Power CMOS Output VCXO Family (17MHz to 130MHz) 5 . DC Specifications P ARAMETERS S upply Current, Dynamic, with Loaded Outputs SYMBOL I DD CONDITIONS F XIN = 2 7MHz, 15pF output load F XIN = 3 5MHz, 15pF output load F XIN = 7 8MHz, 15pF output load P LL500-17B P LL500-27B P LL500-37B Std drive up to 100MHz PLL500-37B High drive I OH = - 8mA I OL = 8 mA I OH = - 4mA S tandard drive at TTL level High drive at TTL level MIN. TYP. 2.8 4.2 7.2 MAX. 4 6 9 30 20 15 UNITS mA pF pF pF pF V V V V A llowable output load capacitance O perating Voltage O utput High Voltage O utput Low Voltage O utput High Voltage at CMOS level O utput drive current S hort Circuit Current V CXO Control Voltage CL ( Output) V DD V OH V OL 2 .25 2.4 V DD – 0 .4 8 24 0 9.5 27 ± 50 10 3.63 0.4 mA mA V VCON V DD 6 . Crystal Specifications P ARAMETERS C rystal Loading Rating (VCON = 1.65V) M aximum Sustainable Drive Level O perating Drive Level M ax C0 for PLL500-17B M ax C0 for PLL500-27B M ax C0 for PLL500-37B C 0/C1 E SR SYMBOL C L ( xtal) MIN. TYP. 8 .5 MAX. 200 UNITS pF µW µW pF Ω 50 5 3.5 2.5 250 30 RS N ote : The crystal must be such that it oscillates (parallel resonant) at nominal frequency when presented a C Load as specified above. If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may reduce the pull range. 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 12/21/05 Page 4 P LL500-17B/27B/37B L ow Power CMOS Output VCXO Family (17MHz to 130MHz) P ACKAGE INFORMATION S OIC 8L ( Dimensions in mm) S ymbol A A1 A2 B C D E H L e D imension in MM Min. Max. 1 .35 1.75 0.10 0.25 1.25 1.50 0 .33 0.53 0 .19 0.27 4 .80 5.00 3 .80 4.00 5 .80 6.20 0 .40 0.89 1 .27 BSC E H D A2 A A1 e b C L O RDERING INFORMATION F or part ordering, please contact our Sales Department: 4 7745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 P ART NUMBER T he order number for this device is a combination of the following: Device number, Package type and Operating temperature range P LL500-X7B X X X X P ART NUMBER N ONE= TUBE R=TAPE AND REEL N ONE=NORMAL PACK A GE L=GREEN PACKAGE P ACKAGE TYPE S=SSOP T EMPERATURE C=COMMERCIAL I=INDUSTRIAL O rder Number P LL500-X7BDC P LL500-X7BSC P LL500-X7BSC-R P LL500-X7BSCL P LL500-X7BSCL-R Marking P500-X7BDC P500-X7BSC P500-X7BSC P500-X7BSCL P500-X7BSCL Package Option Die (Waffle Pack) 8-Pin SOIC (Tube) 8-Pin SOIC (Tape and Reel) 8-Pin SOIC (Tube), GREEN 8-Pin SOIC (Tape and Reel) , GREEN P haseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. L IFE SUPPORT POLICY : PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the ex press written approval of the President of PhaseLink Corporation. 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 12/21/05 Page 5