P LL602-03
L ow Phase Noise CMOS XO (48MHz to 100MHz)
F EATURES
• • • • • • • L ow phase noise XO output for the 48MHz to 100MHz range (-130 dBc at 10kHz offset). 1 2 to 25MHz crystal input. I ntegrated crystal load capacitor: no external load capacitor required. L ow jitter (RMS): 3ps period jitter (1 sigma). S electable High Drive (30mA) or Standard Drive (10mA) output. 3 .3V operation. A vailable in 8-Pin TSSOP or SOIC.
P IN CONFIGURATION
CLK VDD OE^ XIN 1 2 3 4 8 7 6 5 GND GND N/C XOUT
Note: ^ denotes internal pull up
OUTPUT RANGE
M ULTIPLIER X4 FREQUENCY RANGE 48 - 100MHz OUTPUT BUFFER CMOS
PLL602-03
D ESCRIPTION
T he PLL602-03 is a low cost, high performance and low phase noise XO, providing less than -130dBc at 10kHz offset in the 48MHz to 100MHz operating range. The very low jitter (3ps RMS period jitter) makes this chip ideal for applications requiring clean reference frequency sources. Input crystal can range from 12 to 25MHz (fundamental resonant mode).
B LOCK DIAGRAM
VCO Divider Reference Divider Phase Comparator Charge Pump Loop Filter
VCO
CLK
XIN XOUT
XTAL OSC
OE
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P LL602-03
L ow Phase Noise CMOS XO (48MHz to 100MHz)
P IN DESCRIPTIONS
N ame
C LK V DD OE X IN X OUT N /C G ND
Number
1 2 3 4 5 6 7, 8
Type
O P I I I P Output clock. power supply.
Description
Output enable input. Disables (tri-state) output when low. Internal pull-up enables output by default if pin is not connected to low. Crystal input. See Crystal Specification on page 3. Crystal output. See Crystal Specification on page 3. Not connected. Ground.
E LECTRICAL SPECIFICATIONS
1 . Absolute Maximum Ratings P ARAMETERS
S upply Voltage I nput Voltage, dc O utput Voltage, dc S torage Temperature A mbient Operating Temperature* J unction Temperature L ead Temperature (soldering, 10s) E SD Protection, Human Body Model
SYMBOL
V DD VI VO TS TA TJ
MIN.
- 0.5 - 0.5 - 65 - 40
MAX.
4 .6 V DD +0.5 V DD +0.5 150 85 1 25 260 2
UNITS
V V V °C °C °C °C kV
E xposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * N ote : Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2 . DC Specifications P ARAMETERS
S upply Current, Dynamic, with Loaded Outputs O perating Voltage O utput drive current (High Drive) O utput drive current (Standard Drive) S hort Circuit Current
SYMBOL
I DD V DD I OH I OL I OH I OL
CONDITIONS
F XIN = 1 2 - 25MHz Output load of 10pF
MIN.
TYP.
16
MAX.
20 3.63
UNITS
mA V mA mA mA mA
2 .97 V OH = V DD -0.4V, V DD =3.3V V OL = 0 .4V, V DD = 3 .3V V OH = V DD -0.4V, V DD =3.3V V OL = 0 .4V, V DD = 3 .3V 30 30 10 10 ± 50
mA
4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 09/03/04 Page 2
P LL602-03
L ow Phase Noise CMOS XO (48MHz to 100MHz)
3 . AC Specifications P ARAMETERS
I nput Crystal Frequency O utput Clock Rise/Fall Time (Standard Drive) O utput Clock Rise/Fall Time (High Drive) O utput Clock Duty Cycle
SYMBOL
CONDITIONS
0 .3V ~ 3.0V with 15 pF load 0 .3V ~ 3.0V with 15 pF load M easured @ 50% V DD
MIN.
12
TYP.
2.4 1.2
MAX.
25
UNITS
MHz ns
45
50
55
%
4 . Jitter and Phase Noise Specification P ARAMETERS
R MS Period Jitter (1 sigma – 1000 samples) P hase Noise relative to carrier P hase Noise relative to carrier P hase Noise relative to carrier P hase Noise relative to carrier
CONDITIONS
at 80MHz, with capacitive decoupling between VDD and GND. 80MHz @100Hz offset 80MHz @1kHz offset 80MHz @10kHz offset 80MHz @100kHz offset
MIN.
TYP.
3.5 -103 -122 -130 -125
MAX.
UNITS
ps dBc/Hz dBc/Hz dBc/Hz dBc/Hz
5 . Crystal Specifications P ARAMETERS
C rystal Resonator Frequency C rystal Loading Capacitance Rating D riving power E SR
SYMBOL
F XIN C L ( xtal) RS
MIN.
12
TYP.
20 1
MAX.
25
UNITS
MHz pF mW Ω
30
P ACKAGE INFORMATION
8 PIN ( dimensions in mm )
Narrow SOIC Symbol A A1 B C D E H L e Min. 1.47 0.10 0.33 0.19 4.80 3.80 5.80 0.38 Max. 1.73 0.25 0.51 0.25 4.95 4.00 6.20 1.27 1.27 BSC Min. 0.05 0.19 0.09 2.90 4.30 6.20 0.45 TSSOP Max. 1.20 0.15 0.30 0.20 3.10 4.50 6.60 0.75 0.65 BSC A1 B C L e A D E H
4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 09/03/04 Page 3
P LL602-03
L ow Phase Noise CMOS XO (48MHz to 100MHz)
O RDERING INFORMATION
F or part ordering, please contact our Sales Department:
4 7745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991
P ART NUMBER
T he order number for this device is a combination of the following: Device number, Package type and Operating temperature range
P LL602-03 (H) X C
P ART NUMBER O ptional High Drive T EMPERATURE C=COMMERCIAL I=INDUSTRAL P ACKAGE TYPE S=SOIC , O =TSSOP
O rder Number P LL602-03OC-R PLL602-03OC PLL602-03HOC-R PLL602-03HOC PLL602-03SC-R PLL602-03SC PLL602-03HSC-R PLL602-03HSC
Marking PLL602-03OC PLL602-03OC PLL602-03HOC PLL602-03HOC PLL602-03SC PLL602-03SC PLL602-03HSC PLL602-03HSC
Package Option TSSOP TSSOP TSSOP TSSOP SOIC SOIC SOIC SOIC - Tape and Reel – Tube - Tape and Reel – Tube
- Tape and Reel – Tube - Tape and Reel - Tube
P haseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. L IFE SUPPORT POLICY : PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
4 7745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 03/14/00 Page 4
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