PLL620-05OI

P LL620-05/-06/-07/-08/-09 L ow Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal) U niversal Low Phase Noise IC’s F EATURES • • 1 00MHz to 200MHz Fundamental or 3 rd O vertone Crystal. O utput range: 100 – 200MHz (no multiplication), 200 – 400MHz (2x multiplier), 400 – 700MHz (4x multiplier), or 800MHz-1GHz(PLL620-09 only, 8x multiplier). C MOS (Standard drive PLL620-07 or Selectable Drive PLL620-06), PECL (Enable low PLL620-08 or Enable high PLL620-05) or LVDS output (PLL620-09). S upports 3.3V-Power Supply. A vailable in 16-Pin (TSSOP or 3x3mm QFN) Note: PLL620-06 only available in 3x3mm. Note: PLL620-07 only available in TSSOP. PIN CONFIGURATION ( Top View) VDD XIN XOUT SEL3^ SEL2^ OE GND GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SEL0^ SEL1^ GND CLKC VDD CLKT GND GND PLL 620-0x • • • DNC/ DRIVSEL* SEL0^ 10 D ESCRIPTION T he PLL620-0x family of XO IC’s is specifically designed to work with high frequency fundamental and third overtone crystals. Their low jitter and low phase noise performance make them well suited for high frequency XO requirements. They achieve very low current into the crystal resulting in better overall stability. XIN XOUT SEL2^ OE 13 14 15 16 12 11 SEL1^ 9 VDD 8 7 6 5 GND CLKC VDD CLKT PLL620-0x 1 2 3 4 GND GND GND B LOCK DIAGRAM SEL OE PLL (Phase Locked Loop) ^ : Internal pull-up *: PLL620-06 pin 12 is output drive select (DRIVSEL) (0 for High Drive CMOS, 1 for Standard Drive CMOS) T he pin remains ‘Do Not Connect (DNC)’ for PLL620-05/07/08/09. O UTPUT ENABLE LOGICAL LEVELS P art # OE S tate Q Q X+ X- Oscillator Amplifier P LL620-08 P LL620-05 PLL620-06 PLL620-07 PLL620-09 0 ( Default) 1 0 1 (Default) Output enabled Tri-state T ri-state Output enabled PLL by-pass O E input: Logical states defined by PECL levels for PLL620-08 Logical states defined by CMOS levels for PLL620-05/-06/07/-09 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 11/01/05 Page 1 GND P LL620-05/-06/-07/-08/-09 L ow Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal) U niversal Low Phase Noise IC’s P IN DESCRIPTIONS N ame V DD X IN X OUT OE G ND TSSOP* Pin number 1, 12 2 3 6 7,8,9, 10, 14 3x3mm QFN* Pin number 6,11 13 14 16 1,2,3,4,8 Type P I I I P +3.3V power supply. Crystal input. See Crystal Specification on page 3. Crystal output. See Crystal Specification on page 3. Output enable. Ground (except pin 12 on PLL620-06: DRIVSEL see below). PLL620-06 only: Drive Select Input. This pin has an internal pull-up that will default DRIVSEL to ‘1’ when not connect to GND. CMOS output of PLL620-06 will be high drive CMOS when DRIVSEL is set to ‘0’, and will be standard CMOS otherwise. The pin remains ‘Do Not Connect (DNC)’ for PLL620-05/07/08/09. True output PECL (PLL620-08) or LVDS (PLL620-09) (N/C for PLL620-07) Complementary output PECL (PLL620-08) or LVDS (PLL62009) (CMOS out for PLL620-07). Multiplier selector pins. These pins have an internal pull-up that will default SEL to ‘1’ when not connected to GND. Description D RIVSEL** - 12 I C LKT C LKC S EL0 S EL1 S EL2 S EL3 11 13 16 15 5 4 5 7 10 9 15 Not available O O I I I I * N ote: PLL620-06 only available in 3x3mm QFN, PLL620-07 only available in TSSOP. ** Note: DRIVSEL on pin 12 on PLL620-06 only. The pin remains ‘Do Not Connect (DNC)’ for PLL620-05/07/08/09. F REQUENCY SELECTION TABLE S EL3 0 1 1 1 SEL2 0 0 1 1 SEL1 1 1 1 1 SEL0 1 1 0 1 F in x 4 F in x 2 N o multiplication Selected Multiplier F in x 8(PLL620-09 only) N ote: S EL3 is not available (always “1”) in 3x3mm package All pins have internal pull-ups (default value is 1). Connect to GND to set to 0. 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 11/01/05 Page 2 P LL620-05/-06/-07/-08/-09 L ow Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal) U niversal Low Phase Noise IC’s E LECTRICAL SPECIFICATIONS 1 . Absolute Maximum Ratings P ARAMETERS S upply Voltage I nput Voltage, dc O utput Voltage, dc S torage Temperature A mbient Operating Temperature* J unction Temperature L ead Temperature (soldering, 10s) E SD Protection, Human Body Model SYMBOL V DD VI VO TS TA TJ MIN. - 0.5 - 0.5 - 65 - 40 MAX. 4 .6 V DD +0.5 V DD +0.5 150 85 1 25 260 2 UNITS V V V °C °C °C °C kV E xposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * N ote : Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2 . Crystal Specifications P ARAMETERS C rystal Resonator Frequency C rystal Loading Rating I nterelectrode Capacitance R ecommended ESR SYMBOL F XIN C L (xtal) C0 RE CONDITIONS F undamental or o vertone* 3 rd MIN. 100 5 A T cut 5 30 TYP. MAX. 200 UNITS MHz pF pF Ω * N ote : 3 r d o vertone crystals require an external resistor between XIN and XOUT to prevent the fundamental from oscillating. 3 . General Electrical Specifications P ARAMETERS S upply Current (Loaded Outputs) O perating Voltage O utput Clock Duty Cycle S hort Circuit Current SYMBOL I DD V DD @ 5 0% V DD ( CMOS) @ 1.25V (LVDS) @ V DD – 1 .3V (PECL) CONDITIONS P ECL/LVDS/CMOS 2 .97 45 45 45 50 50 50 ± 50 MIN. TYP. MAX. 100/80/40 3.63 55 55 55 UNITS mA V % mA 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 11/01/05 Page 3 P LL620-05/-06/-07/-08/-09 L ow Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal) U niversal Low Phase Noise IC’s 4 . Jitter Specifications P ARAMETERS P eriod jitter RMS P eriod jitter peak-to-peak A ccumulated jitter RMS A ccumulated jitter peak-to-peak R andom Jitter I ntegrated jitter RMS at 155MHz P eriod jitter RMS P eriod jitter peak-to-peak A ccumulated jitter RMS A ccumulated jitter peak-to-peak R andom Jitter I ntegrated jitter RMS at 622MHz CONDITIONS At 155.52MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles At 155.52MHz, with capacitive decoupling between VDD and GND. Over 1,000,000 cycles. “RJ” measured on Wavecrest SIA 3000 Integrated 12 kHz to 20 MHz At 622.08MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles At 622.08MHz, with capacitive decoupling between VDD and GND. Over 1,000,000 cycles. “RJ” measured on Wavecrest SIA 3000 Integrated 12 kHz to 20 MHz MIN. TYP. 2.5 18.5 2.5 24 2.5 0.3 11 45 11 24 3 1.6 MAX. 20 27 0.4 49 27 1.8 UNITS ps ps ps ps ps ps ps ps 5 . Phase Noise Specifications P ARAMETERS P hase Noise relative to carrier FREQUENCY 1 55.52MHz 622.08MHz @10Hz -75 -75 @100Hz -95 -95 @1kHz -125 -110 @10kHz -140 -125 @100kHz -145 -120 UNITS dBc/Hz 6 . CMOS Electrical Specifications P ARAMETERS O utput drive current (High Drive) O utput drive current (Standard Drive) O utput Clock Rise/Fall Time (Standard Drive) O utput Clock Rise/Fall Time (High Drive) SYMBOL I OH I OL I OH I OL CONDITIONS V OH = V DD -0.4V, V DD =3.3V V OL = 0 .4V, V DD = 3 .3V V OH = V DD -0.4V, V DD =3.3V V OL = 0 .4V, V DD = 3 .3V 0 .3V ~ 3.0V with 15 pF load 0 .3V ~ 3.0V with 15 pF load MIN. 30 30 10 10 TYP. MAX. UNITS mA mA mA mA 2.4 1.2 ns * N ote: High Drive CMOS is available on PLL620-06 through DRIVSEL selector input on pin 12. 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 11/01/05 Page 4 P LL620-05/-06/-07/-08/-09 L ow Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal) U niversal Low Phase Noise IC’s 7 . LVDS Electrical Characteristics P ARAMETERS O utput Differential Voltage V DD M agnitude Change O utput High Voltage O utput Low Voltage O ffset Voltage O ffset Magnitude Change P ower-off Leakage O utput Short Circuit Current SYMBOL V OD ∆ V OD V OH V OL V OS ∆ V OS I OXD I OSD V out = V DD o r GND V DD = 0 V R L = 1 00 Ω ( see figure) CONDITIONS MIN. 2 47 - 50 1 .4 0 .9 1 .125 0 1.1 1.2 3 ±1 - 5.7 1.375 25 ± 10 -8 TYP. 355 MAX. 454 50 1.6 UNITS mV mV V V V mV uA mA 8 . LVDS Switching Characteristics P ARAMETERS D ifferential Clock Rise Time D ifferential Clock Fall Time LVDS Levels Test Circuit OUT SYMBOL tr tf CONDITIONS R L = 1 00 Ω C L = 1 0 pF (see figure) MIN. 0 .2 0.2 TYP. 0.7 0.7 MAX. 1.0 1.0 UNITS ns ns LVDS Switching Test Circuit OUT 50Ω CL = 10pF VOD VOS VDIFF RL = 100Ω 50Ω CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% VDIFF 20% 0V 80% 20% tR tF 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 11/01/05 Page 5 P LL620-05/-06/-07/-08/-09 L ow Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal) U niversal Low Phase Noise IC’s 9 . PECL Electrical Characteristics P ARAMETERS O utput High Voltage O utput Low Voltage SYMBOL V OH V OL CONDITIONS R L = 5 0 Ω t o (V DD – 2 V) (see figure) MIN. V DD – 1 .025 MAX. V DD – 1 .620 UNITS V V 1 9. PECL Switching Characteristics P ARAMETERS C lock Rise Time C lock Fall Time SYMBOL tr tf CONDITIONS @ 20/80% - PECL @ 80/20% - PECL MIN. TYP. 0.6 0.5 MAX. 1.5 1.5 UNITS ns ns PECL Levels Test Circuit OUT VDD OUT PECL Output Skew 50Ω 2.0V 50% 50Ω OUT OUT tSKEW PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tR tF 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 11/01/05 Page 6 P LL620-05/-06/-07/-08/-09 L ow Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal) U niversal Low Phase Noise IC’s P ACKAGE INFORMATION 16 PIN TSSOP ( mm ) Symbol A A1 B C D E H L e Min. Max. 1.20 0.05 0.15 0.19 0.30 0.09 0.20 4.90 5.10 4.30 4.50 6.40 BSC 0.45 0.75 0.65 BSC E H D A A1 e B C L 3mm x 3mm, QFN 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 11/01/05 Page 7 P LL620-05/-06/-07/-08/-09 L ow Phase Noise XO with multipliers (for 100-200MHz Fund or 3rdOT Xtal) U niversal Low Phase Noise IC’s O RDERING INFORMATION F or part ordering, please contact our Sales Department: 4 7745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 P ART NUMBER T he order number for this device is a combination of the following: Device number, Package type and Operating temperature range P LL620-0X X X X X P ART NUMBER N ONE= TUBE R=TAPE AND N ONE=NORMAL PACK A GE L=GREEN PACKAGE P ACKAGE TYPE X=SSOP T EMPERATURE C=COMMERCIAL I=INDUSTRIAL Order Number PLL620-08OC PLL620-08OC-R PLL620-08OCL PLL620-08OCL-R PLL620-08QC PLL620-08QC-R PLL620-08QCL PLL620-08QCL-R PLL620-09OC PLL620-09OC-R PLL620-09OCL PLL620-09OCL-R PLL620-09QC PLL620-09QC-R PLL620-09QCL PLL620-09QCL-R O rder Number P LL620-05OC P LL620-05OC-R P LL620-05OCL P LL620-05OCL-R P LL620-05QC P LL620-05QC-R P LL620-05QCL P LL620-05QCL-R P LL620-06QC P LL620-06QC-R P LL620-06QCL P LL620-06QCL-R P LL620-07OC P LL620-07OC-R P LL620-07OCL P LL620-07OCL-R Marking P620-05OC P620-05OC P620-05OCL P620-05OCL P620-05QC P620-05QC P620-05QCL P620-05QCL P620-06QC P620-06QC P620-06QCL P620-06QCL P620-07OC P620-07OC P620-07OCL P620-07OCL Package Option TSSOP – Tube TSSOP – Tape & Reel TSSOP – Tube, GREEN TSSOP – Tape & Reel, GREEN QFN – Tube QFN – Tape & Reel QFN – Tube, GREEN QFN – Tape & Reel, GREEN QFN – Tube QFN – Tape & Reel QFN – Tube, GREEN QFN – Tape & Reel, GREEN TSSOP – Tube TSSOP – Tape & Reel TSSOP – Tube, GREEN TSSOP – Tape & Reel, GREEN Marking P620-08OC P620-08OC P620-08OCL P620-08OCL P620-08QC P620-08QC P620-08QCL P620-08QCL P620-09OC P620-09OC P620-09OCL P620-09OCL P620-09QC P620-09QC P620-09QCL P620-09QCL Package Option TSSOP – Tube TSSOP – Tape & Reel TSSOP – Tube, GREEN TSSOP – Tape & Reel, GREEN QFN – Tube QFN – Tape & Reel QFN – Tube, GREEN QFN – Tape & Reel, GREEN TSSOP – Tube TSSOP – Tape & Reel TSSOP – Tube, GREEN TSSOP – Tape & Reel, GREEN QFN – Tube QFN – Tape & Reel QFN – Tube, GREEN QFN – Tape & Reel, GREEN P haseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. L IFE SUPPORT POLICY : PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 11/01/05 Page 8