PLL620-80DC

P LL620-80 L ow Phase Noise XO (9.5-65MHz Output) F EATURES • • • • • • 1 9MHz to 65MHz crystal input. O utput range: 9.5MHz – 65MHz S electable OE Logic (enable high or enable low). A vailable outputs: PECL, LVDS, or CMOS (High Drive (30mA) or Standard Drive (10mA) output). S upports 2.5V or 3.3V Power Supply. A vailable in die form. D IE CONFIGURATION OUTSEL0^ 65 mil OUTSEL1^ Reserved VDD VDD VDD VDD N/C (1550,1475) 17 16 25 24 23 22 21 20 19 18 GNDBUF CMOS LVDSB PECLB VDDBUF VDDBUF PECL LVDS OE_SEL^ XIN XOUT N/C 62 mil 26 27 Die ID: A2020-20B 15 28 14 D ESCRIPTION T he PLL620-80 is a XO IC specifically designed to work with fundamental or 3 rd O T crystals between 19MHz and 65MHz. The selectable divide by two feature extends the operation range from 9.5MHz to 65MHz. It requires very low current into the crystal resulting in better overall stability. The OE logic feature allows selection of enable high or enable low. Furthermore, it provides selectable CMOS, PECL or LVDS outputs. S2^ OE CTRL N/C 13 29 12 11 30 C502A 31 1 2 3 4 5 6 7 8 10 9 Reserved Y (0,0) X O UTPUT SELECTION AND ENABLE O UT_SEL1* (Pad 18) 0 0 1 1 O E_SELECT (Pad 9) 0 1 ( Default) OUT_SEL0* (Pad 25) 0 1 0 1 OE_CTRL (Pad 30) 0 1 ( Default) 0 ( Default) 1 Selected Output* H igh Drive CMOS S tandard CMOS L VDS P ECL (default) State T ri-state Output enabled Output enabled Tri-state D IE SPECIFICATIONS N ame S ize R everse side P ad dimensions T hickness Value 62 x 65 mil GND 80 micron x 80 micron 10 mil B LOCK DIAGRAM OE Q XIN XOUT Oscillator Amplifier Q S2 PLL620-80 P ads #9, #18 & #25: Bond to GND to set to “0”, No connection results to “default” setting through internal pull-up. OE_CTRL: Logical states defined by PECL levels if OE_SELECT is “1” Logical states defined by CMOS levels if OE_SELECT is “0” O UTPUT FREQUENCY SELECTOR S2 0 1 (Default)* * Internally set to ‘Default’ through 60K Output I nput/2 Input p ull-up resistor 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 11/09/04 Page 1 GNDBUF GNDBUF GND GND GND GND GND P LL620-80 L ow Phase Noise XO (9.5-65MHz Output) E LECTRICAL SPECIFICATIONS 1 . Absolute Maximum Ratings P ARAMETERS S upply Voltage I nput Voltage, dc O utput Voltage, dc S torage Temperature A mbient Operating Temperature* J unction Temperature L ead Temperature (soldering, 10s) E SD Protection, Human Body Model SYMBOL V DD VI VO TS TA TJ MIN. - 0.5 - 0.5 - 65 - 40 MAX. 4 .6 V DD +0.5 V DD +0.5 150 85 1 25 260 2 UNITS V V V °C °C °C °C kV E xposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * N ote : Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2 . Crystal Specifications P ARAMETERS C rystal Resonator Frequency C rystal Loading Rating I nterelectrode Capacitance R ecommended ESR SYMBOL F XIN C L (xtal) C0 RE CONDITIONS F undamental D ie A T cut MIN. 19 TYP. 8* MAX. 65 5 30 UNITS MHz pF pF Ω N ote: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 3 . General Electrical Specifications P ARAMETERS S upply Current (Loaded Outputs) O perating Voltage O utput Clock Duty Cycle S hort Circuit Current SYMBOL I DD V DD CONDITIONS P ECL/LVDS/CMOS @ 5 0% V DD ( CMOS) @ 1.25V (LVDS) @ V DD – 1 .3V (PECL) MIN. 2 .97 45 45 45 TYP. MAX. 100/80/40 3.63 55 55 55 UNITS mA V % mA 50 50 50 ± 50 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 11/09/04 Page 2 P LL620-80 L ow Phase Noise XO (9.5-65MHz Output) 4 . Jitter Specifications P ARAMETERS P eriod jitter RMS at 27MHz P eriod jitter peak-to-peak at 27MHz A ccumulated jitter RMS at 27MHz A ccumulated jitter peak-to-peak at 27MHz R andom Jitter M easured on Wavecrest SIA 3000 CONDITIONS With capacitive decoupling between VDD and GND. Over 10,000 cycles With capacitive decoupling between VDD and GND. Over 1,000,000 cycles. “RJ” measured on Wavecrest SIA 3000 MIN. TYP. 2.3 18.5 2.3 24 2.3 MAX. 20 25 UNITS ps ps ps 5 . Phase Noise Specifications P ARAMETERS P hase Noise relative to carrier FREQUENCY 27MHz @10Hz -75 @100Hz -100 @1kHz -125 @10kHz -140 @100kHz -145 UNITS dBc/Hz N ote: Phase Noise measured on Agilent E5500 6 . CMOS Output Electrical Specifications P ARAMETERS O utput drive current (High Drive) O utput drive current (Standard Drive) O utput Clock Rise/Fall Time (Standard Drive) O utput Clock Rise/Fall Time (High Drive) SYMBOL I OH I OL I OH I OL CONDITIONS V OH = V DD -0.4V, V DD =3.3V V OL = 0 .4V, V DD = 3 .3V V OH = V DD -0.4V, V DD =3.3V V OL = 0 .4V, V DD = 3 .3V 0 .3V ~ 3.0V with 15 pF load 0 .3V ~ 3.0V with 15 pF load MIN. 30 30 10 10 TYP. MAX. UNITS mA mA mA mA 2.4 1.2 ns 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 11/09/04 Page 3 P LL620-80 L ow Phase Noise XO (9.5-65MHz Output) 7 . LVDS Electrical Characteristics P ARAMETERS O utput Differential Voltage V DD M agnitude Change O utput High Voltage O utput Low Voltage O ffset Voltage O ffset Magnitude Change P ower-off Leakage O utput Short Circuit Current SYMBOL V OD ∆ V OD V OH V OL V OS ∆ V OS I OXD I OSD CONDITIONS MIN. 2 47 - 50 TYP. 355 1 .4 1.1 1.2 3 ±1 - 5.7 MAX. 454 50 1.6 1.375 25 ± 10 -8 UNITS mV mV V V V mV uA mA R L = 1 00 Ω ( see figure) 0 .9 1 .125 0 V out = V DD o r GND V DD = 0 V 8 . LVDS Switching Characteristics P ARAMETERS D ifferential Clock Rise Time D ifferential Clock Fall Time LVDS Levels Test Circuit OUT SYMBOL tr tf CONDITIONS R L = 1 00 Ω C L = 1 0 pF (see figure) MIN. 0 .2 0.2 TYP. 0.7 0.7 MAX. 1.0 1.0 UNITS ns ns LVDS Switching Test Circuit OUT CL = 10pF 50Ω VOD VOS VDIFF RL = 100 Ω 50Ω CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% VDIFF 20% 0V 80% 20% tR tF 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 11/09/04 Page 4 P LL620-80 L ow Phase Noise XO (9.5-65MHz Output) 9 . PECL Electrical Characteristics P ARAMETERS O utput High Voltage O utput Low Voltage SYMBOL V OH V OL CONDITIONS R L = 5 0 Ω t o (V DD – 2 V) (see figure) MIN. V DD – 1 .025 MAX. V DD – 1 .620 UNITS V V 1 0. PECL Switching Characteristics P ARAMETERS C lock Rise Time C lock Fall Time SYMBOL tr tf PECL Levels Test Circuit CONDITIONS @ 20/80% - PECL @ 80/20% - PECL MIN. TYP. 0.6 0.5 MAX. 1.5 1.5 UNITS ns ns PECL Output Skew VDD OUT OUT 50Ω 2.0V 50% 50Ω OUT OUT tSKEW PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tR tF 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 11/09/04 Page 5 P LL620-80 P AD DESCRIPTIONS P ad # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Name G ND G ND O ptional GND G ND G ND R eserved G NDBUF G NDBUF O E_SEL LVDS PECL VDDBUF VDDBUF PECLB LVDSB CMOS GNDBUF OUTSEL1 R eserved N ot connected VDD O ptional VDD VDD VDD OUTSEL0 XIN XOUT N ot connected S2 OE_CTRL N ot connected X ( µ m) 248 361 4 73 587 702 8 74 1042 1171 1400 1400 1400 1400 1400 1400 1400 1400 1389 1232 1 042 8 54 659 5 59 459 358 194 109 109 1 09 109 109 1 09 L ow Phase Noise XO (9.5-65MHz Output) Y ( µ m) 109 109 109 109 109 109 109 109 125 259 476 616 716 871 1089 1227 1365 1365 1365 1365 1365 1365 1365 1365 1365 1223 1017 858 646 397 181 Ground. Ground. Optional Ground. Ground. Ground. Reserved for future use. Ground, buffer circuitry. Ground, buffer circuitry. This is the selector input to choose the OE control logic. See the OE SELECTION AND ENABLE table on page 1. Internal pull up. LVDS output. PECL output. Power supply, buffer circuitry. Power supply, buffer circuitry. Complementary PECL output. Complementary LVDS output. CMOS output. Ground, buffer circuitry. Selector input to choose the selected output type (PECL, LVDS, CMOS). See the OUTPUT SELECTION AND ENABLE table on page 1. Internal pull up. Reserved for future use. Not Connected. Power supply. Optional Power supply. Power supply. Power supply. Selector input to choose the selected output type (PECL, LVDS, CMOS). See the OUTPUT SELECTION AND ENABLE table on page 1. Internal pull up. Crystal input. See Crystal Specifications on page 3. Crystal output. See Crystal Specifications on page 3. Not Connected. Output Divide by Two selector pin, as presented on the OUTPUT FREQUENCY SELECTOR Table on page 1. Internal pull up. Used to enable/disable the output(s). See Output Selection and Enable table on page 1. Not connected. Description N ote: for optimal Phase Noise performance, it is recommended to bond all optional VDD and GND pads. 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 11/09/04 Page 6 P LL620-80 L ow Phase Noise XO (9.5-65MHz Output) O RDERING INFORMATION F or part ordering, please contact our Sales Department: 4 7745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 T he order number for this device is a combination of the following: Device number, Package type and Operating temperature range P ART NUMBER P LL620-80 P ART NUMBER DC T EMPERATURE C =COMMERCIAL I =INDUSTRIAL P ACKAGE TYPE D =DIE O rder Number P LL620-80DC Marking P620-80DC Package Option Die – Waffle Pack P haseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. L IFE SUPPORT POLICY : PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 4 7745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 w ww.phaselink.com R ev 11/09/04 Page 7