BULD50

BULD50KC, BULD50SL NPN SILICON TRANSISTOR WITH INTEGRATED DIODE Copyright © 1997, Power Innovations Limited, UK FEBRUARY 1994 - REVISED SEPTEMBER 1997 q Designed Specifically for High Frequency Electronic Ballasts Integrated Fast trr Anti-Parallel Diode, Enhancing Reliability Diode trr Typically 1 µs New Low-Height SL Power Package, TO220 Pin-Compatible Tightly Controlled Transistor Storage Times Voltage Matched Integrated Transistor and Diode Characteristics Optimised for Cool Running Diode-Transistor Charge Coupling Minimised to Enhance Frequency Stability B C E B C E TO-220 PACKAGE (TOP VIEW) q 1 2 3 q q Pin 2 is in electrical contact with the mounting base. q q MDTRACA SL PACKAGE (TOP VIEW) 1 2 3 q q description The new BULDxx range of transistors have been designed specifically for use in High Frequency Electronic Ballasts (HFEB’s). This range of switching transistors has tightly controlled storage times and an integrated fast trr antiparallel diode. The revolutionary design ensures that the diode has both fast forward and reverse recovery times, achieving the same performance as a discrete anti-parallel diode plus transistor. The integrated diode has minimal charge coupling with the transistor, increasing frequency stability, especially in lower power circuits where the circulating currents are low. By design, this new device offers a voltage matched integrated transistor and anti-parallel diode. device symbol C B E absolute maximum ratings at 25°C ¦ (unless otherwise noted) RATING Collector-emitter voltage (V BE = 0) Collector-base voltage (IE = 0) Collector-emitter voltage (IB = 0) Emitter-base voltage Continuous collector current Peak collector current (see Note 2) Continuous base current Peak base current (see Note 2) NOTES: 1. This value applies for tp = 1 s. 2. This value applies for tp = 10 ms, duty cycle ≤ 2%. ¦ ≤ 25°C case temperature for BULD50KC, and ≤ 25°C ambient temperature for BULD50SL BULD50KC BULD50SL (see Note 1) BULD50KC BULD50SL (see Note 1) SYMBOL VCES VCBO VCEO V EBO IC ICM IB IBM VALUE 600 600 400 9 3.5 6 1.5 2.5 UNIT V V V V A A A A PRODUCT INFORMATION Information is current as of publication date. Products conform to specifications in accordance with the terms of Power Innovations standard warranty. Production processing does not necessarily include testing of all parameters. 1 BULD50KC, BULD50SL NPN SILICON TRANSISTOR WITH INTEGRATED DIODE FEBRUARY 1994 - REVISED SEPTEMBER 1997 absolute maximum ratings at 25°C ¦ (unless otherwise noted) (continued) RATING Continuous device dissipation Maximum average continuous diode forward current Operating junction temperature range Storage temperature range BULD50KC BULD50SL SYMBOL Ptot IE(av) Tj Tstg VALUE 50 see Figure 11 0.5 -65 to +150 -65 to +150 UNIT W A °C °C electrical characteristics at 25°C case temperature PARAMETER V CEO(sus) ICES IEBO V BE(sat) VCE(sat) Collector-emitter sustaining voltage Collector-emitter cut-off current Emitter cut-off current Base-emitter saturation voltage Collector-emitter saturation voltage Forward current transfer ratio Anti-parallel diode forward voltage Anti-parallel diode reverse recovery time IC = 100 mA VCE = 600 V VEB = 9V TEST CONDITIONS L = 25 mH VBE = 0 IC = 0 IC = 750 mA IC = 750 mA IC = 1.5 A IC = 10 mA IC = 750 mA IC = 1.5 A (see Notes 3 and 4) (see Note 5) (see Notes 3 and 4) (see Notes 3 and 4) (see Notes 3 and 4) 10 10 10 0.9 0.2 0.4 17 15 15 1.25 1 20 20 1.5 V µs MIN 400 10 1 1.1 0.5 1 TYP MAX UNIT V µA mA V V IB = 150 mA IB = 150 mA IB = 300 mA VCE = 10 V VCE = VCE = IE = 1V 5V 1A hFE V EC trr NOTES: 3. These parameters must be measured using pulse techniques, tp = 300 µs, duty cycle ≤ 2%. 4. These parameters must be measured using voltage-sensing contacts, separate from the current carrying contacts, and located within 3.2 mm from the device body. 5. Tested in a typical High Frequency Electronic Ballast. thermal characteristics PARAMETER RθJA RθJC Junction to free air thermal resistance Junction to case thermal resistance BULD50KC BULD50SL BULD50KC MIN TYP MAX 62.5 115 2.5 UNIT °C/W °C/W inductive-load switching characteristics at 25°C case temperature PARAMETER tsv Storage time IC = 750 mA L = 1 mH TEST CONDITIONS IB(on) = 150 mA IB(off) = 150 mA VCC = 40 V V CLAMP = 300 V MIN TYP 3.35 MAX 4.5 UNIT µs resistive-load switching characteristics at 25°C case temperature PARAMETER tfi Current fall time IC = 750 mA V CC = 300 V TEST CONDITIONS IB(on) = 150 mA IB(off) = 150 mA MIN TYP 150 MAX 250 UNIT ns PRODUCT INFORMATION 2 BULD50KC, BULD50SL NPN SILICON TRANSISTOR WITH INTEGRATED DIODE FEBRUARY 1994 - REVISED SEPTEMBER 1997 TYPICAL CHARACTERISTICS FORWARD CURRENT TRANSFER RATIO vs COLLECTOR CURRENT 30 TC = 25°C IE - Instantaneous Forward Current - A hFE - Forward Current Transfer Ratio LDX50SHF ANTI-PARALLEL DIODE INSTANTANEOUS FORWARD CURRENT vs INSTANTANEOUS FORWARD VOLTAGE 10 TC = 25°C LDX50SVF 10 1·0 0·1 1·0 0·01 VCE = 1 V VCE = 5 V VCE = 10 V 0·1 1·0 10 0·01 0 0·5 1·0 1·5 2·0 2·5 3·0 IC - Collector Current - A VEC - Instantaneous Forward Voltage - V Figure 1. Figure 2. BASE-EMITTER SATURATION VOLTAGE vs CASE TEMPERATURE 1.0 VBE(sat) - Base-Emitter Saturation Voltage - V IC = 750 mA IB = 150 mA 0.9 LDX50SVB 0.8 0.7 0.6 0 25 50 75 100 TC - Case Temperature - °C Figure 3. PRODUCT INFORMATION 3 BULD50KC, BULD50SL NPN SILICON TRANSISTOR WITH INTEGRATED DIODE FEBRUARY 1994 - REVISED SEPTEMBER 1997 MAXIMUM SAFE OPERATING REGIONS MAXIMUM FORWARD-BIAS SAFE OPERATING AREA 10 LDX50CFB MAXIMUM FORWARD-BIAS SAFE OPERATING AREA 10 LDX50SFB IC - Collector Current - A 1·0 IC - Collector Current - A 1·0 0·1 BULD50KC TC = 25°C tp = 100 µs tp = 1 ms tp = 10 ms DC Operation 10 100 1000 0·1 BULD50SL TA = 25°C tp = 100 µs tp = 10 ms tp = 1 s 0·01 1·0 10 100 1000 0·01 1·0 VCE - Collector-Emitter Voltage - V VCE - Collector-Emitter Voltage - V Figure 4. Figure 5. MAXIMUM REVERSE-BIAS SAFE OPERATING AREA 8 LDX50SRB IB(on) = IC / 5 VBE(off) = -5 V TA = 25°C IC - Collector Current - A 6 4 2 0 0 100 200 300 400 500 600 700 800 VCE - Collector-Emitter Voltage - V Figure 6. PRODUCT INFORMATION 4 BULD50KC, BULD50SL NPN SILICON TRANSISTOR WITH INTEGRATED DIODE FEBRUARY 1994 - REVISED SEPTEMBER 1997 THERMAL INFORMATION THERMAL RESPONSE JUNCTION TO AMBIENT vs POWER PULSE DURATION ZθJA/R θJA - Normalised Transient Thermal Impedance 1·0 60% 40% 20% 10% 0·1 LDX50CZA BULD50KC TA = 25°C 0·01 0% duty cycle = t1/t2 Read time at end of t1, t1 t2 Z  T J ( max ) – T A = P D ( peak) •  θ JA  • R θ JA ( max ) R θ JA   0·001 10-4 10-3 10-2 10-1 10 0 101 102 103 t1 - Power Pulse Duration - s Figure 7. THERMAL RESPONSE JUNCTION TO AMBIENT vs POWER PULSE DURATION ZθJA/R θJA - Normalised Transient Thermal Impedance 0·1 60% 40% LDX50SZA BULD50SL TA = 25°C 20% 10% 0·01 t1 duty cycle = t1/t2 Read time at end of t1, 0% t2 Z  T J ( max ) – T A = P D ( peak) •  θ JA  • R θ JA ( max ) R θ JA   10-3 10-2 10 -1 100 101 102 103 0·001 10-4 t1 - Power Pulse Duration - s Figure 8. PRODUCT INFORMATION 5 BULD50KC, BULD50SL NPN SILICON TRANSISTOR WITH INTEGRATED DIODE FEBRUARY 1994 - REVISED SEPTEMBER 1997 THERMAL INFORMATION THERMAL RESPONSE JUNCTION TO CASE vs POWER PULSE DURATION Zθ JC/R θJC - Normalised Transient Thermal Impedance 1·0 60% 40% 20% 10% LDX50CZC BULD50KC TC = 25°C 0·1 0% t1 duty cycle = t1/t2 Read time at end of t1, t2 Z  T J ( max) – T C = P D ( peak ) •  θ JC  • R θ JC ( max) R θ JC   0·01 10-4 10-3 10-2 10-1 100 10 1 t1 - Power Pulse Duration - s Figure 9. MAXIMUM POWER DISSIPATION JUNCTION TO AMBIENT vs POWER PULSE DURATION 1000 Ptot - Maximum Power Dissipation - W LDX50CPA BULD50KC TA = 25°C 0% 100 10% 10 20% 40% 60% 1·0 10-4 10-3 10-2 10-1 10 0 101 102 103 t1 - Power Pulse Duration - s Figure 10. PRODUCT INFORMATION 6 BULD50KC, BULD50SL NPN SILICON TRANSISTOR WITH INTEGRATED DIODE FEBRUARY 1994 - REVISED SEPTEMBER 1997 THERMAL INFORMATION MAXIMUM POWER DISSIPATION JUNCTION TO AMBIENT vs POWER PULSE DURATION 100 Ptot - Maximum Power Dissipation - W 0% LDX50SPA BULD50SL TA = 25°C 10 10% 20% 40% 60% 1·0 10-4 10-3 10 -2 10-1 10 0 101 10 2 103 t1 - Power Pulse Duration - s Figure 11. MAXIMUM POWER DISSIPATION JUNCTION TO CASE vs POWER PULSE DURATION 1000 0% Ptot - Maximum Power Dissipation - W LDX50CPC BULD50KC TC = 25°C 10% 20% 40% 100 60% 10 10-4 10-3 10-2 10-1 100 101 t1 - Power Pulse Duration - s Figure 12. PRODUCT INFORMATION 7 BULD50KC, BULD50SL NPN SILICON TRANSISTOR WITH INTEGRATED DIODE FEBRUARY 1994 - REVISED SEPTEMBER 1997 MECHANICAL DATA TO-220 3-pin plastic flange-mount package This single-in-line package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. The compound will withstand soldering temperature with no deformation, and circuit performance characteristics will remain stable when operated in high humidity conditions. Leads require no additional cleaning or processing when used in soldered assembly. TO220 4,70 4,20 ø 3,96 3,71 10,4 10,0 2,95 2,54 6,6 6,0 15,90 14,55 1,32 1,23 see Note B see Note C 6,1 3,5 0,97 0,61 1 2 3 1,70 1,07 14,1 12,7 2,74 2,34 5,28 4,88 2,90 2,40 0,64 0,41 VERSION 1 V ERSION 2 ALL LINEAR DIMENSIONS IN MILLIMETERS NOTES: A. The centre pin is in electrical contact with the mounting tab. B. Mounting tab corner profile according to package version. C. Typical fixing hole centre stand off height according to package version. Version 1, 18.0 mm. Version 2, 17.6 mm. MDXXBE PRODUCT INFORMATION 8 BULD50KC, BULD50SL NPN SILICON TRANSISTOR WITH INTEGRATED DIODE FEBRUARY 1994 - REVISED SEPTEMBER 1997 MECHANICAL DATA SL003 3-pin plastic single-in-line package This single-in-line package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. The compound will withstand soldering temperature with no deformation, and circuit performance characteristics will remain stable when operated in high humidity conditions. Leads require no additional cleaning or processing when used in soldered assembly. SL003 10,2 (0.400) MAX 4,57 (0.180) MAX 8,31 (0.327) MAX Index Dot 12,9 (0.492) MAX 6,60 (0.260) 6,10 (0.240) 4,267 (0.168) MIN 1 2 3 Pin Spacing 2,54 (0.100) T.P. (see Note A) 2 Places 1,854 (0.073) MAX 0,356 (0.014) 0,203 (0.008) 3 Places 0,711 (0.028) 0,559 (0.022) 3 Places ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES NOTES: A. Each pin centerline is located within 0,25 (0.010) of its true longitudinal position. B. Body molding flash of up to 0,15 (0.006) may occur in the package lead plane. MDXXAD PRODUCT INFORMATION 9 BULD50KC, BULD50SL NPN SILICON TRANSISTOR WITH INTEGRATED DIODE FEBRUARY 1994 - REVISED SEPTEMBER 1997 IMPORTANT NOTICE Power Innovations Limited (PI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to verify, before placing orders, that the information being relied on is current. PI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with PI's standard warranty. Testing and other quality control techniques are utilized to the extent PI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except as mandated by government requirements. PI accepts no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor is any license, either express or implied, granted under any patent right, copyright, design right, or other intellectual property right of PI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. PI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS. Copyright © 1997, Power Innovations Limited PRODUCT INFORMATION 10