PO100HSTL50ASU

PO100HSTL50A Dual Differential LVDS/LVPECL/HSTL to LVTTL Translator Dual LVTTL/LVCMOS to Differential HSTL Translator FEATURES: • Patented Technology • Differential LVDS/LVPECL/HSTL to LVTTL Translator - Operating frequency up to 1GHz with 2pf load - Operating frequency up to 800MHz with 5pf load - Operating frequency up to 450MHz with 15pf load - Very low output pin to pin skew < 150ps - Propagation delay < 1.8ns max with 15pf load • LVTTL/LVCMOS to Differential HSTL Translator - Operating frequency up to 1.65GHz with 5pf load - Operating frequency up to 500MHz with 15pf load - Very low output pin to pin skew < 100ps - Propagation delay < 1.4ns max with 15pf load • 2.4V to 3.6V power supply • Industrial temperature range: –40°C to 85°C • Available in 16-pin 150ml SOIC package 04/19/09 DESCRIPTION: Potato Semiconductor’s PO100HSTL50A is designed for world top performance using submicron CMOS technology to achieve 1GHz LVTTL output frequency with less than 1.8ns propagation delay and 1.65GHz HSTL output frequency with less than 1.4ns propagation delay. The PO100HSTL50A is a low-skew, The small outline 16 pin package and the low skew design to make it ideal for applications which require the translation of a clock or a data signal. Pin Configuration 1B 1A 1R RE 2R 2A 2B GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Logic Block Diagram VC C 1D 1Y 1Z DE 2Z 2Y 2D 1D DE 2D 15 12 9 14 13 10 11 2 1 6 7 1Y 1Z 2Y 2Z 1A 1B 2A 2B 1R RE 2R 3 4 5 Pin Description RECEIVER INPUTS VID = VA– VB VID ≥ 50 mV 50 MV < VID < 50 mV VID ≤ –50 mV Open X RE L L L L H RECEIVER OUTPUT R H ? L H Z DRIVER INPUTS D L H Open X DE H H H L DRIVER OUTPUTS Y L H L Z Z H L H Z 1 C opyright © Potato Semiconductor Corporation PO100HSTL50A Dual Differential LVDS/LVPECL/HSTL to LVTTL Translator Dual LVTTL/LVCMOS to Differential HSTL Translator 04/19/09 Maximum Ratings Description Storage Temperature Operation Temperature Operation Voltage Input Voltage Output Voltage Max -65 to 150 -40 to 85 -0.5 to +4.6 -0.5 to Vcc -0.5 to Vcc+0.5 Unit °C °C V V V Note: stresses greater than listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability specification is not implied. Pin Characteristics Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input B Pullup Resistor Input A Pulldown Resistor Test Conditions Minimum Typical 4 88 88 Maximum Units pF KΩ KΩ DC Electrical Characteristics Symbol Description Output High voltage Output Low voltage Input High voltage Input Low voltage Input High current Input Low current Clamp diode voltage Test Conditions Vcc=3V Vin=VIH or VIL, IOH= -12mA Vcc=3V Vin=VIH or VIL, IOH=12mA Guaranteed Logic HIGH Level (Input Pin) Guaranteed Logic LOW Level (Input Pin) Vcc = 3.6V and Vin = Vcc Vcc = 3.6V and Vin = 0V Vcc = Min. And IIN = -18mA M in Typ M ax Unit VOH VOL VIH VIL IIH IIL VIK Notes: 1. 2. 3. 4. 5. 2.4 2 -0.5 - 3 0.3 -0.7 0.5 Vcc 0.8 1 -1 -1.2 V V V V uA uA V For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25 ° C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. VoH = Vcc – 0.6V at rated current 2 C opyright © Potato Semiconductor Corporation PO100HSTL50A Dual Differential LVDS/LVPECL/HSTL to LVTTL Translator Dual LVTTL/LVCMOS to Differential HSTL Translator 04/19/09 Power Supply Characteristics Symbol Description Quiescent Power Supply Current Test Conditions (1) Vcc=Max, Vin=Vcc or GND M in Typ M ax Unit IccQ Notes: 1. 2. 3. 4. - 0.1 30 uA For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25° C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. Receiver Switching Characteristics Symbol Description Propagation Delay D to Output pair Test Conditions (1) CL = 15pF CL = 15pF CL = 15pF 0.8V – 2.0V CL = 15pF, 125MHz CL = 15pF, 125MHz CL =15pF CL = 5pF CL = 2pF M ax Unit tPD tPZH or tPZL tPHZ or tPLZ tr/tf tsk(o) tsk(pp) fmax fmax fmax Notes: 1.8 2.5 2.5 0.8 150 300 450 250 800 300 1000 400 ns ns ns ns ps ps MHz MHz MHz Output Enable Time Output Disable Time Rise/Fall Time Output Pin to Pin Skew (Same Package) Output Skew (Different Package) Input Frequency Input Frequency Input Frequency 1. See test circuits and waveforms. 2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested. 3. Airflow of 1m/s is recommended for frequencies above 133MHz Test Circuit Vcc 50Ω Pulse Generator V+ VV+ V- D.U.T 50Ω 15pF to 2pF 3 C opyright © Potato Semiconductor Corporation PO100HSTL50A Dual Differential LVDS/LVPECL/HSTL to LVTTL Translator Dual LVTTL/LVCMOS to Differential HSTL Translator 04/19/09 Test Waveforms FIGURE 1. LVDS/ PECL/ ECL/ HSTL /DIFFERENTIAL INPUT WAVEFORM DEFINITIONS VCC VCC= 3.3V VIH VPP VIL VEE=0.0V VEE VPP RANGE 0V-VCC FIGURE 2. LVTTL OUTPUT tr,tf, VO FIGURE 3. Propogation Delay, Output pulse skew, and output-to-output skew for D to output INPUT CLOCK TPLH TPD VPP TPHL VO OUTPUT CLOCK tSK(O) ANOTHER OUTPUT CLOCK 4 Copyright © Potato Semiconductor Corporation PO100HSTL50A Dual Differential LVDS/LVPECL/HSTL to LVTTL Translator Dual LVTTL/LVCMOS to Differential HSTL Translator 04/19/09 Driver Switching Characteristics Symbol Description Propagation Delay D to Output pair Output Enable Time Output Disable Time Rise/Fall Time Output Pin to Pin Skew (Same Package) Output Skew (Different Package) Input Frequency Input Frequency Test Conditions (1) CL = 15pF CL = 15pF CL = 15pF 0.8V – 2.0V CL = 15pF, 125MHz CL = 15pF, 125MHz CL =15pF CL = 5pF Typ M ax Unit tPD tPZH or tPZL tPHZ or tPLZ tr/tf tsk(o) tsk(pp) fmax fmax Notes: 1.4 2.5 2.5 0.8 100 250 500 250 1.65 300 ns ns ns ns ps ps MHz GHz 1. See test circuits and waveforms. 2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested. 3. Airflow of 1m/s is recommended for frequencies above 133MHz Test Circuit Vcc 15pF to 2pF Pulse Generator D.U.T 50Ω 15pF to 2pF 5 C opyright © Potato Semiconductor Corporation PO100HSTL50A Dual Differential LVDS/LVPECL/HSTL to LVTTL Translator Dual LVTTL/LVCMOS to Differential HSTL Translator 04/19/09 Test Waveforms FIGURE 1. LVTTL/LVCMOS INPUT WAVEFORM DEFINITION 3V Input 1.5V 0V FIGURE 2. HSTL OUTPUT tr,tf, 20-80% VO FIGURE 3. Propogation Delay, Output pulse skew, and output-to-output skew for D to output pair INPUT CLOCK TPLH TPD TPHL VO OUTPUT CLOCK tSK(O) ANOTHER OUTPUT CLOCK 6 Copyright © Potato Semiconductor Corporation PO100HSTL50A Dual Differential LVDS/LVPECL/HSTL to LVTTL Translator Dual LVTTL/LVCMOS to Differential HSTL Translator 04/19/09 Packaging Mechanical Drawing: 16 pin SOIC 16 .149 .157 3.78 3.99 .2284 .2440 5.80 6.20 1 .386 .393 9.80 10.00 .0155 0.393 .0260 0.660 .053 .068 1.35 1.75 .0075 .0098 0.19 0.25 .016 .050 0.41 1.27 .050 BSC 1.27 .013 .020 0.330 0.508 .0040 .0098 0.10 0.25 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS 7 C opyright © Potato Semiconductor Corporation PO100HSTL50A Dual Differential LVDS/LVPECL/HSTL to LVTTL Translator Dual LVTTL/LVCMOS to Differential HSTL Translator 04/19/09 Ordering Information Ordering Code PO100HSTL50ASU PO100HSTL50ASR 16 pin SOIC 16 pin SOIC Package Tube Tape and reel Pb-free & Green Pb-free & Green Top-Marking PO100HSTL23AS PO100HSTL23AS TA -40°C to 85°C -40°C to 85°C IC Package Information PACKAGE CODE PACKAGE TYPE TAPE WIDTH (mm) TAPE PITCH (mm) PIN 1 LOCATION TAPE TRAILER LENGTH QTY PER REEL TAPE LEADER LENGTH QTY PER TUBE S SOIC 16 16 8 Top Left Corner 39 (12”) 3000 64 (20”) 48 8 Copyright © Potato Semiconductor Corporation