PO49FCT32803G

PO49FCT32803 3.3V 1:7 CMOS Clock Buffered Driver 500MHz TTL/CMOS Potato Chip 11/22/05 FEATURES: . Operating frequency up to 500MHz with 2pf load . Operating frequency up to 400MHz with 5pf load . Operating frequency up to 230MHz with 15pf load . Operating frequency up to 85MHz with 50pf load . Very low output pin to pin skew < 250ps . Very low pulse skew < 200ps . VCC = 1.65V to 3.6V . Propagation delay < 2.3ns max with 15pf load . Low input capacitance: 3pf typical . 1:7 fanout . Available in 16pin 150mil wide QSOP package . Available in 16pin 173mil wide TSSOP package DESCRIPTION: Potato Semiconductor’s PO49FCT32803G is designed for world top performance using submicron CMOS technology to achieve 500MHz output frequency with less than 250ps output skew. PO49FCT32803G is a 3.3V CMOS 1 input to 7 Output Buffered Driver with integrated series damping resistors on all outputs to match 50 ohm transmission line impedance. Typical applications are clock and signal distribution. Pin Configuration Logic Block Diagram Pin Description Pin Name INA O1 to O7 Description Input Outputs 1 Copyright © 2005, Potato Semiconductor Corporation PO49FCT32803 3.3V 1:7 CMOS Clock Buffered Driver 500MHz TTL/CMOS Potato Chip 11/22/05 Maximum Ratings Description Storage Temperature Operation Temperature Operation Voltage Input Voltage Output Voltage Max -65 to 150 -40 to 85 -0.5 to +4.6 -0.5 to Vcc+0.5 -0.5 to Vcc+0.5 Unit °C °C V V V Note: stresses greater than listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability specification is not implied. DC Electrical Characteristics Symbol Description Output High voltage Output Low voltage Input High voltage Input Low voltage Input High current Input Low current Clamp diode voltage Series Resistor Test Conditions Vcc=3V Vin=VIH or VIL, IOH= -8mA Vcc=3V Vin=VIH or VIL, IOH=12mA Guaranteed Logic HIGH Level (Input Pin) Guaranteed Logic LOW Level (Input Pin) Vcc = 3.6V and Vin = 3.6V Vcc = 3.6V and Vin = 0V Vcc = Min. And IIN = -18mA Min Typ M ax Unit VOH VOL VIH VIL IIH IIL VIK Rs Notes: 1. 2. 3. 4. 5. 2.4 2 -0.5 - 3 0.4 -0.7 22 0.5 Vcc 0.8 1 -1 -1.2 V V V V uA uA V Ω For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25 ° C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. VoH = Vcc – 0.6V at rated current 2 Copyright © 2005, Potato Semiconductor Corporation PO49FCT32803 3.3V 1:7 CMOS Clock Buffered Driver 500MHz TTL/CMOS Potato Chip 11/22/05 Power Supply Characteristics Symbol Description Quiescent Power Supply Current Test Conditions (1) Vcc=Max, Vin=Vcc or GND M in Typ M ax Unit IccQ Notes: 1. 2. 3. 4. - 0.1 30 uA For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25° C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. Capacitance Parameters (1) Description Input Capacitance Output Capacitance Test Conditions Vin = 0V Vout = 0V Typ M ax Unit Cin Cout Notes: 3 - 4 6 pF pF 1 This parameter is determined by device characterization but not production tested. Switching Characteristics Symbol Description Propagation Delay A to Bn Propagation Delay A to Bn Rise/Fall Time Pulse Skew (Same Package) Output Pin to Pin Skew (Same Package) Output Skew (Different Package) Input Frequency Input Frequency Input Frequency Input Frequency Test Conditions (1) CL = 15pF CL = 15pF 0.8V – 2.0V CL = 15pF CL = 15pF CL = 15pF CL = 5 0 p F CL = 1 5 p F CL = 5pF CL = 2pF M ax Unit tPLH tPHL tr/tf tsk(p) tsk(o) tsk(pp) fmax fmax fmax fmax Notes: 2.3 2.3 1 0.2 0.25 0.4 85 230 400 500 ns ns ns ns ns ns MHz MHz MHz MHz 1. See test circuits and waveforms. 2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested. 3. Airflow of 1m/s is recommended for frequencies above 133MHz 3 Copyright © 2005, Potato Semiconductor Corporation PO49FCT32803 3.3V 1:7 CMOS Clock Buffered Driver 500MHz TTL/CMOS Potato Chip 11/22/05 Test Waveforms Test Circuit 50Ω 4 Copyright © 2005, Potato Semiconductor Corporation PO49FCT32803 3.3V 1:7 CMOS Clock Buffered Driver 500MHz TTL/CMOS Potato Chip 11/22/05 Packaging Mechanical Drawing: 16 pin QSOP Packaging Mechanical Drawing: 16 pin TSSOP 5 Copyright © 2005, Potato Semiconductor Corporation PO49FCT32803 3.3V 1:7 CMOS Clock Buffered Driver 500MHz TTL/CMOS Potato Chip Ordering Information Ordering Code PO49FCT32803T PO49FCT32803Q Package Code T Q Package Description Pb-free & Green, 16-pin TSSOP Pb-free & Green, 16-pin QSOP 0 1/05/06 6 Copyright © 2005, Potato Semiconductor Corporation