PO49FCT32806

PO49FCT32806 3.3V Dual 1:5 CMOS Invert Clock Buffered Driver 700MHz TTL/CMOS Potato Chip 11/22/05 FEATURES: . Operating frequency up to 700MHz with 2pf load . Operating frequency up to 500MHz with 5pf load . Operating frequency up to 300MHz with 15pf load . Operating frequency up to 120MHz with 50pf load . Very low output pin to pin skew < 250ps . Very low pulse skew < 200ps . VCC = 1.65V to 3.6V . Propagation delay < 2.9ns max with 15pf load . Low input capacitance: 3pf typical . Dual 1:5 invert fanout . Available in 20pin 300mil wide SOIC package . Available in 20pin 150mil wide QSOP package DESCRIPTION: Potato Semiconductor’s PO49FCT32806G is designed for world top performance using submicron CMOS technology to achieve 700MHz TTL output frequency with less than 200ps output pulse skew. PO49FCT32806G is a 3.3V CMOS Dual 1 input to 5 outputs Invert Buffered driver to achieve 700MHz output frequency with integrated series damping resistors on all outputs to match 50 ohm transmission line impedance. Typical applications are crystal oscillator, ring oscillator, clock and signal distribution. Pin Configuration Logic Block Diagram Pin Description Pin Name INA, INB Description Signal or clock Inputs Hi-Z State Output Enable Inputs (Active LOW) OAn, OBn MON Vcc, GND Signal or clock Outputs Monitor Output Power, Ground L L H H Inputs INA, INB L H L H Outputs OAn, OBn H L Z Z MON H L H L 1 Copyright © 2005, Potato Semiconductor Corporation PO49FCT32806 3.3V Dual 1:5 CMOS Invert Clock Buffered Driver 700MHz TTL/CMOS Potato Chip 11/22/05 Maximum Ratings Description Storage Temperature Operation Temperature Operation Voltage Input Voltage Output Voltage Max -65 to 150 -40 to 85 -0.5 to +4.6 -0.5 to Vcc+0.5 -0.5 to Vcc+0.5 Unit °C °C V V V Note: stresses greater than listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability specification is not implied. DC Electrical Characteristics Symbol Description Output High voltage Output Low voltage Input High voltage Input Low voltage High Impedance Output current High Impedance Output current Input High current Input Low current Clamp diode voltage Test Conditions Vcc=3V Vin=VIH or VIL, IOH= -8mA Vcc=3V Vin=VIH or VIL, IOH=12mA Guaranteed Logic HIGH Level (Input Pin) Guaranteed Logic LOW Level (Input Pin) Vcc = 3.6V and Vo = Vcc Vcc = 3.6V and Vo = 0V Vcc = 3.6V and Vin = 3.6V Vcc = 3.6V and Vin = 0V Vcc = Min. And IIN = -18mA Min Typ M ax Unit VOH VOL VIH VIL IOZH IOZL IIH IIL VIK Notes: 1. 2. 3. 4. 5. 2.4 2 -0.5 - 3 0.3 -0.7 0.5 Vcc 0.8 1 -1 1 -1 -1.2 V V V V uA uA uA uA V For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25 ° C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. VoH = Vcc – 0.6V at rated current 2 Copyright © 2005, Potato Semiconductor Corporation PO49FCT32806 3.3V Dual 1:5 CMOS Invert Clock Buffered Driver 700MHz TTL/CMOS Potato Chip 11/22/05 Power Supply Characteristics Symbol Description Quiescent Power Supply Current Test Conditions (1) Vcc=Max, Vin=Vcc or GND M in Typ M ax Unit IccQ Notes: 1. 2. 3. 4. - 0.1 30 uA For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25° C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. Capacitance Parameters (1) Description Input Capacitance Output Capacitance Test Conditions Vin = 0V Vout = 0V Typ M ax Unit Cin Cout Notes: 3 - 4 6 pF pF 1 This parameter is determined by device characterization but not production tested. Switching Characteristics Symbol Description Propagation Delay INA to OAn, INB to OBn Output Enable Time Output Disable Time Rise/Fall Time Pulse Skew (Same Package) Output Pin to Pin Skew (Same Package) Output Skew (Different Package) Input Frequency Input Frequency Input Frequency Input Frequency Test Conditions (1) CL = 1 5 p F CL = 15pF CL = 15pF 0.8V – 2.0V CL = 15pF, 125MHz CL = 15pF, 125MHz CL = 15pF, 125MHz CL = 50pF CL =15pF CL = 5pF CL = 2pF M ax Unit tPLH & tPHL tPZH or tPZL tPHZ or tPLZ tr/tf tsk(p) tsk(o) tsk(pp) fmax fmax fmax fmax Notes: 2.9 2.5 2.5 1 0.2 0.25 0.4 120 300 500 700 ns ns ns ns ns ns ns MHz MHz MHz MHz 1. See test circuits and waveforms. 2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested. 3. Airflow of 1m/s is recommended for frequencies above 133MHz 3 Copyright © 2005, Potato Semiconductor Corporation PO49FCT32806 3.3V Dual 1:5 CMOS Invert Clock Buffered Driver 700MHz TTL/CMOS Potato Chip 11/22/05 Test Waveforms Test Circuit 500 Ω 50Ω 50 Ω 500 Ω 4 Copyright © 2005, Potato Semiconductor Corporation PO49FCT32806 3.3V Dual 1:5 CMOS Invert Clock Buffered Driver 700MHz TTL/CMOS Potato Chip 11/22/05 Packaging Mechanical Drawing: 20 pin QSOP Packaging Mechanical Drawing: 20 pin SOIC 5 Copyright © 2005, Potato Semiconductor Corporation PO49FCT32806 3.3V Dual 1:5 CMOS Invert Clock Buffered Driver 700MHz TTL/CMOS Potato Chip Ordering Information Ordering Code PO49FCT32806S PO49FCT32806Q Package Code S Q Package Description Pb-free & Green, 20-pin SOIC Pb-free & Green, 20-pin QSOP 0 1/05/06 6 Copyright © 2005, Potato Semiconductor Corporation