PO74G112ASU

DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET PO74G112A 04/19/09 74 Series GHz Logic FEATURES: . Patented technology . Specified From –40°C to 85°C, –40°C to 125°C, and –55°C to 125°C . Operating frequency up to 750MHz with 15pf load . VCC Operates from 1.65V to 3.6V . Propagation delay < 2ns max with 15pf load . Low input capacitance: 4pf typical . Latch-Up Performance Exceeds 250 mA Per JESD 17 . ESD Protection Exceeds JESD 22 . 5000-VHuman-BodyModel (A114-A) . 200-VMachineModel (A115-A) . Available in 16pin 150mil wide SOIC package . Available in 16pin 173mil wide TSSOP package DESCRIPTION: Potato Semiconductor’s PO74G112A is designed for world top performance using submicron CMOS technology to achieve 750MHz TTL /CMOS output frequency with less than 2ns propagation delay. This dual negative-edge-triggered J-K flip-flop is designed for 1.65-V to 3.6-V VCC operation. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V/5V system environment. Pin Configuration 1CLK 1K 1J 1PRE 1Q 1Q 2Q GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Logic Block Diagram VCC 1CLR 2CLR 2CLK 2K 2J 2PRE 2Q Pin Description INPUTS PRE L H L H H H H H CLR H L L H H H H H CLK X X X ↓ ↓ ↓ ↓ H J X X X L H L H X K X X X L L H H X Q0 OUTPUTS Q H L H Q0 H L Toggle Q0 Q L H H Q0 L H 1CLK 1K 1J 1PRE 1Q 1Q 2Q GND J K PRE Q 1 Q CLR J K PRE Q 1 Q CLR VCC 1CLR 2CLR 2CLK 2K 2J 2PRE 2Q 1 C opyright © Potato Semiconductor Corporation DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET PO74G112A 04/19/09 74 Series GHz Logic Maximum Ratings Description Storage Temperature Operation Temperature Operation Voltage Input Voltage Output Voltage Max -65 to 150 -55 to 125 -0.5 to +4.6 -0.5 to +5.5 -0.5 to Vcc+0.5 Unit °C °C V V V Note: stresses greater than listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability specification is not implied. DC Electrical Characteristics Symbol Description Output High voltage Output Low voltage Input High voltage Input Low voltage Input High current Input Low current Clamp diode voltage Test Conditions Vcc=3V Vin=VIH or VIL, IOH= -12mA Vcc=3V Vin=VIH or VIL, IOH=12mA Guaranteed Logic HIGH Level (Input Pin) Guaranteed Logic LOW Level (Input Pin) Vcc = 3.6V and Vin = 5.5V Vcc = 3.6V and Vin = 0V Vcc = Min. And IIN = -18mA Min Typ M ax Unit VOH VOL VIH VIL IIH IIL VIK Notes: 1. 2. 3. 4. 5. 2.4 2 -0.5 - 3 0.3 -0.7 0.5 5.5 0.8 1 -1 -1.2 V V V V uA uA V For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25 ° C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. VoH = Vcc – 0.6V at rated current 2 Copyright © Potato Semiconductor Corporation DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET PO74G112A 04/19/09 74 Series GHz Logic Power Supply Characteristics Symbol Description Quiescent Power Supply Current Test Conditions (1) Vcc=Max, Vin=Vcc or GND M in Typ M ax Unit IccQ Notes: 1. 2. 3. 4. - 0.1 40 uA For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25° C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. Capacitance Parameters (1) Description Input Capacitance Output Capacitance Test Conditions Vin = 0V Vout = 0V Typ Unit Cin Cout Notes: 4 6 pF pF 1 This parameter is determined by device characterization but not production tested. Switching Characteristics Symbol Description Setup time before CLK Hold time, data after CLK Propagation Delay CLK to Q Propagation Delay CLK to Q Rise/Fall Time Input Frequency CL = 1 5 p F CL = 1 5 p F 0.8V – 2.0V CL=2pF - 15pF Test Conditions (1) M ax tsu th tPLH t PHL tr/tf fmax Notes: - Min Unit 0.5 0.5 ns ns ns ns ns MHz 2 2 0.8 - 750 1. See test circuits and waveforms. 2. tPLH, tPHL, tsu, and th are production tested. All other parameters guaranteed but not production tested. 3. Airflow of 1m/s is recommended for frequencies above 500MHz 3 Copyright © Potato Semiconductor Corporation DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET PO74G112A 04/19/09 74 Series GHz Logic Test Waveforms VI Timing Input tw VI Input VM VM 0V VOLTAGE WAVEFORMS PULSE DURA TION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Data Input tsu VM th VI VM 0V VM 0V VI Input tPLH Output tPHL Output VM VM VM VM 0V tPHL VOH VM VOL tPLH VOH VM VOL VOLTAGE WAVEFORMS PROPAGA TION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Control tPZL VI VM VM 0V tPLZ VLOAD/2 VM tPZH VOL + VΔ tPHZ VM VOH - VΔ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING VOL Output Waveform 1 S1 at V LOAD (see Note B) Output Waveform 2 S1 at GND (see Note B) Test Circuit Vcc Pulse Generator D.U.T 50Ω 15pF to 2pF 4 Copyright © Potato Semiconductor Corporation DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET PO74G112A 04/19/09 74 Series GHz Logic Packaging Mechanical Drawing: 16 pin SOIC 16 .149 .157 3.78 3.99 .2284 .2440 5.80 6.20 1 .386 .393 9.80 10.00 .0075 .0098 0.19 0.25 .016 .050 0.41 1.27 .0155 0.393 .0260 0.660 .053 .068 1.35 1.75 .050 BSC 1.27 .013 .020 0.330 0.508 .0040 .0098 0.10 0.25 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Packaging Mechanical Drawing: 16 pin TSSOP X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS 5 Copyright © Potato Semiconductor Corporation DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET PO74G112A 04/19/09 74 Series GHz Logic Ordering Information Ordering Code PO74G112ASU PO74G112ASR PO74G112ATU PO74G112ATR 16-pin SOIC 16-pin SOIC Package Tube Tape and reel Tube Tape and reel Pb-free & Green Pb-free & Green Pb-free & Green Pb-free & Green Top-Marking PO74G112AS PO74G112AS PO74G112AT PO74G112AT TA -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C 16-pin TSSOP 16-pin TSSOP IC Package Information PACKAGE CODE PACKAGE TYPE TAPE WIDTH (mm) TAPE PITCH (mm) PIN 1 LOCATION TAPE TRAILER LENGTH QTY PER REEL TAPE LEADER LENGTH QTY PER TUBE S T SOIC 16 TSSOP 16 16 12 8 8 Top Left Corner Top Left Corner 39 (12”) 39 (12”) 3000 3000 64 (20”) 64 (20”) 48 96 7 Copyright © Potato Semiconductor Corporation