PO74G125A

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS PO74G125A 07/26/06 74 Series GHz Logic FEATURES: . Patented technology . Operating frequency up to 1.125GHz with 2pf load . Operating frequency up to 550MHz with 5pf load . Operating frequency up to 300MHz with 15pf load . VCC Operates from 1.65V to 3.6V . Propagation delay < 1.5ns max with 15pf load . Low input capacitance: 4pf typical . Available in 14pin 150mil wide SOIC package DESCRIPTION: Potato Semiconductor’s PO74G125A is designed for world top performance using submicron CMOS technology to achieve 1.125GHz TTL /CMOS output frequency with less than 1.5ns propagation delay. This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC operation. The PO74G125A features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V/5V system environment. Pin Configuration 1OE 1A 1Y 2OE 2A 2Y GND Logic Block Diagram VCC 4OE 4A 4Y 2OE 4 5 6 1OE 1A 1 2 3 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1Y 3OE 3A 3Y 3OE 10 9 8 2A 2Y Pin Description INPUTS OE L L H A H L X OUTPUT Y H L Z 3A 3Y 4OE 4A 13 12 11 4Y 1 C o p y r i g h t © 2005-2006, Potato Semiconductor Corporation QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS PO74G125A 07/26/06 74 Series GHz Logic Maximum Ratings Description Storage Temperature Operation Temperature Operation Voltage Input Voltage Output Voltage Max -65 to 150 -40 to 85 -0.5 to +4.6 -0.5 to +5.5 -0.5 to Vcc+0.5 Unit °C °C V V V Note: stresses greater than listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability specification is not implied. DC Electrical Characteristics Symbol Description Output High voltage Output Low voltage Input High voltage Input Low voltage Input High current Input Low current Clamp diode voltage Test Conditions Vcc=3V Vin=VIH or VIL, IOH= -12mA Vcc=3V Vin=VIH or VIL, IOH=12mA Guaranteed Logic HIGH Level (Input Pin) Guaranteed Logic LOW Level (Input Pin) Vcc = 3.6V and Vin = 5.5V Vcc = 3.6V and Vin = 0V Vcc = Min. And IIN = -18mA Min Typ M ax Unit VOH VOL VIH VIL IIH IIL VIK Notes: 1. 2. 3. 4. 5. 2.4 2 -0.5 - 3 0.3 -0.7 0.5 5.5 0.8 50 -50 -1.2 V V V V uA uA V For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25 ° C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. VoH = Vcc – 0.6V at rated current 2 C o p y r i g h t © 2005-2006, Potato Semiconductor Corporation QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS PO74G125A 07/27/06 74 Series GHz Logic Power Supply Characteristics Symbol Description Quiescent Power Supply Current Power Supply Current per Input High Test Conditions (1) Vcc=Max, Vin=Vcc or GND Vcc=Max, Vin= Vcc-0.6V Min Typ Max Unit IccQ ∆Icc Notes: 1. 2. 3. 4. 5. - 0.1 50 30 300 uA uA For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25° C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. VoH = Vcc – 0.6V at rated current Capacitance Parameters (1) Description Input Capacitance Output Capacitance Test Conditions Vin = 0V Vout = 0V Typ Unit Cin Cout Notes: 4 6 pF pF 1 This parameter is determined by device characterization but not production tested. Switching Characteristics Symbol Description Propagation Delay A to Y Propagation Delay A to Y Output Enable Time Output Disable Time Rise/Fall Time Input Frequency Input Frequency Input Frequency Test Conditions (1) CL = 15pF CL = 15pF CL = 15pF CL = 15pF 0.8V – 2.0V CL =15pF CL = 5pF CL = 2pF M ax Unit tPLH tPHL tPZH or tPZL tPHZ or tPLZ tr/tf fmax fmax fmax Notes: 1.5 1.5 2.5 2.5 0.8 300 550 1125 ns ns ns ns ns MHz MHz MHz 1. See test circuits and waveforms. 2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested. 3. Airflow of 1m/s is recommended for frequencies above 133MHz 3 C o p y r i g h t © 2005-2006, Potato Semiconductor Corporation QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS PO74G125A 07/27/06 74 Series GHz Logic Test Waveforms Test Circuit 500 Ω 50Ω 15pF to 2pF 50 Ω 500 Ω 4 C o p y r i g h t © 2005-2006, Potato Semiconductor Corporation QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS PO74G125A 07/26/06 74 Series GHz Logic Packaging Mechanical Drawing: 14 pin 150mil SOIC 0.244 6.20 0.228 5.80 0.010 0.007 0.25 0.17 0.050 1.27 0.016 0.40 X.XX Denotes dimensions in inches X.XX X.XX Denotes dimensions in millimenters X.XX 5 C o p y r i g h t © 2005-2006, Potato Semiconductor Corporation QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS PO74G125A 10/27/07 74 Series GHz Logic Ordering Information Ordering Code PO74G125ASU PO74G125ASR 14pin SOIC 14pin SOIC Package Tube Tape and reel Pb-free & Green Pb-free & Green Top-Marking PO74G125AS PO74G125AS TA -40°C to 85°C -40°C to 85°C IC Package Information PACKAGE CODE PACKAGE TYPE TAPE WIDTH (mm) TAPE PITCH (mm) PIN 1 LOCATION TAPE TRAILER LENGTH QTY PER REEL TAPE LEADER LENGTH QTY PER TUBE S SOIC 14 16 8 Top Left Corner 39 (12”) 3000 64 (20”) 55 6 C o p y r i g h t © 2005-2006, Potato Semiconductor Corporation