PO74HSTL314A

PO74HSTL314A 3.3V 2:4 Differential Clock/Data Fanout Buffer 500MHz HSTL Potato Chip 0 7/28/06 FEATURES: . Patented Technology . Four HSTL differential outputs . The two pair of LVDS/LVPECL/HSTL/ differential or single-ended inputs . Hot-swappable/-insertable . Operating frequency up to 500MHz with 2pf load . Operating frequency up to 480MHz with 5pf load . Operating frequency up to 400MHz with 15pf load . Very low output pin to pin skew < 80ps . Very low pulse skew < 80ps . 2.8-ns propagation delay (typical) . 2.4V to 3.6V power supply . Industrial temperature range: –40°C to 85°C . 20-pin 209 mil SSOP package DESCRIPTION: The PO74HSTL314 is a low-skew, 2-to-4 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on 0.35um CMOS technology and has a fully differential internal architecture that is optimized to achieve low signal skews at operating frequencies of up to 500MHz . The device features two differential input paths that are multiplexed plexed internally. This mux is controlled by the CLK_SEL pin. The PO74HSTL314 may function not only as a differential clock buffer but also as a signal-level translator and fanout on HSTL or LVCMOS / LVTTL single-ended signal to four HSTL differential loads. Since the PO74HSTL314 introduces negligible jitter to the timing budget, it is the ideal choice for distributing high frequency, high precision clocks across back-planes and boards in communication systems. Pin Configuration 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q0 Q0# Q1 Q1# Q2 Q2# Q3 Q3# VCC Logic Block Diagram VCC CLKA CLKA# VEE VCC CLKB CLKB# VEE CLK_SEL Q2 Q2# Q0 Q0# VCC NC VCC CLK_SEL CLKA CLKA# CLKB CLKB# VEE VCC PO74HSTL314 Q1 Q1# Q3 Q3# VEE 1 Copyright © Potato Semiconductor Corporation PO74HSTL314A 3.3V 2:4 Differential Clock/Data Fanout Buffer 500MHz HSTL Potato Chip 08/03/06 Pin Definitions Pin 1, 10,11,20,3 2 4 5 6 7 8 9 18, 16,14,12 19, 17,15,13 VCC NC CLK_SEL CLKA CLKA# CLKB CLKB# VEE Q[0:3]# Q[0:3] I,PD I,PD I,PU I,PD I,PU GND O O LVCMOS Name I/O VCC Type Power No connect Input clock select with pull down resistor LVDS, PECL, HSTL Default differential clock input LVDS, PECL, HSTL Input clock select with pull up resistor LVDS, PECL, HSTL Input clock select with pull down resistor LVDS, PECL, HSTL Input clock select with pull up resistor Description Power supply, positive connection Power HSTL HSTL Power Ground Complement output Ture output Function Table Control CLK_SEL 0 CLKA, CLKA# input pair is active (Default condition with no connection to pin) CLKA can be driven with LVDS, ECL, PECL, HSTL or T TL compatible signals with respective power configurations CLKB, CLKB# input pair is active CLKB can be driven with LVDS, ECL, PECL, HSTL or T TL compatible signals with respective power configurations 1 Pin Characteristics Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 88 88 Maximum Units pF KΩ KΩ 2 Copyright © Potato Semiconductor Corporation PO74HSTL314A 3.3V 2:4 Differential Clock/Data Fanout Buffer 500MHz HSTL Potato Chip 0 7/28/06 Maximum Ratings Description Storage Temperature Operation Temperature Operation Voltage Input Voltage Output Voltage Max -65 to 150 -40 to 85 -0.5 to +4.6 -0.5 to +5.5 -0.5 to Vcc+0.5 Unit °C °C V V V Note: stresses greater than listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability specification is not implied. DC Electrical Characteristics Symbol Description Output High voltage Output Low voltage Clamp diode voltage Power off output leakage current Test Conditions Vcc=3V Vin=VIH or VIL, IOH= -12mA Vcc=3V Vin=VIH or VIL, IOH=12mA Vcc = Min. And IIN = -18mA Vcc = 0V. Vi or Vo = 0V to 5.5V Min Typ M ax Unit VOH VOL VIK IOFF Notes: 1. 2. 3. 4. 5. 2.4 - 3 0.3 -0.7 - 0.5 -1.2 +5 - V V V uA Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25 ° C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. VoH = Vcc – 0.6V at rated current 3 Copyright © Potato Semiconductor Corporation PO74HSTL314A 3.3V 2:4 Differential Clock/Data Fanout Buffer 500MHz HSTL Potato Chip 0 7/28/06 Power Supply Characteristics Symbol Description Quiescent Power Supply Current Test Conditions (1) Vcc=Max, Vin=Vcc or GND M in Typ M ax Unit IccQ Notes: 1. 2. 3. 4. - 0.1 30 uA For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25° C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. Switching Characteristics Symbol Description Propagation Delay CLKA or CLKB to Output pair Test Conditions (1) CL = 15pF 0.8V – 2.0V CL = 15pF, 125MHz CL = 15pF, 125MHz CL = 15pF, 125MHz CL =15pF CL = 5pF CL = 2pF M ax Unit tPD tr/tf tsk(p) tsk(o) tsk(pp) fmax fmax fmax Notes: 3.2 0.8 80 80 350 400 250 480 300 500 400 ns ns ps ps ps MHz MHz MHz Rise/Fall Time Pulse Skew (Same Package) Output Pin to Pin Skew (Same Package) Output Skew (Different Package) Input Frequency Input Frequency Input Frequency 1. See test circuits and waveforms. 2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested. 3. Airflow of 1m/s is recommended for frequencies above 133MHz 4 Copyright © Potato Semiconductor Corporation PO74HSTL314A 3.3V 2:4 Differential Clock/Data Fanout Buffer 500MHz HSTL Potato Chip 07/10/06 Test Waveforms FIGURE 1. LVDS/ PECL/ ECL/ HSTL /DIFFERENTIAL INPUT WAVEFORM DEFINITIONS VCC VCC= 3.3V VIH VPP VIL VEE=0.0V VEE VPP RANGE 0V-VCC FIGURE 2. HSTL/HSTL OUTPUT tr,tf, 20-80% VO FIGURE 3. Propogation Delay, Output pulse skew, and output-to-output skew for both CLKA or CLKB to output pair INPUT CLOCK VPP TPLH TPD OUTPUT CLOCK TPHL VO tSK(O) ANOTHER OUTPUT CLOCK 5 Copyright © Potato Semiconductor Corporation PO74HSTL314A 3.3V 2:4 Differential Clock/Data Fanout Buffer 500MHz HSTL Potato Chip 07/10/06 Test Circuit 50Ω 50pF to 2pF 50Ω 50pF to 2pF Packaging Mechanical Drawing: 20 pin SSOP 20 0.55 .022 0.95 .037 .197 .220 5.00 5.60 .291 .322 7.40 8.20 1 .272 .295 6.90 7.50 .078 2.00 Max .004 .009 0.09 0.25 SEATING PLANE .0256 BSC 0.65 .0098 Max. 0.25 .002 Min 0.050 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS 6 Copyright © Potato Semiconductor Corporation PO74HSTL314A 3.3V 2:4 Differential Clock/Data Fanout Buffer 500MHz HSTL Potato Chip 0 7/28/06 Ordering Information Ordering Code PO74HSTL314ASU PO74HSTL314ASR 20pin SSOP 20pin SSOP Package Tube Tape and reel Pb-free & Green Pb-free & Green Top-Marking PO74HSTL314AS PO74HSTL314AS TA -40°C to 85°C -40°C to 85°C 7 Copyright © Potato Semiconductor Corporation