PO74HSTL85350ATU

PO74HSTL85350A LVCMOS Input to HSTL Output 1:4 Fanout Buffer 300MHz HSTL Potato Chip 0 3/24/07 FEATURES: . Patented Technology . Four HSTL differential outputs . Two single LVTTL/LVCMOS inputs . Operating frequency up to 300MHz with 15 pf load . Very low output pin to pin skew < 50ps . 3.4-ns propagation delay (max) . 2.4V to 3.6V power supply . Industrial temperature range: –40°C to 85°C . 20-pin TSSOP package DESCRIPTION: The PO74HSTL85350A is a low-skew, 1-to-4 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on CMOS technology and has a fully differential internal architecture that is optimized to achieve low signal skews at operating frequencies of up to 300MHz . The device features two single-ended input paths that are multiplexed internally. This mux is controlled by the CLK_SEL pin. The PO74HSTL85350A functions as a signal-level translator and fanout on LVCMOS / LVTTL single-ended signal to four HSTL differential loads. Since the PO74HSTL85350A introduces negligible jitter to the timing budget, it is the ideal choice for distributing high frequency, high precision clocks across back-planes and boards in communication systems. Pin Configuration VE E CLK_EN CLK_SEL CLK0 nc CLK1 nc nc nc VC C 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Logic Block Diagram Q0 nQ0 VC C Q1 nQ1 Q2 nQ2 VC C Q3 nQ3 CLK_EN D Q LE CLK0 CLK1 0 1 Q0 nQ0 Q1 nQ1 CLK_SEL Q2 nQ2 Q3 nQ3 1 Copyright © Potato Semiconductor Corporation PO74HSTL85350A LVCMOS Input to HSTL Output 1:4 Fanout Buffer 300MHz HSTL Potato Chip 03/24/07 Pin Definitions Pin 10,13,18 5, 7, 8, 9 3 4 6 2 1 19, 16,14,11 20, 17,15,12 VCC NC CLK_SEL CLK0 CLK1 CLK_EN VEE Q[0:3]# Q[0:3] I,PD I,PD I,PD I,PU GND O O LVCMOS Name I/O VCC Type Power No connect Input clock select with pull down resistor LVCMOS/ LVTTL LVCOMS / LVTTL clock input LVCMOS/ LVTTL LVCOMS / LVTTL clock input LVCMOS/ LVTTL Clock enabled Description Power supply, positive connection Power HSTL HSTL Power Ground Complement output Ture output Control Input Function Table Inputs CLK_EN 0 0 1 1 CLK_SEL 0 1 0 1 Selected Source CLK0 CL K 1 CLK0 CLK1 Q0:Q3 Disabled; LOW Disabled; LOW Enabled Enabled Outputs nQ0:nQ3 Disabled; HIGH Disabled; HIGH Enabled Enabled Input/ Output Function Table Inputs CLK0 or CLK1 0 1 Q0:Q3 LOW HIGH Outputs nQ0:nQ3 HIGH LOW Pin Characteristics Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 88 88 Maximum Units pF KΩ KΩ 2 Copyright © Potato Semiconductor Corporation PO74HSTL85350A LVCMOS Input to HSTL Output 1:4 Fanout Buffer 300MHz HSTL Potato Chip 03/24/07 Maximum Ratings Description Storage Temperature Operation Temperature Operation Voltage Input Voltage Output Voltage Max -65 to 150 -40 to 85 -0.5 to +4.6 -0.5 to +5.5 -0.5 to Vcc+0.5 Unit °C °C V V V Note: stresses greater than listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability specification is not implied. DC Electrical Characteristics Symbol Description Output High voltage Output Low voltage Clamp diode voltage Test Conditions Vcc=3V Vin=VIH or VIL, IOH= -12mA Vcc=3V Vin=VIH or VIL, IOH=12mA Vcc = Min. And IIN = -18mA Min Typ M ax Unit VOH VOL VIK 2.4 - 3 0.3 -0.7 0.5 -1.2 V V V Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Notes: 1. 2. 3. 4. 5. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25 ° C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. VoH = Vcc – 0.6V at rated current 3 C opyright © Potato Semiconductor Corporation PO74HSTL85350A LVCMOS Input to HSTL Output 1:4 Fanout Buffer 03/24/07 300MHz HSTL Potato Chip Power Supply Characteristics Symbol Description Quiescent Power Supply Current Test Conditions (1) Vcc=Max, Vin=Vcc or GND M in Typ M ax Unit IccQ Notes: 1. 2. 3. 4. - 0.1 30 uA For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25° C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. Switching Characteristics Symbol Description Propagation Delay CLKA or CLKB to Output pair Test Conditions (1) CL = 15pF 0.8V – 2.0V CL = 15pF, 125MHz CL = 15pF, 125MHz CL =15pF M ax Unit tPD tr/tf tsk(o) tsk(pp) fmax 3.4 0.8 50 350 300 250 ns ns ps ps MHz Rise/Fall Time Output Pin to Pin Skew (Same Package) Output Skew (Different Package) Input Frequency 1. See test circuits and waveforms. 2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested. 3. Airflow of 1m/s is recommended for frequencies above 133MHz 4 C opyright © Potato Semiconductor Corporation PO74HSTL85350A LVCMOS Input to HSTL Output 1:4 Fanout Buffer 300MHz HSTL Potato Chip 0 3/24/07 Test Waveforms FIGURE 1. LVTTL/LVCMOS INPUT WAVEFORM DEFINITION 3V Input FIGURE 2. HSTL OUTPUT 1.5V 0V tr,tf, 20-80% VO FIGURE 3. Propogation Delay, Output pulse skew, and output-to-output skew for D to output pair INPUT CLOCK TPLH TPD OUTPUT CLOCK TPHL VO tSK(O) ANOTHER OUTPUT CLOCK FIGURE 4. CLK_EN Timing Diagram Disabled Enabled CLK CLK_EN nQ0:nQ3 Q0:Q3 5 C opyright © Potato Semiconductor Corporation PO74HSTL85350A LVCMOS Input to HSTL Output 1:4 Fanout Buffer 300MHz HSTL Potato Chip 0 3/24/07 Test Circuit Vcc 15pF to 2pF Pulse Generator D.U.T 50Ω 15pF to 2pF Packaging Mechanical Drawing: 20 pin TSSOP 20 .169 .177 4.3 4.5 .018 .030 0.45 0.75 .238 .269 6.1 6.7 1 .252 .260 6.4 6.6 .047 1.20 Max SEATING PLANE .004 0.09 .008 0.20 .0256 BSC 0.65 .007 .012 0.19 0.30 .002 0.05 .006 0.15 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS 6 C opyright © Potato Semiconductor Corporation PO74HSTL85350A LVCMOS Input to HSTL Output 1:4 Fanout Buffer 300MHz HSTL Potato Chip 02/20/07 Ordering Information Ordering Code PO74HSTL85350ATU PO74HSTL85350ATR 20 pin TSSOP 20 pin TSSOP Package Tube Tape and reel Pb-free & Green Pb-free & Green Top-Marking TA PO74HSTL85350AT -40°C to 85°C PO74HSTL85350AT -40°C to 85°C 7 C opyright © Potato Semiconductor Corporation