The Q24S30033 surface mounted DC-DC converter offers
unprecedented performance in the industry-standard quarter brick
format. This is accomplished through the use of patent pending circuit
and packaging techniques to achieve ultra-high efficiency, excellent
thermal performance and a very low body profile.
In telecommunications applications the Q Family 30 A converters
provide thermal performance that far exceeds all quarter bricks and is
comparable even to existing half-bricks. Low body profile and the
preclusion of heatsinks minimize airflow shadowing, thus enhancing
cooling for downstream devices. The use of 100% surface-mount
technologies for assembly, coupled with advanced electric and
thermal circuitry and packaging, results in a product with extremely
high quality and reliability.
RoHS lead free and lead-solder-exempt products are available
Delivers up to 30 A
Higher current capability at 70 ºC than existing quarter brick and 30 A
half-brick converters
High efficiency: 88% @ 30 A, 89% @ 15 A
Starts-up into pre-biased output
No minimum load required
No heatsink required
Low profile: 0.26” [6.6 mm]
Light weight: 1 oz [28 g] typical
Industry-standard footprint: 1.45” x 2.30”
Meets Basic Insulation Requirements of EN60950
On-board LC input filter
Fixed frequency operation
Fully protected
Remote output sense
Output voltage trim range: +10%/-20%
Trim resistor via industry-standard equations
High reliability: MTBF 2.6 million hours, calculated per Telcordia TR332, Method I Case 1
Positive or negative logic ON/OFF option
UL 60950 recognized in U.S. & Canada, and DEMKO certified per
IEC/EN 60950
Meets conducted emissions requirements of FCC Class B and
EN55022 Class B with external filter
All materials meet UL94, V-0 flammability rating
Q24S30033
2
Conditions: TA = 25ºC, Airflow = 300 LFM (1.5 m/s), Vin = 24 VDC, unless otherwise specified.
PARAMETER
CONDITIONS / DESCRIPTION
MIN
TYP
MAX
UNITS
40
VDC
Absolute Maximum Ratings
Input Voltage
Continuous
0
Operating Ambient Temperature
-40
85
°C
Storage Temperature
-55
125
°C
Input Characteristics
Operating Input Voltage Range
18
24
36
VDC
Turn-on Threshold
16
17
17.5
VDC
Turn-off Threshold
15
16
16.5
VDC
30,000
μF
30
ADC
36
40
ADC
45
55
A
8
Arms
Input Under Voltage Lockout
Non-latching
Output Characteristics
External Load Capacitance
Plus full load (resistive)
Output Current Range
0
Current Limit Inception
Non-latching
Peak Short-Circuit Current
Non-latching. Short=10mΩ.
RMS Short-Circuit Current
Non-latching
33
Isolation Characteristics
I/O Isolation
2000
Isolation Capacitance
VDC
ρF
230
Isolation Resistance
10
MΩ
Feature Characteristics
Switching Frequency
Output Voltage Trim Range
435
1
Use trim equations on Page 6
-20
kHz
+10
%
+10
%
127
%
Remote Sense Compensation1
Percent of VOUT(NOM)
Output Over-Voltage Protection
Non-latching
Over-Temperature Shutdown (PCB)
Non-latching
118
°C
Auto-Restart Period
Applies to all protection features
100
ms
2.5
ms
117
Turn-On Time
122
ON/OFF Control (Positive Logic)
Converter Off
-20
0.8
VDC
Converter On
2.4
20
VDC
Converter Off
2.4
20
VDC
Converter On
-20
0.8
VDC
6.3
ADC
ON/OFF Control (Negative Logic)
Input Characteristics
Maximum Input Current
30 ADC, 1.8 VDC Out @ 18 VDC In
Input Stand-by Current
Vin = 24 V, converter disabled
3.5
mAdc
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3
Input No Load Current (0 load on the output)
Vin = 24 V, converter enabled
Input Reflected-Ripple Current
See Figure 21 - 25MHz bandwidth
Input Voltage Ripple Rejection
120Hz
140
mAdc
6
mAPK-PK
TBD
dB
Output Characteristics
Output Voltage Set Point (no load)
-40ºC to 85ºC
3.267
3.300
3.333
VDC
±2
±5
mV
Output Regulation
Over Line
Over Load
±2
Output Voltage Range
Over line, load and temperature
3.250
Output Ripple and Noise - 25MHz bandwidth
Full load + 10 μF tantalum + 1 μF ceramic
30
±5
mV
3.350
VDC
50
mVPK-PK
Dynamic Response
Load Change 25% of Iout Max, di/dt = 0.1 A/μS Co = 1 μF ceramic (Fig.16)
50
mV
140
mV
100
µs
100% Load
88
%
50% Load
89
%
di/dt = 5 A/μS
Co = 450 μF tant. + 1 μF ceramic (Fig.17)
Setting Time to 1%
Efficiency
1)
Vout can be increased up to 10% via the sense leads or up to 10% via the trim function, however total output voltage trim
from all sources should not exceed 10% of VOUT(nom), in order to insure specified operation of over-voltage protection
circuitry. See further discussion at end of Output Voltage Adjust /TRIM section.
These power converters have been designed to be stable with no external capacitors when used in low inductance input
and output circuits.
However, in many applications, the inductance associated with the distribution from the power source to the input of the
converter can affect the stability of the converter. The addition of a 33 µF electrolytic capacitor with an ESR < 1 across
the input helps ensure stability of the converter. In many applications, the user has to use decoupling capacitance at the
load. The power converter will exhibit stable operation with external load capacitance up to 30,000 µF.
The ON/OFF pin is used to turn the power converter on or off remotely via a system signal. There are two remote control
options available, positive logic and negative logic and both are referenced to Vin(-). Typical connections are shown in
Fig. 1.
Q
TM
Vin (+)
Family
Converter
(Top View)
ON/OFF
Vin
Vout (+)
SENSE (+)
TRIM
Rload
SENSE (-)
Vin (-)
Vout (-)
CONTROL
INPUT
Figure 1. Circuit configuration for ON/OFF function.
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The positive logic version turns on when the ON/OFF pin is at logic high and turns off when at logic low. The converter is on
when the ON/OFF pin is left open.
The negative logic version turns on when the pin is at logic low and turns off when the pin is at logic high. The ON/OFF pin
can be hard wired directly to Vin(-) to enable automatic power up of the converter without the need of an external control
signal.
ON/OFF pin is internally pulled-up to 5 V through a resistor. A mechanical switch, open collector transistor, or FET can be
used to drive the input of the ON/OFF pin. The device must be capable of sinking up to 0.2 mA at a low level voltage of
0.8 V. An external voltage source of ±20 V max. may be connected directly to the ON/OFF input, in which case it should be
capable of sourcing or sinking up to 1 mA depending on the signal polarity. See the Start-up Information section for system
timing waveforms associated with use of the ON/OFF pin.
The remote sense feature of the converter compensates for voltage drops occurring between the output pins of the converter
and the load. The SENSE(-) (Pin 5) and SENSE(+) (Pin 7) pins should be connected at the load or at the point where regulation
is required (see Fig. 2).
Q
TM
Vin (+)
Family
Converter
(Top View)
ON/OFF
Vin
Vout (+)
Rw
100
SENSE (+)
TRIM
Rload
SENSE (-)
10
Vin (-)
Vout (-)
Rw
Figure 2. Remote sense circuit configuration.
If remote sensing is not required, the SENSE(-) pin must be connected to the Vout(-) pin (Pin 4), and the SENSE(+) pin must
be connected to the Vout(+) pin (Pin 8) to ensure the converter will regulate at the specified output voltage. If these
connections are not made, the converter will deliver an output voltage that is slightly higher than the specified value.
Because the sense leads carry minimal current, large traces on the end-user board are not required. However, sense traces
should be located close to a ground plane to minimize system noise and insure optimum performance. When wiring
discretely, twisted pair wires should be used to connect the sense lines to the load to reduce susceptibility to noise.
The converter’s output over-voltage protection (OVP) senses the voltage across Vout(+) and Vout(-), and not across the
sense lines, so the resistance (and resulting voltage drop) between the output pins of the converter and the load should be
minimized to prevent unwanted triggering of the OVP.
When utilizing the remote sense feature, care must be taken not to exceed the maximum allowable output power capability
of the converter, equal to the product of the nominal output voltage and the allowable output current for the given conditions.
When using remote sense, the output voltage at the converter can be increased by as much as 10% above the nominal
rating in order to maintain the required voltage across the load. Therefore, the designer must, if necessary, decrease the
maximum current (originally obtained from the derating curves) by the same percentage to ensure the converter’s actual
output power remains at or below the maximum allowable output power.
The converter’s output voltage can be adjusted up 10% or down 20% relative to the rated output voltage by the addition of
an externally connected resistor. Trim up to 10% is guaranteed only at Vin ≥ 20 V, and it is marginal (8% to 10%) at Vin = 18
V.
The TRIM pin should be left open if trimming is not being used. To minimize noise pickup, a 0.1 µF capacitor is connected
internally between the TRIM and SENSE(-) pins.
To increase the output voltage, refer to Fig. 3. A trim resistor, RT-INCR, should be connected between the TRIM (Pin 6) and
SENSE(+) (Pin 7), with a value of:
RTINCR
5.11 (100 Δ) VONOM 626
- 10.22
1.225Δ
Δ
[kΩ],
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Q24S30033
5
where,
RTINCR Required value of trim-up resistor kΩ]
VONOM Nominal value of output voltage [V]
Δ
VOREQ
(VO -REQ VO -NOM)
X 100
VO -NOM
[%]
Desired (trimmed) output voltage [V].
When trimming up, care must be taken not to exceed the converter‘s maximum allowable output power. See previous section
for a complete discussion of this requirement.
To decrease the output voltage (Fig. 4), a trim resistor, RT-DECR, should be connected between the TRIM (Pin 6) and
SENSE(-) (Pin 5), with a value of:
RTDECR
511
10.22
|Δ|
[kΩ]
where,
RTDECR Required value of trim-down resistor [kΩ] and Δ is defined above.
Note:
The above equations for calculation of trim resistor values match those typically used in conventional industry-standard quarterbricks.
Q
TM
Vin (+)
Vin
Family
Converter
Vout (+)
(Top View)
SENSE (+)
ON/OFF
R T-INCR
TRIM
Rload
SENSE (-)
Vin (-)
Vout (-)
Figure 3. Configuration for increasing output voltage.
Q
TM
Vin (+)
Vin
ON/OFF
Family
Converter
Vout (+)
(Top View)
SENSE (+)
TRIM
Rload
R T-DECR
SENSE (-)
Vin (-)
Vout (-)
Figure 4. Configuration for decreasing output voltage.
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Trimming/sensing beyond 110% of the rated output voltage is not an acceptable design practice, as this condition could
cause unwanted triggering of the output over-voltage protection (OVP) circuit. The designer should ensure that the difference
between the voltages across the converter’s output pins and its sense pins does not exceed 0.33 V, or:
[VOUT() VOUT()] [VSENSE() VSENSE()] 0.33 [V]
This equation is applicable for any condition of output sensing and/or output trim.
Input under-voltage lockout is standard with this converter. The converter will shut down when the input voltage drops below
a pre-determined voltage.
The input voltage must be at least 17.5 V for the converter to turn on. Once the converter has been turned on, it will shut off
when the input voltage drops below 15 V. This feature is beneficial in preventing deep discharging of batteries used in
telecom applications.
The converter is protected against over-current or short circuit conditions. Upon sensing an over-current condition, the
converter will switch to constant current operation and thereby begin to reduce output voltage. When the output voltage
drops below 1.2 Vdc, the converter will shut down (Fig. 24).
Once the converter has shut down, it will attempt to restart nominally every 100 ms with a 3% duty cycle (Fig 25). The
attempted restart will continue indefinitely until the overload or short circuit conditions are removed or the output voltage
rises above 1.2 Vdc.
The converter will shut down if the output voltage across Vout(+) (Pin 8) and Vout(-) (Pin 4) exceeds the threshold of the OVP
circuitry. The OVP circuitry contains its own reference, independent of the output voltage regulation loop. Once the converter
has shut down, it will attempt to restart every 100 ms until the OVP condition is removed.
The converter will shut down under an over-temperature condition to protect itself from overheating caused by operation
outside the thermal derating curves, or operation in abnormal conditions such as system fan failure. After the converter has
cooled to a safe operating temperature, it will automatically restart.
The converters meet North American and International safety regulatory requirements per UL60950 and EN60950. Basic
Insulation is provided between input and output.
To comply with safety agencies requirements, an input line fuse must be used external to the converter. A 10-A fuse is
recommended for use with this product.
EMC requirements must be met at the end-product system level, as no specific standards dedicated to EMC characteristics
of board mounted component dc-dc converters exist. However, di/dt tests its converters to several system level standards,
primary of which is the more stringent EN55022, Information technology equipment - Radio disturbance characteristics Limits and methods of measurement.
With the addition of a simple external filter (see application notes), all versions of the Q24S30 converters pass the
requirements of Class B conducted emissions per EN55022 and FCC, and meet at a minimum, Class A radiated emissions
per EN 55022 and Class B per FCC Title 47CFR, Part 15-J. Please contact di/dt Applications Engineering for details of this
testing.
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Q24S30033
7
VIN
Scenario #1: Initial Startup From Bulk Supply
ON/OFF function enabled, converter started via application of
VIN. See Figure 5.
Time
t0
Comments
ON/OFF pin is ON; system front-end power is
toggled on, VIN to converter begins to rise.
t1
VIN crosses Under-Voltage Lockout protection circuit
threshold; converter enabled.
t2
Converter begins to respond to turn-on command
(converter turn-on delay).
t3
Converter VOUT reaches 100% of nominal value.
For this example, the total converter startup time (t3- t1) is
typically 2.5 ms.
ON/OFF
STATE
OFF
ON
VOUT
t0
t1 t2
t
t3
Figure 5. Start-up scenario #1.
Scenario #2: Initial Startup Using ON/OFF Pin
With VIN previously powered, converter started via ON/OFF pin.
See Figure 6.
Time
t0
t1
Comments
VINPUT at nominal value.
Arbitrary time when ON/OFF pin is enabled (converter
enabled).
t2
End of converter turn-on delay.
t3
Converter VOUT reaches 100% of nominal value.
For this example, the total converter startup time (t3- t1) is
typically 2.5 ms.
VIN
ON/OFF
STATE OFF
ON
VOUT
t0
t1 t2
t
t3
Figure 6. Startup scenario #2.
Scenario #3: Turn-off and Restart Using ON/OFF Pin
With VIN previously powered, converter is disabled and then
enabled via ON/OFF pin. See Figure 7.
VIN
Time
t0
t1
Comments
VIN and VOUT are at nominal values; ON/OFF pin ON.
ON/OFF pin arbitrarily disabled; converter output falls
to zero; turn-on inhibit delay period (100 ms typical) is
initiated, and ON/OFF pin action is internally inhibited.
t2
ON/OFF pin is externally re-enabled.
If (t2- t1) ≤ 100 ms, external action of ON/OFF
pin is locked out by startup inhibit timer.
If (t2- t1) > 100 ms, ON/OFF pin action is
internally enabled.
t3
Turn-on inhibit delay period ends. If ON/OFF pin is
ON, converter begins turn-on; if off, converter awaits
ON/OFF pin ON signal; see Figure 5.
t4
End of converter turn-on delay.
t5
Converter VOUT reaches 100% of nominal value.
For the condition, (t2- t1) ≤ 100 ms, the total converter startup time
(t5- t2) is typically 102.5 ms. For (t2- t1) > 100 ms, startup will be
typically 2.5 ms after release of ON/OFF pin.
100 ms
ON/OFF
STATE OFF
ON
VOUT
t0
t1
t2
t3 t4
t5
t
Figure 7. Startup scenario #3.
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Q24S30033
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The converter has been characterized for many operational aspects, to include thermal derating (maximum load current as
a function of ambient temperature and airflow) for vertical and horizontal mounting, efficiency, start-up and shutdown
parameters, output ripple and noise, transient response to load step-change, overload and short circuit.
The following pages contain specific plots or waveforms associated with the converter. Additional comments for specific
data are provided below.
All data presented were taken with the converter soldered to a test board, specifically a 0.060” thick printed wiring board
(PWB) with four layers. The top and bottom layers were not metalized. The two inner layers, comprising two-ounce copper,
were used to provide traces for connectivity to the converter.
The lack of metalization on the outer layers as well as the limited thermal connection ensured that heat transfer from the
converter to the PWB was minimized. This provides a worst-case but consistent scenario for thermal derating purposes.
All measurements requiring airflow were made in di/dt’s vertical and horizontal wind tunnel facilities using Infrared (IR)
thermography and thermocouples for thermometry.
Ensuring components on the converter do not exceed their ratings is important to maintaining high reliability. If one
anticipates operating the converter at or close to the maximum loads specified in the derating curves, it is prudent to check
actual operating temperatures in the application. Thermographic imaging is preferable; if this capability is not available, then
thermocouples may be used. di/dt recommends the use of AWG #40 gauge thermocouples to ensure measurement
accuracy. Careful routing of the thermocouple leads will further minimize measurement error. Refer to Figure 26 for optimum
measuring thermocouple location.
Load current vs. ambient temperature and airflow rates are given in Figs. 8 -11. Ambient temperature was varied between
25°C and 85°C, with airflow rates from 30 to 500 LFM (0.15 to 2.5 m/s), and vertical and horizontal converter mounting.
For each set of conditions, the maximum load current was defined as the lowest of:
(i)
The output current at which either any FET junction temperature did not exceed a maximum specified temperature
(either 105°C or 120°C) as indicated by the thermographic image, or
(ii) The nominal rating of the converter (30 A)
During normal operation, derating curves with maximum FET temperature less than or equal to 120°C should not be
exceeded. Temperature on the PCB at the thermocouple location shown in Fig. 26 should not exceed 118°C in order to
operate inside the derating curves.
Efficiency vs. load current plots are shown in Figs. 12 and 14 for ambient temperature of 25ºC, airflow rate of 300 LFM (1.5
m/s), both vertical and horizontal orientations, and input voltages of 18 V, 27 V and 36 V. Also, plots of efficiency vs. load
current, as a function of ambient temperature with Vin = 27 V, airflow rate of 200 LFM (1 m/s) are shown for both a vertically
and horizontally mounted converter in Figs. 13 and 15, respectively.
Output voltage waveforms, during the turn-on transient using the ON/OFF pin for full rated load currents (resistive load) are
shown without and with 10,000 F load capacitance in Figs. 16 and 17, respectively.
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Q24S30033
9
35
35
30
30
Load Current [Adc]
Load Current [Adc]
Figure 20 shows the output voltage ripple waveform, measured at full rated load current with a 10 µF tantalum and 1 µF
ceramic capacitor across the output. Note that all output voltage waveforms are measured across a 1 F ceramic capacitor.
The input reflected ripple current waveforms are obtained using the test setup shown in Fig 21. The corresponding
waveforms are shown in Figs. 22 and 23.
25
20
15
500 LFM (2.5 m/s)
400 LFM (2.0 m/s)
300 LFM (1.5 m/s)
200 LFM (1.0 m/s)
100 LFM (0.5 m/s)
30 LFM (0.15 m/s)
10
5
25
20
15
500 LFM (2.5 m/s)
400 LFM (2.0 m/s)
300 LFM (1.5 m/s)
200 LFM (1.0 m/s)
100 LFM (0.5 m/s)
30 LFM (0.15 m/s)
10
5
0
0
20
30
40
50
60
70
80
20
90
30
Ambient Temperature [°C]
30
30
Load Current [Adc]
Load Current [Adc]
35
25
20
500 LFM (2.5 m/s)
400 LFM (2.0 m/s)
300 LFM (1.5 m/s)
200 LFM (1.0 m/s)
100 LFM (0.5 m/s)
30 LFM (0.15 m/s)
5
60
70
80
90
Figure 9. Available load current vs. ambient air temperature
and airflow rates for converter mounted vertically with Vin = 27
V, air flowing from pin 3 to pin 1 and maximum FET
temperature
C.
35
10
50
Ambient Temperature [°C]
Figure 8. Available load current vs. ambient air temperature
and airflow rates for converter mounted vertically with Vin = 27
V, air flowing from pin 3 to pin 1 and maximum FET
C.
15
40
25
20
15
500 LFM (2.5 m/s)
400 LFM (2.0 m/s)
300 LFM (1.5 m/s)
200 LFM (1.0 m/s)
100 LFM (0.5 m/s)
30 LFM (0.15 m/s)
10
5
0
0
20
30
40
50
60
70
80
20
90
30
40
50
60
70
80
90
Ambient Temperature [°C]
Ambient Temperature [°C]
Figure 10. Available load current vs. ambient temperature and
airflow rates for converter mounted horizontally with Vin = 27
V, air flowing from pin 3 to pin 4 and maximum FET
temperature 1 C.
Figure 11. Available load current vs. ambient temperature and
airflow rates for converter mounted horizontally with Vin = 27
V, air flowing from pin 3 to pin 4 and maximum FET
temperature
C.
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Q24S30033
0.95
0.95
0.90
0.90
0.85
0.85
Efficiency
Efficiency
10
0.80
36 V
27 V
18 V
0.75
0.80
0.75
0.70
70 C
55 C
40 C
0.70
0.65
0.65
0
5
10
15
20
25
30
35
0
5
10
Load Current [Adc]
15
20
25
30
35
Load Current [Adc]
Figure 12. Efficiency vs. load current and input voltage for
converter mounted vertically with air flowing from pin 3 to pin 1
at a r
C
Figure 13. Efficiency vs. load current and ambient temperature
for convert-er mounted vertically with Vin = 27 V and air
flowing from pin 3 to pin 1 at a rate of 200 LFM (1.0 m/s).
0.95
0.95
0.90
0.90
0.85
Efficiency
Efficiency
0.85
0.80
0.80
0.75
36 V
27 V
18 V
0.75
70 C
55 C
40 C
0.70
0.70
0.65
0.65
0
0
5
10
15
20
25
30
5
10
15
20
25
30
35
35
Load Current [Adc]
Figure 14. Efficiency vs. load current and input voltage for
converter mounted horizontally with air flowing from pin 3 to
pin 4 at a rate of 300 LFM (1.5 m/s) and
C.
Figure 16. Turn-on transient at full rated load current (resistive)
with no out-put capacitor at Vin = 24 V, triggered via ON/OFF
pin. Top trace: ON/OFF signal (5 V/div.). Bottom trace: output
voltage (1 V/div.) Time scale: 1 ms/div.
Load Current [Adc]
Figure 15. Efficiency vs. load current and ambient temperature
for convert-er mounted horizontally with Vin = 27 V and air
flowing from pin 3 to pin 4 at a rate of 200 LFM (1.0 m/s).
Figure 17. Turn-on transient at full rated load current (resistive)
µF F at Vin = 24 V, triggered via ON/OFF pin. Top
trace: ON/OFF signal (5 V/div.). Bottom trace: output voltage
(1 V/div.). Time scale: 1 ms/div.
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11
Figure 18. Output voltage response to load current stepchange (7.5 A – 15 A – 7.5 A) at Vin = 24 V. Top trace: output
voltage (100 mV/div). Bottom trace: load current (5 A/div.).
µ
µF ceramic. Time scale:
0.2 ms/div..
Figure 19. Output voltage response to load current stepchange (7.5 A – 15 A – 7.5 A) at Vin = 24 V. Top trace: output
voltage (100 mV/div.). Bottom trace: load current (5 A/div).
ceramic. Time scale: 0.2 ms/d
iS
10 H
source
inductance
Vsource
Figure 20. Output voltage ripple (20 mV/div.) at full rated load
µF tantalum + 1µF
µs/div.
Figure 22. Input reflected ripple current, ic (100 mA/div),
measured at input terminals at full rated load current and Vin =
24 V. Refer to Fig. 21
µs/div.
iC
33 F
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