QD48T033050-NBB0

LI FE The QD48T033050 dual output through-hole mounted DC-DC converter offers unprecedented performance in a quarter brick package by providing two independently regulated high current outputs with total power of 100 W. This is accomplished by the use of patent pending circuit and packaging techniques to achieve ultra-high efficiency, excellent thermal performance and a very low body profile. In telecommunications applications the QD48 converters provide up to 15 A @ 3.3 V and 10 A @ 5 V simultaneously – with thermal performance far exceeding existing dual quarter bricks and comparable to dual half-bricks. Low body profile and the preclusion of heatsinks minimize airflow shadowing, thus enhancing cooling for downstream devices. The use of 100% surface-mount technologies for assembly, coupled with Power Bel Solutions advanced electric and thermal circuitry and packaging, results in a product with extremely high quality and reliability. F  EN D O  RoHS lead-free solder and lead-solder-exempted products are available Delivers simultaneously up to 15 A on 3.3 VDC and up to 10 A on 5.0 VDC output Can replace two single output quarter-bricks Minimal cross-channel interference High efficiency: 88% @ full load, 89% @ half load Starts-up into pre-biased output No minimum load required No heat sink required Low profile: 0.28” [7.2 mm] Low weight: 1 oz [28 g] typical Industry-standard footprint: 1.45” x 2.30” Industry-standard pinout Meets Basic Insulation Requirements of EN60950 Withstands 100 V input transient for 100ms On-board LC input filter Fixed-frequency operation Fully protected Output voltage trim range: ±10% for both outputs Trim resistor via industry-standard equations High reliability: MTBF 2.6 million hours, calculated per Telcordia TR332, Method I Case 1 Positive or negative logic ON/OFF option Approved to the latest edition and amendment of ITE Safety standards, UL/CSA 60950-1 and IEC60950-1 Meets conducted emissions requirements of FCC Class B and EN55022 Class B with external filter All materials meet UL94, V-0 flammability rating                        QD48T033050 2 Conditions: TA = 25ºC, Airflow = 300 LFM (1.5 m/s), Vin = 48 VDC, unless otherwise specified. PARAMETER Absolute Maximum Ratings CONDITIONS / DESCRIPTION Input Voltage Continuous MIN TYP MAX UNITS 0 80 VDC Operating Ambient Temperature -40 85 °C Storage Temperature -55 125 °C 75 VDC Input Characteristics Operating Input Voltage Range 36 Non-latching Turn-on Threshold Turn-off Threshold Input Transient Withstand (Susceptibility) 100 ms Isolation Characteristics I/O Isolation Non-latching Non-latching F Peak Short-Circuit Current 3.3 V 5.0 V RMS Short-Circuit Current 3.3 V 5.0 V At nominal output voltage 3.3 V At nominal output voltage 5.0 V 34 31 32 17 11.5 35 VDC 33 VDC 100 VDC 10,000 4.700 μF μF 15 10 ADC ADC 18.5 13 20 15 ADC ADC 20 15 30 30 A A 4 4 Arms Arms 0 0 Non-latching. Short=10mΩ. Non-latching. Short=10mΩ. O Output Current Range 3.3 V 5.0 V Current Limit Inception 3.3 V 5.0 V Plus full load (resistive) Plus full load (resistive) 33 LI Output Characteristics External Load Capacitance 3.3 V 5.0 V 48 FE Input Under Voltage Lockout Non-latching Non-latching 2000 Isolation Capacitance VDC ρF 1.3 10 EN D Isolation Resistance MΩ Feature Characteristics Switching Frequency Output Voltage Trim Range1 3.3 V 5.0 V Output Over-Voltage Protection 3.3 V 5.0 V See section: Output Voltage Adjust/TRIM 435 Simultaneous with 3.3 V output -10 -10 Non-latching Non-latching 3.85 5.85 4.125 6.15 kHz +10 +10 % % 4.25 6.4 V V Over-Temperature Shutdown (PCB) Non-latching 120 °C Auto-Restart Period Applies to all protection features 100 ms 4 ms Turn-On Time 5.0 V 3.3 V tracks 5.0 V ON/OFF Control (Positive Logic) Converter Off -20 0.8 VDC Converter On 2.4 20 VDC ON/OFF Control (Negative Logic) Converter Off 2.4 20 VDC Converter On -20 0.8 VDC tech.support@psbel.com QD48T033050 3 Input Characteristics Maximum Input Current 3.3 VDC @ 15 ADC, 5.0 VDC @ 10 ADC, Vin = 36 V Input Stand-by Current Vin = 48 V, converter disabled 2.6 Input No Load Current (0 load on the output) Vin = 48 V, converter enabled 72 mAdc Input Reflected-Ripple Current See Figure 36 - 25MHz bandwidth 6 mAPK-PK Input Voltage Ripple Rejection 120Hz TBD dB 3.2 ADC mAdc Output Characteristics Output Voltage Set Point (no load) 3.3 V 5.0 V -40ºC to 85ºC -40ºC to 85ºC 3.267 4.950 3.333 5.050 VDC VDC FE Output Regulation 3.300 5.000 ±2 ±2 mV mV -10 -6 mV mV LI Over Line 3.3 V 5.0 V Over Load2 3.3 V 5.0 V Cross Regulation3 3.3 V 5.0 V Output Voltage Range 3.3 V 5.0 V For Iout2 (5.0 V) change from 0 to 10 A For Iout1 (3.3 V) change from 0 to 15 A Over line, load and cross regulation Over line, load and cross regulation Full load + 1 μF ceramic Full load + 1 μF ceramic F Output Ripple and Noise - 25MHz bandwidth 3.3 V 5.0 V Dynamic Response 3.234 4.9 20 25 mV mV 3.366 5.100 VDC VDC 30 35 mVPK-PK mVPK-PK ΔIout = 25% of IoutMax O Load Change: 50% to 75% to 50% di/dt = 0.1 A/μS 3.3 V 5.0 V -3 -5 Co = 10 μF tant. + 1 μF ceramic (Fig.23) Co = 10 μF tant. + 1 μF ceramic (Fig.24) 40 50 mV mV 100 20 µs µs 90 90 mV mV 60 60 µs µs 3.3 V 100% Load, 5.0V 100% Load 88 % 3.3 V 50% Load, 5.0V 50% Load 89 % Setting Time to 1% 3.3 V 5.0 V EN D di/dt = 5 A/μS Co = 300 μF tant. + 1 μF ceramic (Fig.25) Co = 300 μF tant. + 1 μF ceramic (Fig.26) 3.3 V 5.0 V Setting Time to 1% 3.3 V 5.0 V Efficiency 1) 2) 3) Vout1 and Vout2 can be simultaneously increased or decreased up to 10% via the Trim function. When trimming up, in order not to exceed the converter‘s maximum allowable output power capability equal to the product of the nominal output voltage and the allowable output current for the given conditions, the designer must, if necessary, decrease the maximum current (originally obtained from the derating curves) by the same percentage to ensure the converter’s actual output power remains at or below the maximum allowable output power. Load regulation is affected with resistance of the output pins (approximately 0.3 mΩ) since there is no remote sense. Cross regulation is affected with resistance of the RETURN pin (approximately 0.3 mΩ) since there is no remote sense. Europe, Middle East +353 61 225 977 North America +1 408 785 5200 © 2016 Bel Power Solutions & Protection BCD.00790_AB Asia-Pacific +86 755 298 85888 QD48T033050 4 FE These power converters have been designed to be stable with no external capacitors when used in low inductance input and output circuits. However, in many applications, the inductance associated with the distribution from the power source to the input of the converter can affect the stability of the converter. The addition of a 33 µF electrolytic capacitor with an ESR < 1  across the input helps ensure stability of the converter. In many applications, the user has to use decoupling capacitance at the load. The converter will exhibit stable operation with external load capacitance up to 10,000 µF on 3.3 V and 4,700uF on 5 V output. The ON/OFF pin is used to turn the power converter on or off remotely via a system signal. There are two remote control options available, positive logic and negative logic and both are referenced to Vin(-). Typical connections are shown in Fig. 1. Q TM Vin (+) Family Converter ON/OFF Vin Rload2 LI (Top View) Vout2 (+) TRIM RTN Rload1 Vin (-) Vout1 (+) F CONTROL INPUT Figure 1. Circuit configuration for ON/OFF function. EN D O The positive logic version turns on when the ON/OFF pin is at logic high and turns off when at logic low. The converter is on when the ON/OFF pin is left open. The negative logic version turns on when the pin is at logic low and turns off when the pin is at logic high. The ON/OFF pin can be hard wired directly to Vin(-) to enable automatic power up of the converter without the need of an external control signal. ON/OFF pin is internally pulled-up to 5 V through a resistor. A mechanical switch, open collector transistor, or FET can be used to drive the input of the ON/OFF pin. The device must be capable of sinking up to 0.2 mA at a low level voltage of  0.8 V. An external voltage source of ±20 V max. may be connected directly to the ON/OFF input, in which case it should be capable of sourcing or sinking up to 1 mA depending on the signal polarity. See the Start-up Information section for system timing waveforms associated with use of the ON/OFF pin. The converter’s output voltages can be adjusted simultaneously up 10% or down 10% relative to the rated output voltages by the addition of an externally connected resistor. For output voltage 3.3 V, trim up to 10% is guaranteed only at Vin ≥ 40 V, and it is marginal (8% to 10%) at Vin = 36 V. The TRIM pin should be left open if trimming is not being used. To minimize noise pickup, a 0.1 µF capacitor is connected internally between the TRIM and RETURN pins. Vin Q Family Converter Vout2 (+) (Top View) TRIM TM Vin (+) R T-INCR Rload2 ON/OFF RTN Rload1 Vin (-) Vout1 (+) Figure 2. Configuration for increasing output voltage. tech.support@psbel.com QD48T033050 5 To increase the output voltage (refer to Fig. 2), a trim resistor, RT-INCR, should be connected between the TRIM (Pin 6) and RETURN (Pin 5), with a value from the table below. Q Family Converter Vout2 (+) (Top View) TRIM TM Vin (+) R T-DECR Rload2 ON/OFF Vin RTN Rload1 Vin (-) FE Vout1 (+) Figure 3. Configuration for decreasing output voltage. Δ = percentage of increase or decrease Vout(NOM). TRIM RESISTOR (VOUT INCREASE) Δ [%] RT-INCR [kΩ] 1 54.9 F Note 1: Both outputs are trimmed up or down simultaneously. LI To decrease the output voltage, a trim resistor RT-DECR, (Fig. 3) should be connected between the TRIM (Pin 6) and Vout1(+) pin (Pin 4), with a value from the table below, where: TRIM RESISTOR (VOUT DECREASE) Δ [%] RT-DECR [kΩ] 68.1 -2 30.1 14.3 -3 17.8 9.31 -4 11.5 6.34 -5 7.68 4.32 -6 5.36 7 2.80 -7 3.48 8 1.69 -8 2.10 9 0.825 -9 1.05 10 0 -10 0 3 4 5 EN D 6 O -1 24.9 2 Note 2: The above trim resistor values match those typically used in industry-standard dual quarter bricks. Europe, Middle East +353 61 225 977 North America +1 408 785 5200 © 2016 Bel Power Solutions & Protection BCD.00790_AB Asia-Pacific +86 755 298 85888 QD48T033050 6 FE Input under-voltage lockout is standard with this converter. The converter will shut down when the input voltage drops below a pre-determined voltage. The input voltage must be at least 35 V for the converter to turn on. Once the converter has been turned on, it will shut off when the input voltage drops below 31 V. This feature is beneficial in preventing deep discharging of batteries used in telecom applications. LI The converter is protected against overcurrent or short circuit conditions on both outputs. Upon sensing an over-current condition, the converter will switch to constant current operation and thereby begin to reduce output voltages. If, due to current limit, the output voltage Vout1 (3.3 V) drops, than Vout2 (5.0 V) will follow Vout1 with less than 1 V difference. Drop on Vout2 output due to current limit will not affect voltage on Vout1. For further load increase, if either Vout1 drops below 1 VDC or Vout2 drops below 2 VDC, the converter will shut down (Figs. 29 and 30). Once the converter has shut down, it will attempt to restart nominally every 100 ms with a 2% duty cycle (Figs. 31 and 32). The attempted restart will continue indefinitely until the overload or short circuit conditions are removed or the output voltage Vout1 rises above 1 VDC and Vout2 above 2 VDC. O F The converter will shut down if the output voltage across either Vout1(+) (Pin 4) or Vout2(+) (Pin 7) and RETURN (Pin 5) exceeds the threshold of the OVP circuitry. The OVP protection is separate for Vout1 and Vout2 with their own reference independent of the output voltage regulation loops. Once the converter has shut down, it will attempt to restart every 100 ms until the OVP condition is removed. The converter will shut down under an over temperature condition to protect itself from overheating caused by operation outside the thermal derating curves, or operation in abnormal conditions such as system fan failure. After the converter has cooled to a safe operating temperature, it will automatically restart. EN D The converters meet North American and International safety regulatory requirements per UL60950 and EN60950. Basic Insulation is provided between input and output. To comply with safety agencies requirements, an input line fuse must be used external to the converter. A 5-A fuse is recommended for use with this product. EMC requirements must be met at the end-product system level, as no specific standards dedicated to EMC characteristics of board mounted component dc-dc converters exist. However, Power Bel Solutions tests its converters to several system level standards, primary of which is the more stringent EN55022, Information technology equipment - Radio disturbance characteristics - Limits and methods of measurement. With the addition of a simple external filter (see application notes), all versions of the QD48T converters pass the requirements of Class B conducted emissions per EN55022 and FCC, and meet at a minimum, Class A radiated emissions per EN 55022 and Class B per FCC Title 47CFR, Part 15-J. Please contact Power Bel Solutions Applications Engineering for details of this testing. tech.support@psbel.com QD48T033050 7 VIN Scenario #1: Initial Startup From Bulk Supply ON/OFF function enabled, converter started via application of VIN. See Figure 4. t1 t2 t3 Comments ON/OFF pin is ON; system front-end power is toggled on, VIN to converter begins to rise. VIN crosses Under-Voltage Lockout protection circuit threshold; converter enabled. Converter begins to respond to turn-on command (converter turn-on delay). Output voltage VOUT1 reaches 100% of nominal value ON/OFF STATE OFF ON VOUT2 VOUT2 VOUT1 Output voltage VOUT2 reaches 100% of nominal value. For this example, the total converter startup time (t4- t1) is typically 4 ms. FE Time t0 VOUT1 t4 t0 t1 t2 t3 t t4 Comments VINPUT at nominal value. Arbitrary time when ON/OFF pin is enabled (converter enabled). t2 End of converter turn-on delay. t3 Output voltage VOUT1 reaches 100% of nominal value. t4 Output voltage VOUT2 reaches 100% of nominal value. For this example, the total converter startup time (t4- t1) is typically 4 ms. VIN ON/OFF STATE OFF O F Time t0 t1 LI Figure 4. Start-up scenario #1. Scenario #2: Initial Startup Using ON/OFF Pin With VIN previously powered, converter started via ON/OFF pin. See Figure 5. EN D Scenario #3: Turn-off and Restart Using ON/OFF Pin With VIN previously powered, converter is disabled and then enabled via ON/OFF pin. See Figure 6. ON VOUT2 VOUT2 VOUT1 VOUT1 t0 t1 t2 t3 t t4 Figure 5. Startup scenario #2. VIN Time t0 t1 Comments VIN and VOUT are at nominal values; ON/OFF pin ON. ON/OFF pin arbitrarily disabled; converter output falls to zero; turn-on inhibit delay period (100 ms typical) is initiated, and ON/OFF pin action is internally inhibited. t2 ON/OFF pin is externally re-enabled. If (t2- t1) ≤ 100 ms, external action of ON/OFF pin is locked out by startup inhibit timer. If (t2- t1) > 100 ms, ON/OFF pin action is internally enabled. t3 Turn-on inhibit delay period ends. If ON/OFF pin is ON, converter begins turn-on; if off, converter awaits ON/OFF pin ON signal; see Figure 5. t4 End of converter turn-on delay. t5 Output voltage VOUT1 reaches 100% of nominal value. t6 Output voltage VOUT2 reaches 100% of nominal value. For the condition, (t2- t1) ≤ 100 ms, the total converter startup time (t6- t2) is typically 104 ms. For (t2- t1) > 100 ms, startup will be typically 4 ms after release of ON/OFF pin. 100 ms ON/OFF STATE OFF ON VOUT2 VOUT2 VOUT1 VOUT1 t0 t1 t2 t3 t4 t5 t6 t Figure 6. Startup scenario #3. Europe, Middle East +353 61 225 977 North America +1 408 785 5200 © 2016 Bel Power Solutions & Protection BCD.00790_AB Asia-Pacific +86 755 298 85888 QD48T033050 8 FE The converter has been characterized for many operational aspects, to include thermal derating (maximum load current as a function of ambient temperature and airflow) for vertical and horizontal mounting, efficiency, start-up and shutdown parameters, output ripple and noise, transient response to load step-change, overload and short circuit. The following pages contain specific plots or waveforms associated with the converter. Additional comments for specific data are provided below. F LI All data presented were taken with the converter soldered to a test board, specifically a 0.060” thick printed wiring board (PWB) with four layers. The top and bottom layers were not metalized. The two inner layers, comprising two-ounce copper, were used to provide traces for connectivity to the converter. The lack of metalization on the outer layers as well as the limited thermal connection ensured that heat transfer from the converter to the PWB was minimized. This provides a worst-case but consistent scenario for thermal derating purposes. All measurements requiring airflow were made in Power Bel Solutions vertical and horizontal wind tunnel facilities using infrared (IR) thermography and thermocouples for thermometry. Ensuring that the components on the converter do not exceed their ratings is important to maintaining high reliability. If one anticipates operating the converter at or close to the maximum loads specified in the derating curves, it is prudent to check actual operating temperatures in the application. Thermographic imaging is preferable; if this capability is not available, then thermocouples may be used. Power Bel Solutions recommends the use of AWG #40 gauge thermocouples to ensure measurement accuracy. Careful routing of the thermocouple leads will further minimize measurement error. Refer to Figure 37 for optimum measuring thermocouple location. The output current at which either any FET junction temperature did not exceed a maximum specified temperature (120°C) as indicated by the thermographic image, or (ii) The nominal rating of the converter (15 A on Vout1 and 10 A on Vout2.) During normal operation, derating curves with maximum FET temperature less than or equal to 120°C should not be exceeded. Temperature on the PCB at the thermocouple location shown in Fig. 37 should not exceed 118°C in order to operate inside the derating curves. EN D (i) O Available output power and load current vs. ambient temperature and airflow rates are given in Figs. 7-14. Ambient temperature was varied between 25°C and 85°C, with airflow rates from 30 to 500 LFM (0.15 to 2.5 m/s), and vertical and horizontal converter mounting. For each set of conditions, the maximum load current was defined as the lowest of: Efficiency vs. load current plots are shown in Figs. 15-20 for ambient temperature of 25ºC, airflow rate of 300 LFM (1.5 m/s), both vertical and horizontal orientations, and input voltages of 36 V, 48 V and 72 V, for different combinations of the loads on outputs Vout1 and Vout2. Output voltage waveforms during the turn-on transient using the ON/OFF pin, are shown without and with full rated load currents (resistive load) in Figs. 21 and 22, respectively. tech.support@psbel.com QD48T033050 9 110 100 100 90 90 80 70 60 50 500 LFM (2.5 m/s) 400 LFM (2.0 m/s) 300 LFM (1.5 m/s) 200 LFM (1.0 m/s) 100 LFM (0.5 m/s) 30 LFM (0.15 m/s) 30 20 60 50 500 LFM (2.5 m/s) 400 LFM (2.0 m/s) 300 LFM (1.5 m/s) 200 LFM (1.0 m/s) 100 LFM (0.5 m/s) 30 LFM (0.15 m/s) 40 30 20 10 10 0 0 20 30 40 50 60 70 80 90 20 30 40 50 60 70 80 90 Ambient Temperature [°C] Ambient Temperature [°C] Figure 8. Available output power for balanced load current (Iout1 = 1.5·Iout2) vs. ambient air temperature and airflow rates for converter mounted horizontally with Vin = 48 V, air flowing from pin 3 to pin 4 and maximum FET temperature  120 C. F Figure 7. Available output power for balanced load current (Iout1 = 1.5·Iout2) vs. ambient air temperature and airflow rates for converter mounted vertically with Vin = 48 V, air flowing from pin 3 to pin 1 and maximum FET temperature  120 C. 120 120 100 90 80 70 60 500 LFM (2.5 m/s) 400 LFM (2.0 m/s) 300 LFM (1.5 m/s) 200 LFM (1.0 m/s) 100 LFM (0.5 m/s) 30 LFM (0.15 m/s) 50 40 30 O 110 EN D % of Max. Load Current Iout1, Iout2 70 LI 40 80 FE Total Output Power [W] 110 20 10 30 40 50 60 70 110 100 90 80 70 60 500 LFM (2.5 m/s) 400 LFM (2.0 m/s) 300 LFM (1.5 m/s) 200 LFM (1.0 m/s) 100 LFM (0.5 m/s) 30 LFM (0.15 m/s) 50 40 30 20 10 0 0 20 % of Max. Load Current Iout1, Iout2 Total Output Power [W] Figure 33 shows the output voltage ripple waveform, measured at full rated load current on both outputs with a 1 µF ceramic capacitor across both outputs. Note that all output voltage waveforms are measured across a 1 F ceramic capacitor. The input reflected ripple current waveforms are obtained using the test setup shown in Fig. 34. The corresponding waveforms are shown in Figs. 35 and 36. 80 90 20 30 40 50 60 70 80 90 Ambient Temperature [°C] Ambient Temperature [°C] Figure 9. Available balanced load current (Iout1 = 1.5·Iout2) vs. ambient air temperature and airflow rates for converter mounted vertical-ly with Vin = 48 V, air flowing from pin 3 to pin 1 and maximum FET temperature  120 C. Figure 10. Available balanced load current (Iout1 = 1.5·Iout2) vs. ambient temperature and airflow rates for converter mounted horizontally with Vin = 48 V, air flowing from pin 3 to pin 4 and maximum FET temperature  120 C. Europe, Middle East +353 61 225 977 North America +1 408 785 5200 © 2016 Bel Power Solutions & Protection BCD.00790_AB Asia-Pacific +86 755 298 85888 QD48T033050 110 110 100 100 90 90 Total Output Power [W] 80 70 60 50 500 LFM (2.5 m/s) 400 LFM (2.0 m/s) 300 LFM (1.5 m/s) 200 LFM (1.0 m/s) 100 LFM (0.5 m/s) 30 LFM (0.15 m/s) 40 30 20 80 70 60 50 500 LFM (2.5 m/s) 400 LFM (2.0 m/s) 300 LFM (1.5 m/s) 200 LFM (1.0 m/s) 100 LFM (0.5 m/s) 30 LFM (0.15 m/s) 40 30 20 10 10 0 0 20 30 40 50 60 70 80 20 90 30 40 60 70 80 90 Figure 12. Available output power for balanced load current (Iout1 = 1.5·Iout2) vs. ambient air temperature and airflow rates for converter mounted vertically with Vin = 48 V, air flowing from pin 4 to pin 3 and maximum FET temperature  120 C. LI Figure 11. Available output power for balanced load current (Iout1 = 1.5·Iout2) vs. ambient air temperature and airflow rates for converter mounted vertically with Vin = 48 V, air flowing from pin 3 to pin 4 and maximum FET temperature  120 C. 110 100 90 80 70 40 30 20 O 500 LFM (2.5 m/s) 400 LFM (2.0 m/s) 300 LFM (1.5 m/s) 200 LFM (1.0 m/s) 100 LFM (0.5 m/s) 30 LFM (0.15 m/s) 50 10 0 20 30 110 100 90 80 70 60 F 60 % of Max. Load Current Iout1, Iout2 120 120 40 50 60 70 80 500 LFM (2.5 m/s) 400 LFM (2.0 m/s) 300 LFM (1.5 m/s) 200 LFM (1.0 m/s) 100 LFM (0.5 m/s) 30 LFM (0.15 m/s) 50 40 30 20 10 0 90 20 30 40 Ambient Temperature [°C] EN D Figure 13. Available balanced load current (Iout1 = 1.5·Iout2) vs. ambient air temperature and airflow rates for converter mounted vertical-ly with Vin = 48 V, air flowing from pin 3 to pin 4 and maximum FET temperature  120 C. 0.95 0.90 0.90 0.85 0.85 72 V 48 V 36 V 0.75 60 70 72 V 48 V 36 V 0.70 Iout2 = 5 Adc Iout2 = 5 Adc 0.65 2 4 6 8 10 90 0.80 0.75 0.70 0 80 Figure 14. Available balanced load current (Iout1 = 1.5·Iout2) vs. ambient air temperature and airflow rates for converter mounted vertical-ly with Vin = 48 V, air flowing from pin 4 to pin 3 and maximum FET temperature  120 C. 0.95 0.80 50 Ambient Temperature [°C] Efficiency Efficiency 50 Ambient Temperature [°C] Ambient Temperature [°C] % of Max. Load Current Iout1, Iout2 FE Total Output Power [W] 10 0.65 12 14 16 Load Current Iout1 [Adc] Figure 15. Efficiency vs. load current Iout1 and input voltage for converter mounted vertically with air flowing from pin 3 to pin 1 at a rate of 300 LFM (1.5 m/s), for Iout2 = 5 A and Ta = º 0 2 4 6 8 10 12 14 16 Load Current Iout1 [Adc] Figure 16. Efficiency vs. load current Iout1 and input voltage for converter mounted horizontally with air flowing from pin 3 to pin 4 at a rate of 300 LFM (1.5 m/s), for Iout2 = 5 A and ºC. tech.support@psbel.com 11 0.95 0.95 0.90 0.90 0.85 0.85 Efficiency 0.80 72 V 48 V 36 V 0.75 0.80 72 V 48 V 36 V 0.75 0.70 0.70 Iout1 = 7.5 Adc Iout1 = 7.5 Adc 0.65 0.65 0 1 2 3 4 5 6 7 8 9 10 0 11 1 2 3 4 5 6 7 8 9 10 11 Load Current Iout2 [Adc] Load Current Iout2 [Adc] 0.95 Figure 18. Efficiency vs. load current Iout2 and input voltage for converter mounted horizontally with air flowing from pin 3 to pin 4 at a rate of 300 LFM (1.5 m/s), for Iout1 = 7.5 A and ºC. LI Figure 17. Efficiency vs. load current Iout2 and input voltage for converter mounted vertically with air flowing from pin 3 to pin 1 at a rate of 300 LFM (1.5 m/s), for Iout1 = 7.5 A and ºC. 0.95 0.90 0.90 0.85 0.85 F Efficiency Efficiency FE Efficiency QD48T033050 0.80 72 V 48 V 36 V 0.70 0.65 0 2 4 6 8 10 12 14 72 V 48 V 36 V 0.75 O 0.75 0.80 16 0.70 0.65 0 Load Current Iout1 = 1.5·Iout2 [Adc] 2 4 6 8 10 12 14 16 Load Current Iout1 = Iout2 [Adc] Figure 20. Efficiency vs. balanced load current (Iout1/Iout2 = const.) and input voltage for converter mounted horizontally with air flowing from pin 3 to pin 4 at a rate of 300 LFM (1.5 Figure 21. Turn-on transient waveforms at no load current and Vin = 48 V, triggered via ON/OFF pin. Top trace: ON/OFF signal (5 V/div.). Bottom traces: Vout1 (blue, 1 V/div.), Vout2 (red, 1 V/div.). Time scale: 1 ms/div. Figure 22. Turn-on transient waveforms at full rated load current (resistive) and Vin = 48 V, triggered via ON/OFF pin. Top trace: ON/OFF signal (5 V/div.). Bottom traces: Vout1 (blue, 1 V/div.), Vout2 (red, 1 V/div.). Time scale: 1 ms/div. EN D Figure 19. Efficiency vs. balanced load current (Iout1 = 1.5·Iout2) and input voltage for converter mounted vertically with air flowing from pin 3 to pin 1 at a rate of 300 LFM (1.5 Europe, Middle East +353 61 225 977 North America +1 408 785 5200 © 2016 Bel Power Solutions & Protection BCD.00790_AB Asia-Pacific +86 755 298 85888 QD48T033050 FE 12 Figure 23. Output voltage response to Iout1 load current stepchange of 3.75 A (50%-75%-50%) at Iout2 = 5 A and Vin = 48 V. Ch1 = Vout1 (50 mV/div), Ch2 = Vout2 (50 mV/div), Ch3 = Iout1 (10 A/div.), Ch4 = Iout2 (10 A/div.). Current slew rate: 0.1 A/s, Co = 10 F tantalum + 1 F ceramic. Time scale: 0.5 ms/div. O F LI Figure 24. Output voltage response to Iout2 load current stepchange of 2.5 A (50%-75%-50%) at Iout1 = 7.5 A and Vin = 48 V. Ch1 = Vout1 (50 mV/div), Ch2 = Vout2 (50 mV/div), Ch3 = Iout1 (10 A/div.), Ch4 = Iout2 (10 A/div.). Current slew rate: 0.1 A/s, Co = 10 F tantalum + 1 F ceramic. Time scale: 0.5 ms/div. EN D Figure 25. Output voltage response to Iout1 load current stepchange of 3.75 A (50%-75%-50%) at Iout2 = 5 A and Vin = 48 V. Ch1 = Vout1 (100 mV/div), Ch2 = Vout2 (100 mV/div), Ch3 = Iout1 (10 A/div.), Ch4 = Iout2 (10 A/div.). Current slew rate: 5 A/s, Co = 300 F tantalum + 1 F ceramic. Time scale: 0.5 ms/div. Figure 27. Output voltage response to both Iout1 and Iout2 (out of phase) load current step-change of 3.75 A (Iout1) and 2.5 A (Iout2) (50%-75%-50%) at Vin = 48 V. Ch1 = Vout1 (50 mV/div), Ch2 = Vout2 (50 mV/div), Ch3 = Iout1 (10 A/div.), Ch4 = Iout2 (10 A/div.). Current slew rate: 0.1 A/s, Co = 10 F tantalum + 1 F ceramic. Time scale: 1 ms/div. Figure 26. Output voltage response to Iout2 load current stepchange of 2.5 A (50%-75%-50%) at Iout1 = 7.5 A and Vin = 48 V. Ch1 = Vout1 (100 mV/div), Ch2 = Vout2 (100 mV/div), Ch3 = Iout1 (10 A/div.), Ch4 = Iout2 (10 A/div.). Current slew rate: 5 A/s, Co = 300 F tantalum + 1 F ceramic. Time scale: 0.5 ms/div. Figure 28. Output voltage response to both Iout1 and Iout2 (out of phase) load current step-change of 3.75 A (Iout1) and 2.5 A (Iout2) (50%-75%-50%) at Vin = 48 V. Ch1 = Vout1 (100 mV/div), Ch2 = Vout2 (100 mV/div), Ch3 = Iout1 (10 A/div.), Ch4 = Iout2 (10 A/div.). Current slew rate: 5 A/s, Co = 300 F tantalum + 1 F ceramic. Time scale: 1 ms/div. Note: The only cross-talk during transient is due to the common RETURN pin for both outputs. tech.support@psbel.com QD48T033050 13 4.0 6.0 Vout1 Vout2 5.0 Vout [Vdc] Vout [Vdc] 3.0 2.0 4.0 3.0 2.0 1.0 1.0 0 0 5 10 15 0 20 5 10 FE 0 15 Iout [Adc] Iout [Adc] LI Figure 30. Output voltage Vout2 vs. load current Iout2 showing current limit point and converter shutdown point. When Vout2 is in current limit, Vout1 will follow with less than 1 V difference until Vout2 reaches shut-down threshold of 2 V. Input voltage has almost no effect on Vout2 current limit characteristic. O F Figure 29. Output voltage Vout1 vs. load current Iout1 showing current limit point and converter shutdown point. When Vout1 is in current limit, Vout2 is not affected until Vout1 reaches the shut-down threshold of 1 V. Input voltage has almost no effect on Vout1 current limit characteristic. EN D Figure 31. Load current Iout1 into a 10 mΩ short circuit on Vout1 during re-start, with Vout2 open (no load), at Vin = 48 V. Ch2 = Iout1 (20 A/div, 20 ms/div). ChB = Iout1 (20 A/div, 1 ms/div) is an expansion of the on-time portion of Iout1. Figure 32. Load current Iout2 into a 10 mΩ short circuit on Vout2 during re-start, with Vout1 open (no load), at Vin = 48 V. Ch2 = Iout2 (20 A/div, 20 ms/div). ChB = Iout2 (20 A/div, 1 ms/div) is an expansion of the on-time portion of Iout2. iS 10 H source inductance Vsource Figure 33. Output voltage ripple at full rated load current into a resistive load on both outputs with Co = 1uF (ceramic) and Vin = 48 V. Ch2 = Vout2, Ch1 = Vout1 (both 20 mV/div). Time iC 33 F ESR