The SRBP-80A2P0 is a 2-phase non-isolated step-down digital DC/DC
converter providing up to 80 A of output current.
All operating features can be configured through Power Management
bus. The output voltage range is from 0.6 VDC to 5.2 VDC over a wide
range of input voltage from 7.5 VDC to 14 VDC.
The module is provided in a quite small dimension SMD package of
(L x W x H): 1 x 0.5 x 0.48 [inch] / 25.4 x 12.7 x12.2 [mm].
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•
•
•
•
•
•
•
•
•
•
•
•
•
7.5 – 14 VDC Input / 0.6 - 5.2 VDC @ 80 A (single) or 40 A (dual) Output
Non-isolated Digital DC-DC Converter with Power Management bus
Two Phase Design, Dual or Single Output Configurable
High Efficiency
High Power Density
Output Over-Voltage Protection
Over Temperature Protection
Remote On/Off
Undervoltage Lockout
Over Current and Short Circuit Protection
2-Wire Remote Sense
Wide Trim
Parallelable Up To 8 Phase
Small Dimension SMD Package
Class II, Category 2, Non-Isolated DC/DC Converter (refer to IPC-9592B)
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Networking
Computers and Peripherals
Telecommunications
SRBP-80A2P0
2
MODEL
NUMBER
OUTPUT
VOLTAGE
INPUT
VOLTAGE
SRPB-80A2P0
0.6 – 5.2 V
7.5 - 14 V
MAX. OUTPUT
CURRENT
MAX. OUTPUT
POWER
80 A
TYPICAL EFFICIENCY
200 W
90% (11Vin,1.0V/80Aout)
NOTE: Add “G” suffix at the end of the model number to indicate Tray Packaging.
Add “R” suffix to indicate Tape & Reel package.
S
R
BP
Mounting Type
RoHS
Status
Series
Name
SMD
RoHS
POL
PARAMETER
-
80
A
2P
0
Output
Current
Input Range
Output Voltage
Active Logic
Package Type
Active High
G – Tray package
R – T&R package
80A
7.5 – 14 V
0.6 – 5.2 V
DESCRIPTION
x
MIN
TYP
Continuous non-operating Input Voltage
-0.3
Output Voltage
SHARE, EN1, EN2, PG1, PG2, ADDR,
SCL, SDA, SALERT, SYNC, CFG, ASCR,
Vtrim1, Vtrim2, Terminal Voltage
VS0+, VS0-, VS1+, VS1-,
0.6
Ambient Temperature
Storage Temperature
Altitude
MAX
UNITS
-
15
V
-
5.2
V
-0.3
-
5.5
V
-0.3
-
6.0
V
-40
-
85
C
-40
-
125
C
-
-
3000
m
NOTE: Ratings used beyond the maximum ratings may cause a reliability degradation of the converter or may permanently damage the device.
All specifications are typical at 25°C unless otherwise state
PARAMETER
DESCRIPTION
Operating Input Voltage
Vout=0.6 - 3.3 V
Vin = 7.5 V, Vout = 3.3 V Iout = 60 A,
Fsw = 457 kHz, Tamb = 55°C, 200 LFM
Enable off
MIN
TYP
MAX
UNITS
7.5
11
14
V
-
-
33
A
-
40
60
mA
-
160
-
µF
-
140
-
µF
-
6.8
-
V
-
6.1
-
V
Logic Input Low
-
-
0.8
V
Logic Input High
2.0
-
-
V
-
-
0.5
V
2.25
-
-
V
-100
-
+100
nA
Input Current
Input Current under Disable
Input Capacitance (Internal)
Input Capacitance
(Recommended External)
Turn on Voltage Threshold
16 x 10 µF/16 V Ceramic Cap
2x 47 µF / 25 V Polymer Cap and
4x 10 µF / 16 V Ceramic Cap
Turn off Voltage Threshold
Logic Output Low
2 mA Sinking
Logic Output High
2 mA Sourcing
Logic Input Leakage Current
CAUTION: All specifications are typical at nominal input, full load at 25°C unless noted.
tech.support@psbel.com
SRBP-80A2P0
3
All specifications are typical at nominal input, full load at 25°C unless otherwise stated.
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNITS
0.6
-
5
V
-1
-
1
%
-
2
0.2
5
-
mV
%
mV
-
0.5
0.6-1.0V in Dual Output Mode
5
-
mV
1.0-5.0V in Dual Output Mode
-
0.5
-
%
0.6-2.5V in 4-phase Mode
-
32
-
mV
3.3V in 4-phase Mode
-
24
-
mV
5.0V in 4-phase Mode
-
16
-
mV
0.6-2.5V in 6-phase Mode
-
48
-
mV
3.3V in 6-phase Mode
-
36
-
mV
5.0V in 6-phase Mode
-
24
-
mV
0.6-2.5V in 8-phase Mode
-
64
-
mV
3.3V in 8-phase Mode
-
48
-
mV
5.0V in 8-phase Mode
-
32
-
mV
-
10
-
mV
Vout =0.6V to 1.0V in Single Output Mode
Vout =0.6V to 1.0V in Dual Outputs Mode
Vout =1.8V in Single Output Mode
Vout =1.8V in Dual Outputs Mode
Vout =2.5V in Single Output Mode
Vout =2.5V in Dual Outputs Mode
Vout =3.3V in Single Output Mode
Vout =3.3V in Dual Outputs Mode
Vout =5V in Single Output Mode
Vout =5V in Dual Outputs Mode
Vout =0.6V to 1.0V in Single Output Mode
0
25
20
45
35
65
55
95
85
120
100
-
80
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
A
Vout =0.6V to 1.0V in Dual Outputs Mode
0
-
40
A
Vout =1.8V in Single Output Mode
0
-
70
A
Vout =1.8V in Dual Outputs Mode
0
-
35
A
Vout =2.5V in Single Output Mode
0
-
65
A
Vout =2.5V in Dual Outputs Mode
0
-
32.5
A
Vout =3.3V in Single Output Mode
0
-
60
A
Vout =3.3V in Dual Outputs Mode
0
-
30
A
Vout =5V in Single Output Mode
0
-
40
A
Vout =5V in Dual Outputs Mode
0
-
20
A
Ton Ramp/Toff Ramp Time
Default
-
5
-
ms
Ton Delay/Toff Delay
Default
-
5
-
ms
Ton Delay/Toff Delay Range
Set by Power Management bus
2
-
5000
ms
Power-good Delay
Default
-
1
-
ms
Power-good Delay Range
Set by Power Management bus
11Vin, 1Vout, 50% Load to 75% Load to 50%
Load, 1A/us with Minimum Cout
Minimum Cout 2*220uF/6.3V Polymer Cap and
3*100uF/6.3V Ceramic Cap
0
-
30
100
5000
-
ms
mV
µs
740
2320
4700
µF
Output Voltage
Output Voltage Set Point Accuracy
Line Regulation
Iout=50% Ioutmax, with +/-1% Rvtrim,
Measured at VSx+ and VSx0.6-1.0V
1.0-5.0V
0.6-1.0V in Single Output Mode
1.0-5.0V in Single Output Mode
Load Regulation
Regulation Over Temperature
(-40C - 85C)
Output Ripple and Noise with Minimum
Cout
Output Current Range
Transient Response
Output Capacitance per Phase
%
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SRBP-80A2P0
4
PARAMETER
DESCRIPTION
MIN
TYP
MA
X
UNITS
Full load 1 Vout
-
90
-
%
Full load 1.8 Vout
-
93
-
%
Full load 2.5 Vout
-
94.5
-
%
Full load 3.3 Vout
-
95
-
%
Full load 5 Vout
-
95.5
-
%
100
-
400
kHz
-
457
-
kHz
400
-
800
kHz
-
120
-
C
-
9.5
-
g
-
45,283,015
-
Hours
General Specifications
Efficiency
Power Management Bus Clock
Frequency
Switching Frequency
Configurable Switching
Frequency
Over Temperature Protection
RSYNC=23.7 kohm
Weight
MTBF
Vin=11 V, Vo=1 V, Io=80 A with 200 LFM, Ta=40°C
Dimensions (L × W × H)
1 x 0.5 x 0.48
inch
25.4 x 12.7 x12.2
mm
Control/Supervisory
Specifications
ENABLE
Signal Low
-0.3
-
0.8
V
2
-
5
V
ENABLE pin open, unit on default.
Signal High
Enable
The enable pins (EN1 and EN2) are used to enable and disable Vo1 and Vo2 separately. When working in Single Output Mode, use
only EN1 and ground EN2.
The Enable pins should be held LOW whenever a configuration file, or script is used to configure the module, or a Power Management
Bus command is sent to prevent potential damage to application circuit. When the module is used in a self-enabled mode, for
example, when EN1 or EN2 is tied to an external 5V, or to a resistor divider to VIN, the user must consider the module's default factory
settings. When a configuration file is used to configure the module, the factory default settings are restored to both the user and
default stores in order to set the module to an initialized state. Since the default state of the module is to be enabled when the enable
pin is high, it is possible for the module to be enabled while the Power Management bus commands are sent to the module during the
configuration process.
The Enable pin is edge triggered to achieve fast turn-off times. As a result, minimum Enable high and Enable low pulse widths must be
observed to ensure correct operation. The minimum high and low pulse widths are dependent on the configured rise, fall and delay
times and can be calculated:
EN low >TOFF_DELAY + TOFF_FALL + 10.5ms
EN high >TON_DELAY + TON_RISE + POWER_GOOD_DELAY + 5.5ms
EN low and EN high times shorter than these minimums may result in the module not responding to the trailing edge of the pulse. For
example, a EN low pulse below the EN low minimum pulse width may stay in the OFF state until a valid EN low pulse is applied to the
EN pin.
tech.support@psbel.com
SRBP-80A2P0
5
94.0%
EFFICIENCY
92.0%
90.0%
7.5V
88.0%
11 V
86.0%
14V
84.0%
82.0%
80.0%
4A
10A
20A
30A
40A
OUTPUT CURRENT (Vout1=Vout2=1.0V, Iout1=Iout2)
Figure 1. Efficiency data-1
96.0%
94.0%
EFFICIENCY
92.0%
90.0%
7.5V
88.0%
11 V
86.0%
14V
84.0%
82.0%
80.0%
3.5A
8.8A
17.5A
26.2A
35A
OUTPUT CURRENT (Vout1=Vout2=1.8V, Iout1=Iout2)
Figure 2. Efficiency data-2
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SRBP-80A2P0
EFFICIENCY
6
98.0%
96.0%
94.0%
92.0%
90.0%
88.0%
86.0%
84.0%
82.0%
80.0%
3.3A
7.5V
11 V
14V
8.1A
16.2A
24.4A
32.5A
OUTPUT CURRENT(Vout1=Vout2=2.5V, Iout1=Iout2)
EFFICIENCY
Figure 3. Efficiency data-3
98.0%
96.0%
94.0%
92.0%
90.0%
88.0%
86.0%
84.0%
82.0%
80.0%
7.5V
11 V
14V
3A
7.5A
15A
22.5A
30A
OUTPUT CURRENT(Vout1=Vout2=3.3V, Iout1=Iout2)
Figure 4. Efficiency data-4
tech.support@psbel.com
EFFICIENCY
SRBP-80A2P0
7
98.0%
96.0%
94.0%
92.0%
90.0%
88.0%
86.0%
84.0%
82.0%
80.0%
7.5V
11V
14V
2A
5A
10A
15A
20A
OUTPUT CURRENT(Vout1=Vout2=5.0V, Iout1=Iout2)
Figure 5. Efficiency data-5
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SRBP-80A2P0
8
TEST SETUP
Ls
is
ic
Vin+
+
Cs
+
Cin
VinFigure 6.
Notes and values in testing.
is: Simulated Source Impedance
ic: Input Terminal Ripple Current
Ls: Offset possible source Impedance (1μF)
Cin: Capacitors should be as closed as possible to the power module to damped ic ripple current and enhance stability.
Recommendation: 1*1000uF/16V Aluminum electrolytic, 16YXF1000+1*330uF/16V OS-CON, 16SVP330M+3*22uF/16V/1210
Below measured waveforms are based on above simulated and recommended inductance and capacitance.
Figure 7. is (input reflected ripple current), AC component
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SRBP-80A2P0
9
Figure 8. Test Condition: Vout1 = 1.0V/40A,
Figure 9. Test Condition: Vout1 = 1.8V/35A,
Vout2 = 1.8V/35A at Vin=11V@Ta=25°C
Vout2 = 1.0V/40A at Vin=11V@Ta=25°C
Figure 10.
Test Condition: Vout1 = 3.3V/30A；Vout2 = 3.3V/30A at Vin=11V@Ta=25°C
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SRBP-80A2P0
10
Figure 11.
Figure 12.
NOTE: Ripple and noise at full load,
Vin=11V, Vo=1.0V, 0-20MHz BW, with 3*100uF ceramic
and 2*220uF polymer capacitors at the output, Ta=25 C.
NOTE: Ripple and noise at full load,
Vin=11V, Vo=1.8V, 0-20MHz BW, with 3*100uF ceramic
and 2*220uF polymer capacitors at the output, Ta=25 C.
Figure 13.
Figure 14.
NOTE: Ripple and noise at full load,
Vin=11V, Vo=2.5V, 0-20MHz BW, with 3*100uF ceramic
and 2*220uF polymer capacitors at the output, Ta=25 C.
NOTE: Ripple and noise at full load,
Vin=11V, Vo=3.3V, 0-20MHz BW, with 3*100uF ceramic
and 2*220uF polymer capacitors at the output, Ta=25 C
tech.support@psbel.com
SRBP-80A2P0
Figure 15. Vin=11V, Vo=1.0V, Io=50%-75%Io max, di/dt=1A/us
11
Figure 16.Vin=11V, Vo=1.0V, Io=75%-50%Io max, di/dt=1A/us
NOTE：0-20MHz BW, with 3*100uF ceramic and 2*220uF polymer capacitors at the output, Ta=25 C.
Figure 17. Vin=11V, Vo=1.8V, Io=50%-75%Io max , di/dt=1A/us
Figure 18. Vin=11V, Vo=1.8V, Io=75%-50%Io max , di/dt=1A/us
NOTE：0-20MHz BW, with 3*100uF ceramic and 2*220uF polymer capacitors at the output, Ta=25 C
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SRBP-80A2P0
12
Figure 19. Vin=11V, Vo=2.5V, Io=50%-75%Io max , di/dt=1A/us
Figure 20. Vin=11V, Vo=2.5V, Io=75%-50%Iomax , di/dt=1A/us
NOTE：0-20MHz BW, with 3*100uF ceramic and 2*220uF polymer capacitors at the output, Ta=25 C.
Figure 21. Vin=11V, Vo=3.3V, Io=50%-75%Io max , di/dt=1A/us
Figure 22. Vin=11V, Vo=3.3V, Io=75%-50%Io max , di/dt=1A/us
NOTE：0-20MHz BW, with 3*100uF ceramic and 2*220uF polymer capacitors at the output, Ta=25 C.
Once the module has been disabled due to over temperature fault, the unit will auto recovery once temperature is below
OT_WARN_LIMIT +110°C.
The OTP limit, hysteresis and response are configured using the Power Management bus commands OT_FAULT_LIMIT,
OT_WARN_LIMIT and OT_FAULT_RESPONSE.
tech.support@psbel.com
SRBP-80A2P0
13
Hiccup: To provide protection in output overload condition, the module is equipped with internal current-limiting circuitry which
can endure current limiting for a few milliseconds. If the overcurrent condition persists beyond a few milliseconds, the module will
shut down then goes into hiccup mode and restart every 280 ms. The module operates normally when the output current goes
into specified range. The typical average output current is 4 A during hiccup.
Figure 23. Vout1,
Output current @ SCP, Vin = 11V, Vout = 1.0V, Ta=25 C
Figure 24. Vout2
Output current @ SCP, Vin = 11V, Vout = 1.0V, Ta=25 C
Figure 25. Vout1
Output current @ SCP，Vin = 11V, Vout = 1.8V, Ta=25 C
Figure 26. Vout2
Output current @ SCP，Vin = 11V, Vout = 1.8V, Ta=25 C
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SRBP-80A2P0
14
Figure 27. Vout1
Output current @ SCP，Vin = 11V, Vout = 2.5V, Ta=25 C
Figure 28. Vout2
Output current @ SCP，Vin = 11V, Vout = 2.5V, Ta=25 C
Figure 29. Vout1,
Output current @ SCP，Vin = 11V, Vout = 3.3V, Ta=25 C
Figure 30. Vout2,
Output current @ SCP，Vin = 11V, Vout = 3.3V, Ta=25 C
The input undervoltage lockout (UVLO) prevents the module from operating when the input falls below a preset threshold. The
default UVLO value is 6.7V. The input voltage undervoltage lock-out threshold can be set between 2.85V and 16V using the
VIN_UV_FAULT_LIMIT command.
The default response from an undervoltage fault is shut down and stay off until the fault has cleared, and the module has been
disabled and re-enabled.
When controlling the module exclusively through the Power Management bus, a high voltage setting for UVLO can be used to
prevent the module from being enabled until a lower voltage for UVLO is set using the VIN_UV_FAULT_LIMIT command.
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SRBP-80A2P0
15
Rise time
Figure 31. Test Condition: Vout1= 1.0V/40A；Vout2= 1.0V/40A at
Vin=11V@Ta=25C
Figure 32. Test Condition: Vout1= 1.0V/40A；Vout2= 1.0V/40A at
Vin=11V@Ta=25C Cext = 3300uF
Figure 33. Test Condition: Vout1= 1.8V/35A；Vout2= 1.8V/35A at
Vin=11V@Ta=25C
Figure 34.Test Condition: Vout1= 1.8V/35A；Vout2= 1.8V/35A at
Vin=11V@Ta=25C Cext = 3300uF
Figure 35. Test Condition: Vout1= 2.5V/32.5A；Vout2= 2.5V/32.5A at
Vin=11V@Ta=25C
Figure 36.Test Condition: Vout1= 12.5V/32.5A；Vout2= 2.5V/32.5A
at Vin=11V@Ta=25C Cext = 3300uF
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16
Figure 37. Test Condition: Vout1= 3.3V/30A；Vout2= 3.3V/30A at
Vin=11V@Ta=25C
Figure 38.Test Condition: Vout1= 3.3V/30A；Vout2= 3.3V/30A at
Vin=11V@Ta=25C Cext = 3300uF
Startup time
Figure 39. Startup from EN
Ch1: Vout1 ；Ch2：Vout2；Ch3: EN (EN1&EN2)
Test Condition: Vout1= 1.0V/40A；Vout2= 1.0V/40A at
Vin=11V@Ta=25C
Figure 40. Startup from EN
Ch1: Vout1 ；Ch2：Vout2；Ch3: EN (EN1&EN2)
Test Condition: Vout1= 1.0V/40A；Vout2= 1.0V/40A at
Vin=11V@Ta=25C Cext = 3300uF
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SRBP-80A2P0
17
Figure 41. Startup from EN
Ch1: Vout1 ；Ch2：Vout2; Ch3: EN (EN1&EN2)
Test Condition: Vout1= 1.8V/35A；Vout2= 1.8V/35A at
Vin=11V@Ta=25C
Figure 42. Startup from EN
Ch1: Vout1 ；Ch2：Vout2; Ch3: EN (EN1&EN2)
Test Condition: Vout1= 1.8V/35A；Vout2= 1.8V/35A at
Vin=11V@Ta=25C Cext = 3300uF
Figure 43. Startup from EN
Ch1: Vout1 ；Ch2：Vout2; Ch3: EN (EN1&EN2)
Test Condition: Vout1= 2.5V/32.5A；Vout2= 2.5V/32.5A
Vout2= 2.5V/32.5A at Vin=11V@Ta=25C
Figure 44.. Startup from EN
Ch1: Vout1 ；Ch2：Vout2; Ch3: EN (EN1&EN2)
Test Condition: Vout1= 2.5V/32.5A；
at Vin=11V@Ta=25C Cext = 3300uF
Figure 45. Startup from EN
Ch1: Vout1 ；Ch2：Vout2; Ch3: EN (EN1&EN2)
Test Condition: Vout1= 3.3V/30A；Vout2= 3.3V/30A at
Vin=11V@Ta=25C
Figure 46.Startup from EN
Ch1: Vout1 ；Ch2：Vout2; Ch3: EN (EN1&EN2)
Test Condition: Vout1= 3.3V/30A；Vout2= 3.3V/30A at
Vin=11V@Ta=25C Cext = 3300uF
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SRBP-80A2P0
18
Shutdown
Figure 47. Ch1: Vout1 ；Ch2：Vout2
Test Condition: Vout1= 1.0V/40A；Vout2= 1.0V/40A at
Vin=11V@Ta=25C
Figure 48.Ch1: Vout1 ；Ch2: Vout2
Test Condition: Vout1= 1.8V/35A；Vout2= 1.8V/35A at
Vin=11V@Ta=25C
Figure 49. Ch1: Vout1 ；Ch2：Vout2
Test Condition: Vout1= 2.5V/32.5A；Vout2= 2.5V/32.5A at
Vin=11V@Ta=25C
Figure 50.Ch1: Vout1 ；Ch2：Vout2
Test Condition: Vout1= 3.3V/30A；Vout2= 3.3V/30A at
Vin=11V@Ta=25C
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SRBP-80A2P0
19
The module provides power good (PG1, PG2) for each output that indicates the output voltage is within a specified tolerance of
its target level and no-fault condition exists. By default, the PG pin will assert if the output is within 10% of the target voltage.
These limits and the polarity of the pin may be changed using power management bus commands.
A PG delay period is defined as the time from when all conditions within the module for asserting PG are met to when the PG pin
is asserted. This feature is commonly used instead of using an external reset controller to control external digital logic. By default,
the module PG delay is set equal to 1ms. The PG delay may be set using a Power Management bus command as described in
“POWER_GOOD_DELAY (D4h)”.
Figure 51.
Ch1: Vout1 ；Ch2：Vout2；Ch3: PG (PG1&PG2)
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20
Block Diagram - In Single Output Mode
Vin
Cin
GND
Vin
GND
Vin
Vout2
GND
Vout2
PG1
PG2
GND
En1
Vout1
En2
SYNC
Vout1
SHARE
VS2+
ADDR
VS2SCL
Vtrim2
SDA
VS1SALERT SGND ASCR CFG Vtrim1 VS1+
RSYNC RADDR
RASCR RCFG
Cout
Vout
GND
RTrim
Figure 52.
Block Diagram - In Dual Outputs Mode
Vin
Cin
GND
Vin
GND
Vin
Vout2
GND
Vout2
PG1
PG2
GND
En1
Vout1
En2
SYNC
Vout1
SHARE
VS2+
ADDR
VS2SCL
Vtrim2
SDA
VS1SALERT SGND ASCR CFG Vtrim1 VS1+
RSYNC RADDR
Vout2
Cout2
Cout1
GND
Vout1
RTrim2
RASCR RCFG RTrim1
Figure 53.
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SRBP-80A2P0
21
Block Diagram - 4 Phases in Single Output Mode
Vin
Cin
GND
Vin
GND
Vin
Vout2
GND
Vout2
PG1
PG2
GND
En1
Vout1
En2
SYNC
Vout1
SHARE
VS2+
ADDR
VS2SCL
Vtrim2
SDA
VS1SALERT SGND ASCR CFG Vtrim1 VS1+
RADDR
RASCR RCFG
Cout
Vout
GND
RTrim
Vin
GND
Cin
Vin
GND
Vin
Vout2
GND
Vout2
PG1
PG2
GND
En1
Vout1
En2
SYNC
Vout1
SHARE
VS2+
ADDR
VS2SCL
Vtrim2
SDA
VS1SALERT SGND ASCR CFG Vtrim1 VS1+
RSYNC RADDR
RASCR RCFG RTrim
Figure 54.
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22
The output voltage is adjustable from 0.6V to 5.0 V. The outputs can be adjusted with an external resistor placed between the
“Vtrim1 or Vtrim2” and “GND”. Vo1 and Vo2 can also be set by Power Management bus command. VOUT_MAX is also
determined by this pin-strap setting, and is 15% greater than the Vtrim0 and Vtrim1 voltage settings by default, however
VOUT_MAX can be changed via the Power Management bus.
Trim Resistor
RTrim (kΩ)
VOUT (V)
RTrim (kΩ)
VOUT (V)
LOW
1
38.3
1.3
OPEN
1.2
42.2
1.4
HIGH
0.9
46.4
1.5
10
0.6
51.1
1.6
11
0.65
56.2
1.7
12.1
0.7
61.9
1.8
13.3
0.75
68.1
1.9
14.7
0.8
75
2
16.2
0.85
82.5
2.1
17.8
0.9
90.9
2.2
19.6
0.95
100
2.3
21.5
1
110
2.5
23.7
1.05
121
2.8
26.1
1.1
133
3
28.7
1.15
147
3.3
31.6
1.2
162
4
34.8
1.25
178
5
The device’s Charge-Mode response can be optimized by adjusting the ASCR gain and residual settings, either by resister
between ASCR and GND, or by using the ASCR_CONFIG Power Management Bus command.
Charge Mode Setting Resistor (RASCR)
RASCR(kΩ)
Vo1 GAIN
Vo2 GAIN
RASCR(kΩ)
Vo1 GAIN
Vo2 GAIN
10
200
200
51.1
800
600
11
200
400
56.2
800
800
12.1
200
600
61.9
800
1000
13.3
200
800
68.1
1000
200
14.7
200
1000
75
1000
400
16.2
400
200
82.5
1000
600
17.8
400
400
90.9
1000
800
19.6
400
600
100
1000
1000
21.5
400
800
110
100
100
23.7
400
1000
121
300
300
26.1
600
200
133
500
500
28.7
600
400
147
700
700
31.6
600
600
162
900
900
34.8
600
800
178
1100
1100
38.3
600
1000
LOW
300
300
42.2
800
200
OPEN
500
500
46.4
800
400
HIGH
700
700
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The Configuration pin (CFG) sets several module configuration settings allowing the module to be used in applications without the
need for loading configuration files. When using the module in a 4-phase application, the master module address must be 1
higher than the slave address. This must be done in order for the 2 modules to be recognized as part of a current sharing group.
See Power Management bus command “DDC_CONFIG (D3h)” for details.
Configuration Setting Resistor (RCFG)
10
Vo1
AVERAGE OC
LIMIT (A)
25
Vo1
PEAK OC
LIMIT (A)
28
Vo2
AVERAGE OC
LIMIT (A)
25
Vo2
PEAK OC
LIMIT (A)
28
2 Outputs
11
35
40
35
40
2 Outputs
12.1
45
50
45
50
2 Outputs
13.3
55
60
55
60
2 Outputs
17.8
35
40
25
28
2 Outputs
19.6
45
50
25
28
2 Outputs
21.5
55
60
25
28
2 Outputs
23.7
45
50
35
40
2 Outputs
26.1
55
60
35
40
2 Outputs
28.7
55
60
45
50
2 Outputs
31.6
25
28
35
40
2 Outputs
34.8
25
28
45
50
2 Outputs
38.3
25
28
55
60
2 Outputs
42.2
35
40
45
50
2 Outputs
46.4
35
40
55
60
2 Outputs
51.1
45
50
55
60
2 Outputs
56.2
25
28
25
28
2-Phase
61.9
35
40
35
40
2-Phase
68.1
45
50
45
50
2-Phase
75
55
60
55
60
2-Phase
90.9
35
40
35
40
4-PH Master
100
35
40
35
40
4-PH Slave
110
45
50
45
50
4-PH Master
121
45
50
45
50
4-PH Slave
133
55
60
55
60
4-PH Master
147
55
60
55
60
4-PH Slave
162
65
70
65
70
4-PH Master
4-PH Slave
RCFG(kΩ)
MODE
178
65
70
65
70
LOW
20
22.5
20
22.5
2-Phase
OPEN
20
22.5
20
22.5
2 Output
HIGH
35
40
35
40
2 Output
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The module switching frequency can be set from 400kHz to 800kHz by connect a RSNYC to SGND or using the Power
Management bus command REQUENCY_SWITCH. Switching frequency of 457kHz is recommended.
The module can be driven by an external clock source connected to the SYNC pin. When using the internal oscillator, the SYNC
pin can be configured as a clock source. By default, the SYNC pin is configured as an input. The module will automatically check
for a clock signal on the SYNC pin each time ON/OFF is asserted. The module will then synchronize with the rising edge of the
external clock.
The incoming clock signal must be in the range of 400kHz to 800kHz and must be stable when the ON/OFF pin (ON/OFF0,
ON/OFF1) is asserted. When using an external clock, the frequencies are not limited to discrete values as when using the internal
clock. The external clock signal must not vary more than 10% from its initial value, and should have a minimum pulse width of
150ns. In the event of a loss of the external clock signal, the output voltage may show transient over shoot or undershoot. If loss
of synchronization occurs, the module will automatically switch to its internal oscillator and switch at its programmed frequency.
The SYNC pin can also be configured as an output. The module will run from its internal oscillator and will drive the SYNC
pin so other modules can be synchronized to it. The SYNC pin will not be checked for an incoming clock signal while in this
mode. The switching frequency can be set to any value between 400kHz to 800kHz using a Power Management bus command.
The available frequencies below 800kHz are defined by fSW = 16MHz/N, where 20 ≤ N ≤ 40.
If a value other than fSW = 16MHz/N is entered using a Power Management bus command, the internal circuitry will select the
switching frequency value using N as a whole number to achieve a value close to the entered value. For example, if 810kHz is
entered, the module will select 800kHz (N=20).
Resistor for switching frequency setting
RSYNC(kΩ)
FREQ(kHz)
RSYNC(kΩ)
FREQ(kHz)
OPEN
400
28.7
571
HIGH
485
31.6
615
21.5
432
34.8
727
23.7
457
38.3
800
26.1
533
By connecting the SHARE and SYNC pins of each module and configuring the modules as a current sharing rail, the modules will
share the current equally. Current sensing element tolerances should be taken into account, or adjusted for using the
IOUT_CAL_GAIN and IOUT_CAL_OFFSET commands when necessary. Up to 4 modules can be configured in a given current
sharing group.
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When communicating with multiple Power Management bus modules using the Power Management bus interface, each module
must have its own unique address so the host can distinguish between the module. The module address can be set by a resistor
from pin ADDR to SGND. When operating in 2-channel mode, care must be taken when using sequential Power Management bus
addresses. Since DDC(SHARE) addresses are automatically set using the Power Management bus address, it is possible for a
module with a Power Management bus address immediately after a 2-channel module to be automatically configured with the
same DDC address as one of the module channels, which could cause unintended operating modes. For this reason, do not use
the next higher Power Management bus address when using the module as a 2-channel module. See Power Management bus
command “DDC_CONFIG (D3h)” for details. The Power Management bus address cannot be changed with a Power Management
bus command.
Power Management Bus Address (RADDR)
LOW
POWER MANAGEMENT BUS
ADDRESS
40h
42.2
POWER MANAGEMENT BUS
ADDRESS
51h
OPEN
42h
46.4
52h
10
41h
51.1
53h
11
43h
56.2
54h
12.1
44h
61.9
55h
13.3
45h
68.1
56h
14.7
46h
75
57h
16.2
47h
82.5
58h
17.8
48h
90.9
59h
19.6
49h
100
5Ah
21.5
4Ah
110
5Bh
23.7
61h
121
5Ch
26.1
4Ch
133
5Dh
28.7
4Dh
147
5Eh
31.6
4Eh
162
5Fh
34.8
4Fh
178
60h
RADDR(kΩ)
RADDR (kΩ)
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26
CODE
COMMAND NAME
DESCRIPTION
TYPE
DATA
FORMAT
DEFAULT
VALUE
00h
PAGE
Selects Controller 0, 1, or both
R/W
BIT
00h
01h
OPERATION
Enable/disable, margin settings
R/W
BIT
00h
02h
ON_OFF_CONFIG
On/off configuration settings
R/W
BIT
17h
DEFAULT SETTING
03h
CLEAR_FAULTS
Clears faults
Write
N/A
N/A
Page 0 Controller
addressed
Immediate off, nominal
margin
ENABLE pin control,
active high
N/A
11h
STORE_DEFAULT_ALL
Stores values to default store
Write
N/A
N/A
N/A
12h
RESTORE_DEFAULT_ALL
Restores values from default store
Write
N/A
N/A
N/A
15h
STORE_USER_ALL
Stores values to user store
Write
N/A
N/A
N/A
16h
RESTORE_USER_ALL
Restores values from user store
Write
N/A
N/A
20h
VOUT_MODE
Reports VOUT mode and exponent
Read
BIT
13h
21h
VOUT_COMMAND
R/W
L16u
N/A
22h
VOUT_TRIM
R/W
L16s
0000h
0V
23h
VOUT_CAL_OFFSET
Sets nominal VOUT set-point
Applies offset voltage to VOUT setpoint
Applies offset voltage to VOUT setpoint
N/A
Linear mode,
exponent = -13
Pin-strap setting
R/W
L16s
0000h
24h
VOUT_MAX
25h
VOUT_MARGIN_HIGH
26h
VOUT_MARGIN_LOW
27h
VOUT_TRANSITION_RATE
28h
VOUT_DROOP
33h
FREQUENCY_SWITCH
37h
INTERLEAVE
38h
IOUT_CAL_GAIN
39h
IOUT_CAL_OFFSET
40h
VOUT_OV_FAULT_LIMIT
41h
VOUT_OV_FAULT_RESPONSE
44h
VOUT_UV_FAULT_LIMIT
45h
VOUT_UV_FAULT_RESPONSE
46h
IOUT_OC_FAULT_LIMIT
4Bh
IOUT_UC_FAULT_LIMIT
4Fh
OT_FAULT_LIMIT
50h
OT_FAULT_RESPONSE
51h
OT_WARN_LIMIT
52h
UT_WARN_LIMIT
53h
UT_FAULT_LIMIT
54h
UT_FAULT_RESPONSE
55h
VIN_OV_FAULT_LIMIT
Sets maximum VOUT set-point
Sets VOUT set-point during margin
high
Sets VOUT set-point during margin
low
Sets VOUT transition rate during
margin commands
Sets V/I slope for total rail output
current (all phases combined)
Sets switching frequency
Configures phase offset during group
operation
Sets impedance of current sense
circuit
Sets an offset to IOUT sense circuit
Sets the VOUT overvoltage fault
threshold
Sets the VOUT overvoltage fault
response
Sets the VOUT undervoltage fault
threshold
Sets the VOUT undervoltage fault
response
Sets the IOUT peak overcurrent fault
threshold for each phase
Sets the IOUT valley undercurrent
fault threshold for each phase
Sets the over-temperature fault limit
Sets the over-temperature fault
response
Sets the over-temperature warning
limit
Sets the under-temperature warning
limit
Sets the under-temperature fault limit
Sets the under-temperature fault
response
Sets the VIN overvoltage fault
threshold
0V
1.15 x VSET pin-strap
setting
1.05 x VSET pin-strap
setting
0.95 x VSET pin-strap
setting
R/W
L16u
N/A
R/W
L16u
N/A
R/W
L16u
N/A
R/W
L11
BA00h
1V/ms
R/W
L11
N/A
CFG pin-strap setting
R/W
L11
N/A
SYNC pin-strap
setting
R/W
BIT
N/A
CFG pin-strap setting
R/W
L11
B3CCh
0.95mV/A,
R/W
L11
BD00h
R/W
L16u
N/A
-1.5A
1.10 x VSET pin-strap
setting
R/W
BIT
80h
Disable, no retry
R/W
L16u
N/A
0.85 x VSET pin-strap
setting
R/W
BIT
80h
Disable, no retry
R/W
L11
N/A
CFG pin-strap setting
1*IOUT_OC_FAULT_LI
MIT from CFG pinstrap setting
+125°C
Continuous retry,
280ms retry delay
R/W
L11
N/A
R/W
L11
EBE8h
R/W
BIT
FFh
R/W
L11
EB70h
+110°C
R/W
L11
E580h
-40°C
R/W
L11
E440h
R/W
BIT
FFh
-60°C
Continuous retry,
280ms retry delay
R/W
L11
D3C0h
15V
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SRBP-80A2P0
27
78h
STATUS_BYTE
Sets the VIN overvoltage fault
response
Sets the VIN overvoltage warning
threshold
Sets the VIN undervoltage warning
threshold
Sets the VIN undervoltage fault
threshold
Sets the VIN undervoltage fault
response
Sets the voltage threshold for powergood indication
Sets the delay time from enable to
VOUT rise
Sets the rise time of VOUT after
ENABLE and TON_DELAY
Sets the delay time from DISABLE to
start of VOUT fall
Sets the fall time for VOUT after
DISABLE and TOFF_DELAY
First byte of STATUS_WORD
Read
BIT
00h
No faults
79h
STATUS_WORD
Summary of critical faults
Read
BIT
0000h
No faults
7Ah
STATUS_VOUT
Reports VOUT warnings/faults
Read
BIT
00h
No faults
7Bh
STATUS_IOUT
Reports IOUT warnings/faults
Read
BIT
00h
No faults
7Ch
STATUS_INPUT
Reports input warnings/faults
Read
BIT
00h
No faults
7Dh
STATUS_TEMP
Read
BIT
00h
No faults
7Eh
STATUS_CML
Read
BIT
00h
No faults
80h
STATUS_MFR_SPECIFIC
88h
READ_VIN
Reports temperature warnings/faults
Reports communication, memory,
logic errors
Reports voltage monitoring/clock
synchronization faults
Reports input voltage measurement
89h
READ_IIN
8Bh
56h
VIN_OV_FAULT_RESPONSE
57h
VIN_OV_WARN_LIMIT
58h
VIN_UV_WARN_LIMIT
59h
VIN_UV_FAULT_LIMIT
5Ah
VIN_UV_FAULT_RESPONSE
5Eh
POWER_GOOD_ON
60h
TON_DELAY
61h
TON_RISE
64h
TOFF_DELAY
65h
TOFF_FALL
R/W
BIT
80h
R/W
L11
D360h
Disable, no retry
13.5V
1.1 x UVLO pin-strap
setting
UVLO pin-strap
setting
Continuous retries,
280ms retry delay
0.9 x VSET pin-strap
setting
R/W
L11
N/A
R/W
L11
N/A
R/W
BIT
BFh
R/W
L16u
N/A
R/W
L11
CA80h
5ms
R/W
L11
CA80h
5ms
R/W
L11
CA80h
5ms
R/W
L11
CA80h
5ms
Read
BIT
00h
no faults
Read
L11
N/A
N/A
Reports input current measurement
Read
L11
N/A
N/A
READ_VOUT
Reports output voltage measurement
Read
L16u
N/A
N/A
8Ch
READ_IOUT
Read
L11
N/A
N/A
8Dh
READ_TEMPERATURE_1
Read
L11
N/A
N/A
8Eh
READ_TEMPERATURE_2
Read
L11
N/A
N/A
8Fh
READ_TEMPERATURE_3
Read
L11
N/A
N/A
94h
READ_DUTY_CYCLE
Reports output current measurement
Reports internal temperature
measurement
Reports external temperature
measurement from XTEMP pins
Reports external temperature
measurement from VMON/TMON pin.
Reports actual duty cycle
Read
L11
N/A
N/A
95h
Reports actual switching frequency
Reports the POWER MANAGEMENT
BUS revision used
Sets a user defined identification
Read
L11
N/A
N/A
Read
BIT
22h
P1 R1.2, P2 R1.2
99h
READ_FREQUENCY
POWER MANAGEMENT
BUS_REVISION
MFR_ID
R/W
ASC
N/A
9Ah
MFR_MODEL
Sets a user defined model
R/W
ASC
N/A
9Bh
MFR_REVISION
Sets a user defined revision
R/W
ASC
N/A
9Ch
MFR_LOCATION
Sets a user defined location identifier
R/W
ASC
N/A
9Dh
MFR_DATE
Sets a user defined date
R/W
ASC
N/A
9Eh
MFR_SERIAL
R/W
ASC
N/A
ADh
IC_DEVICE_ID
Read
CUS
49A02D00h
Intersil MODULE
AEh
IC_DEVICE_REV
Sets a user defined serialized identifier
Reports device identification
information
Reports device revision information
Read
CUS
01000000h
Initial Release
B0h
USER_DATA_00
Sets user defined data
R/W
ASC
N/A
CEh
MIN_VOUT_REG
Sets a minimum start-up voltage
R/W
L11
0000h
D0h
ISENSE_CONFIG
Configures current sensing circuitry
R/W
BIT
620Eh
D1h
USER_CONFIG
Configures several user-level features
R/W
BIT
N/A
0mV
Downslope, 5 fault
count, 384ns blanking,
high range
Set by CFG pin-strap
setting
IIN_CAL_GAIN
Sets the resistance of the input
current sensing resistor
R/W
L11
C200h
98h
D2h
2mfi
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28
D3h
DDC_CONFIG
D4h
POWER_GOOD_DELAY
D5h
MULTI_PHASE_RAMP_GAIN
D6h
INDUCTOR
D7h
SNAPSHOT_FAULT_MASK
D8h
OVUV_CONFIG
D9h
XTEMP_SCALE
DAh
XTEMP_OFFSET
DBh
MFR_SMBALERT_MASK
Configures the DDC addressing and
current sharing
Sets the delay between PG threshold
and PG assertion
Adjusts the ramp-up and ramp-down
rate by setting the feedback gain
Sets the inductor value
Masks faults that cause a snapshot to
be taken
Configures output voltage OV/UV fault
detection
R/W
BIT
N/A
Set by pin-strapped
Power Management
bus address and CFG
pin-strap setting
R/W
L11
BA00h
1ms
R/W
CUS
03h
3
R/W
L11
B133h
0.3μH
R/W
BIT
0000h
No faults masked
R/W
BIT
00h
Low side FET off on
fault, 1 violation
triggers fault.
R/W
L11
BA00h
1/degree C
R/W
L11
0000h
No offset
R/W
Custom
00..00h
N/A
DCh
TEMPCO_CONFIG
Calibrates external temperature
sensor
Offset calibration for external
temperature sensor
Identifies which fault limits will not
assert SALRT
Sets tempco settings
R/W
BIT
00h
0ppm/°C
DDh
PINSTRAP_READ_STATUS
Reads pin-strap settings
Read
BIT
N/A
DFh
ASCR_CONFIG
Configures the ASCR settings
R/W
BIT
N/A
E0h
SEQUENCE
DDC rail sequencing configuration
R/W
BIT
00h
E1h
TRACK_CONFIG
R/W
BIT
00h
E2h
DDC_GROUP
Configures voltage tracking.
Configures group ID, fault spreading,
OPERATION and VOUT
Set by pin-straps
ASCRCFG pin-strap
setting
Prequel and sequel
disabled
Tracking disabled
R/W
BIT
N/A
Set by CFG pin-strap
E4h
DEVICE_ID
Returns the device identifier string
Read
ASC
TBD
MFR_IOUT_OC_FAULT_RESPO
NSE
MFR_IOUT_UC_FAULT_RESPO
NSE
Configures the IOUT overcurrent fault
response
Configures the IOUT undercurrent
fault response
Sets the IOUT average overcurrent
fault threshold
R/W
BIT
BFh
R/W
BIT
BFh
R/W
L11
N/A
R/W
L11
N/A
R/W
BIT
N/A
Read
BIT
N/A
R/W
BIT
00000000h
R/W
BIT
00h
N/A
Write
N/A
N/A
N/A
E5h
E6h
E7h
IOUT_AVG_OC_FAULT_LIMIT
E8h
IOUT_AVG_UC_FAULT_LIMIT
E9h
USER_GLOBAL_CONFIG
EAh
SNAPSHOT
F0h
LEGACY_FAULT_GROUP
F3h
SNAPSHOT_CONTROL
F4h
RESTORE_FACTORY
Sets the IOUT average undercurrent
fault threshold
MODULE, current
revisions
Continuous retries,
280ms retry delay
Continuous retries,
280ms retry delay
Set by CFG pin-strap
-1*
IOUT_AVG_OC_FAUL
T_LIMIT
Set by CFG pin-strap
setting
FAh
SECURITY_LEVEL
Sets options pertaining to advanced
features
32-byte read-back of parametric and
status values
Configures fault group compatibility
with older Intersil digital power
devices
Snapshot feature control command
Restores device to the hard-coded
default values
Sets the VMON overvoltage fault
threshold
Sets the VMON undervoltage fault
threshold
Reads the VMON voltage
Configures the VMON overvoltage
fault response
Configures the VMON undervoltage
fault response
Reports the security level
Read
Hex
01h
Public security level
FBh
PRIVATE_PASSWORD
Sets the private password string
R/W
ASC
00…00h
FCh
PUBLIC_PASSWORD
R/W
ASC
00…00h
FDh
UNPROTECT
Sets the public password string
Identifies which commands are
protected
R/W
Custom
FF…FFh
No commands are
protected
F5h
MFR_VMON_OV_FAULT_LIMIT
F6h
MFR_VMON_UV_FAULT_LIMIT
F7h
MFR_READ_VMON
F8h
VMON_OV_FAULT_RESPONSE
F9h
VMON_UV_FAULT_RESPONSE
R/W
L11
C266h
2.4V, SPS OT trip
voltage
R/W
L11
A333h
0.2V
Read
L11
N/A
N/A
R/W
BIT
BFh
Continuous retry
R/W
BIT
BFh
Continuous retry
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The Power Management bus is a powerful tool that allows the user to optimize circuit performance by configuring the MODULE for
their application. When configuring the MODULE in a circuit, the MODULE should be disabled whenever most settings are changed
with Power Management bus commands. Some exceptions to this recommendation are OPERATION, ON_OFF_CONFIG,
CLEAR_FAULTS, VOUT_COMMAND, VOUT_MARGIN_HIGH, VOUT_MARGIN_LOW and ASCCR_CONFIG. While the device is
enabled any command can be read. Many commands do not take effect until after the device has been reenabled, hence the
recommendation that commands that change device settings are written while the device is disabled.
When sending the STORE_DEFAULT_ALL, STORE_USER_ALL, RESTORE_DEFAULT_ALL and RESTORE_USER_ALL commands,
it is recommended that no other commands are sent to the device for 100ms after sending STORE or RESTORE commands.
In addition, there should be a 2ms delay between repeated READ commands sent to the same device. When sending any other
command, a 5ms delay is recommended between repeated commands sent to the same device.
All commands can be read at any time.
Always disable the MODULE when writing commands that change device settings. Exceptions to this rule are commands intended
to be written while the device is enabled, for example, VOUT_MARGIN_HIGH.
To be sure a change to a device setting has taken effect, write the STORE_USER_ALL command, then cycle input power and
reenable the device.
Linear-11 (L11)
L11 data format uses 5-bit two’s compliment exponent (N) and 11-bit two’s compliment mantissa (Y) to represent real world
decimal value (X).
Data Byte High
Data Byte Low
7 6 5 4 3 2 1 0
Exponent (N)
7 6 5 4 3 2 1 0
Mantissa (Y)
Relation between real world decimal value (X), N and Y is: X = Y·2N
Linear-16 Unsigned (L16u)
L16u data format uses a fixed exponent (hard-coded to N = -13h) and a 16-bit unsigned integer mantissa (Y) to represent real
world decimal value (X). Relation between real world decimal value (X), N and Y is: X = Y·2 -13
Linear-16 Signed (L16s)
L16s data format uses a fixed exponent (hard-coded to N = -13h) and a 16-bit two’s compliment mantissa (Y) to represent real
world decimal value (X).
Relation between real world decimal value (X), N and Y is: X = Y·2-13
Bit Field (BIT)
Breakdown of Bit Field is provided in “Power Management bus Command Detail”.
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Custom (CUS)
Breakdown of Custom data format is provided in “Power Management bus Command Detail”. A combination of Bit Field and
integer are common type of Custom data format.
ASCII (ASC)
A variable length string of text characters uses ASCII data format
PAGE (00h)
Definition: Selects Controller 0, Controller 1 or both Controllers 0 and 1 to receive commands. All commands following this
command will be received and acted on by the selected controller or controllers.
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: No
Default Value: 00h (Page 0)
Units: N/A
COMMAND
PAGE (00h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Function
Default Value
See Following Table
0
0
BITS 7:4
BITS 3:0
PAGE
0
0
0
0
1
1
1111
1111
Both
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OPERATION (01h)
Definition: Sets Enable, Disable and VOUT Margin settings. This command can also be monitored to read the operating state of
the device on bits 7:6. Writing Immediate off will turn off the output and ignore TOFF_DELAY and TOFF_FALL settings. This
command is not stored like other Power Management bus commands. The value read reflects the current state of the device.
When this command is written the command takes effect, but if a STORE _USER_ALL written and the device is reenabled, the
OPERATION settings may not be the same settings that were written before the device was reenabled.
Paged or Global: Paged
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: 00h (immediate off)
Units: N/A
COMMAND
OPERATION (01h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Function
See Following Table
Default Value
0
0
BITS
7:6
BITS 5:4
BITS 3:0 (NOT USED)
UNIT ON OR OFF
MARGIN STATE
0
0
0
Immediate off (No sequencing)
N/A
1
0
0
Soft off (With sequencing)
N/A
10
0
0
On
Nominal
10
1
0
On
Margin Low
10
10
0
On
Margin High
NOTE: Bit combinations not listed above may cause command errors.
ON_OFF_CONFIG (02h)
Definition: Configures the interpretation and coordination of the OPERATION command and the ENABLE pin (EN). When bit 0 is
set to 1 (turn off the output immediately), the TOFF_FALL setting is ignored.
Paged or Global: Paged
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: 17h (ENABLE pin control, active high, turn off output immediately – no ramp down)
Units: N/A
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COMMAND
ON_OFF_CONFIG (02h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
Function
See Following Table
Default Value
0
0
0
1
0
BIT NUMBER
PURPOSE
BIT VALUE
MEANING
7:5
Not Used
000
Not used
000
Not used
4:2
Sets the default to either operate any time
power is present or for the on/off to be
controlled by ENABLE pin or OPERATION
command
101
Device starts from ENABLE pin only.
110
Device starts from OPERATION command only.
1
(Polarity of ENABLE pin - not used)
1
Active high only.
0
ENABLE pin action when commanding the
unit to turn off
0
Use the configured ramp-down settings (“soft-off”)
1
Turn off the output immediately.
CLEAR_FAULTS (03h)
Definition: Clears all fault bits in all registers and releases the SALRT pin (if asserted) simultaneously. If a fault condition still exists,
the bit will reassert immediately. This command will not restart a device if it has shut down, it will only clear the faults.
Paged or Global: Global
Data Length in Bytes: 0 Byte
Data Format: N/A
Type: Write only
Protectable: Yes
Default Value: N/A
Units: N/A
STORE_DEFAULT_ALL (11h)
Definition: Stores all current Power Management bus values from the operating memory into the nonvolatile DEFAULT Store
memory. To clear the DEFAULT store, perform a RESTORE_FACTORY then STORE_DEFAULT_ALL. To add to the DEFAULT
store, perform a RESTORE_DEFAULT_ALL, write commands to be added, then STORE_DEFAULT_ALL. This command should
not be used during device operation, the device will be unresponsive for 100ms while storing values.
Paged or Global: Global
Data Length in Bytes: 0
Data Format: N/A
Type: Write only
Default Value: N/A
Units: N/A
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RESTORE_DEFAULT_ALL (12h)
Definition: Restores Power Management bus settings from the nonvolatile DEFAULT store memory into the operating memory.
These settings are loaded during at power-up if not superseded by settings in USER store. Security level is changed to level 1
following this command. This command should not be used during device operation, the device will be unresponsive for 100ms
while storing values.
Paged or Global: Global
Data Length in Bytes: 0
Data Format: N/A
Type: Write only
Default Value: N/A
Units: N/A
STORE_USER_ALL (15h)
Definition: Stores all Power Management bus settings from the operating memory to the nonvolatile USER store memory. To clear
the USER store, perform a RESTORE_FACTORY then STORE_USER_ALL. To add to the USER store, perform a
RESTORE_USER_ALL, write commands to be added, then STORE_USER_ALL. This command should not be used during device
operation, the device will be unresponsive for 100ms while storing values.
Paged or Global: Global
Data Length in Bytes: 0
Data Format: N/A
Type: Write only
Default Value: N/A
Units: N/A
RESTORE_USER_ALL (16h)
Definition: Restores all Power Management bus settings from the USER store memory to the operating memory. Command
performed at power-up. Security level is changed to Level 1 following this command. This command should not be used during
device operation, the device will be unresponsive for 100ms while restoring values.
Paged or Global: Global
Data Length in Bytes: 0
Data Format: N/A
Type: Write only
Default Value: N/A
Units: N/A
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VOUT_MODE (20H)
Definition: Reports the VOUT mode and provides the exponent used in calculating several VOUT settings.
Data Length in Bytes: 1
Data Format: BIT
Type: Read Only
Default Value: 13h (Linear Mode, Exponent = -13)
Units: N/A
COMMAND
VOUT_MODE (20h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
Default Value
0
0
0
0
1
1
MODE
BITS 7:5
BITS 4:0 (PARAMETER)
000
5-bit two’s complement exponent for the mantissa delivered as the data bytes for an output
voltage related command.
Function
See Following Table
Linear
1
0
VOUT_COMMAND (21h)
Definition: This command sets or reports the target output voltage. The integer value is multiplied by 2 raised to the power of 13h. This command cannot be set to be higher than 115% of the pin-strap VSET setting, or VOUT_MAX if VOUT_MAX is set
higher than 115% of the pin-strap VSET setting.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear -16 Unsigned
Type: R/W
Protectable: Yes
Default Value: VSET pin-strap setting
Units: Volts
Equation: VOUT = VOUT_COMMAND × 2-13
Range: 0 to VOUT_MAX
Example: VOUT_COMMAND = 699Ah = 27,034
Target voltage equals 27034 × 2-13 = 3.3V
COMMAND
VOUT_COMMAND (21h)
Format
Linear-16 Unsigned
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
VSET Pin-strap Setting
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VOUT_TRIM (22h)
Definition: The VOUT_TRIM command is used to apply a fixed trim voltage to the output voltage command value. This command
is typically used by the manufacturer of a power supply subassembly to calibrate a device in the subassembly circuit. The two
bytes are formatted as a two’s complement binary mantissa, used in conjunction with the exponent of -13h.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear -16 Signed
Type: R/W
Protectable: Yes
Default Value: 0000h
Units: Volts
Equation: VOUT trim = VOUT_TRIM× 2-13
Range: ±150mV
COMMAND
VOUT_TRIM (22h)
Format
Linear-16 Signed
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VOUT_CAL_OFFSET (23h)
Definition: The VOUT_CAL_OFFSET command is used to apply a fixed offset voltage to the output voltage command value. This
command is typically used by the user to calibrate a device in the application circuit. The two bytes are formatted as a two’s
complement binary mantissa, used in conjunction with the exponent of -13h.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear -16 Signed
Type: R/W
Protectable: Yes
Default Value: 0000h
Units: Volts
Equation: VOUT calibration offset = VOUT_CAL_OFFSET×2-13
Range: ±150mVV
COMMAND
VOUT_CAL_OFFSET (23h)
Format
Linear-16 Signed
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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VOUT_MAX (24h)
Definition: The VOUT_ MAX command sets an upper limit on the output voltage the unit can command regardless of any other
commands or combinations. The intent of this command is to provide a safeguard against a user accidentally setting the output
voltage to a possibly destructive level rather than to be the primary output overprotection. If a VOUT_COMMAND is sent with a
value higher than VOUT_MAX, the device will set the output voltage to VOUT_MAX. Note that this command setting does not
automatically scale with a stored VOUT_COMMAND setting.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear -16 Unsigned
Type: R/W
Protectable: Yes
Default Value: 1.15 x VSET pin-strap setting
Units: Volts
Equation: VOUT max = VOUT_MAX × 2-13
Range: 0V to 5.5V
COMMAND
VOUT_MAX (24h)
Format
Linear-16 Unsigned
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
1.15 x VSET Pin-strap Setting
VOUT_MARGIN_HIGH (25h)
Definition: Sets the value of the VOUT during a margin high. This VOUT_MARGIN_HIGH command loads the unit with the
voltage to which the output is to be changed when the OPERATION command is set to “Margin High”.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-16 Unsigned
Type: R/W word
Protectable: Yes
Default Value: 1.05 x VSET pin-strap setting.
Units: V
Equation: VOUT margin high = VOUT_MARGIN_HIGH x 2-13
Range: 0V to VOUT_MAX
COMMAND
VOUT_MARGIN_HIGH (25h)
Format
Linear-16 Unsigned
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
1.05 x VSET Pin-strap Setting
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VOUT_MARGIN_LOW (26h)
Definition: Sets the value of the VOUT during a margin low. This VOUT_MARGIN_LOW command loads the unit with the voltage
to which the output is to be changed when the OPERATION command is set to “Margin Low”.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-16 Unsigned.
Type: R/W
Protectable: Yes
Default Value: 0.95 x VSET pin-strap setting.
Units: V
Equation: VOUT margin low = VOUT_MARGIN_LOW
Range: 0V to VOUT_MAX
COMMAND
VOUT_MARGIN_LOW (26h)
Format
Linear-16 Unsigned
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
0.95 x VSET Pin-strap Setting
VOUT_TRANSITION_RATE (27h)
Definition: This command sets the rate at which the output should change voltage when the device receives an OPERATION
command (Margin High, Margin Low) that causes the output voltage to change. The maximum possible positive value of the two
data bytes indicates that the device should make the transition as quickly as possible. This commanded rate does not apply
when the device is commanded to turn on or to turn off.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: BA00h (1.0V/ms)
Units: V/ms
Equation: VOUT_TRANSITION_RATE = Y×2N
Range: 0.1 to 4V/ms
COMMAND
VOUT_TRANSITION_RATE (27h)
Format
Linear-11
Bit Position
15
14
13
12
11
Access
R/W
R/W
R/W
R/W
R/W
Function
Default Value
10
9
R/W R/W
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
Signed Exponent, N
1
0
1
1
Signed Mantissa, Y
1
0
1
0
0
0
0
0
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VOUT_DROOP (28h)
Definition: The VOUT_DROOP sets the effective load line (V/I slope) for the rail in which the device is used. It is the rate, in mV/A
at which the output voltage decreases with increasing output current for use with passive current sharing schemes. For devices
that are set to sink output current (negative output current), the output voltage continues to increase as the output current is
negative.
VOUT_DROOP is not needed with a single (2-phase) ZL8802. VOUT_DROOP is needed when multiple ZL8802s are operated in
current sharing mode, i.e., 4-, 6- and 8-phase configurations. In this case, VOUT_DROOP is calculated based on the combined
output current of all phases as applicable.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: Set by CFG pin-strap setting
Units: mV/A
Equation: VOUT_DROOP = Y×2N
Range: 0 to 40mV/A
COMMAND
VOUT_DROOP (28h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Signed Exponent, N
Default Value
Signed Mantissa, Y
Set by CFG Pin-strap Setting
FREQUENCY_SWITCH (33h)
Definition: Sets the switching frequency of the device. Initial default value is defined by a pin-strap and this value can be
overridden by writing this command. If an external SYNC is utilized, this value should be set as close as possible to the external
clock value. The output must be disabled when writing this command. Available frequencies are defined by the equation fSW =
16MHz/n where
12 S n S 80.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: SYNC pin-strap setting
Units: kHz
Equation: FREQUENCY_SWITCH = Y×2N
Range: 200kHz-1.33MHz
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COMMAND
FREQUENCY_SWITCH (33h)
Format
Linear-11
Bit Position
15
Access
R/W
Function
14
13
12
11
10
9
8
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Signed Exponent, N
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Signed Mantissa, Y
Default Value
SYNC Pin-strapped Value
INTERLEAVE (37h)
Definition: Configures the phase offset of a device that is sharing a common SYNC clock with other devices. A desired phase
position is specified. Interleave is used for setting the phase offset between individual devices, current sharing groups, and/or
combinations of devices and current sharing groups. For devices within single current sharing group the phase offset is set
automatically. In a multiphase current share group the same interleave settings must be stored in all devices in the current
sharing group in order to phase spread properly. Interleave Offset refers to the phase offset of Phase 0 of the device; Phase 1 is
always Phase 0 + 180 degrees.
INTERLEAVE Phase offset is calculated with Equation:
Phase Offset (in degrees) = Rounded Position • 16 Number • 22.5
Phase offsets greater than 360 degrees are “wrapped around” by subtracting 360 degrees.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: Set by CFG pin-strap setting.
Units: N/A
COMMAND
INTERLEAVE (37h)
Format
Bit Field
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
See Following Table
Default Value
Set by CFG Pin-strap Setting
BITS
PURPOSE
VALUE
15:8
Not Used
0
7:4
Number In Group
0 to 15d
3:0
Position in Group
(Interleave Order)
0 to 15d
DESCRIPTION
Not used
Sets the number of devices in the interleave group. A value of 0
is interpreted as 16.
Sets position of the device’s rail within the group. A value of 0 is interpreted as 16.
Position 1 will have a 22.5 degree offset.
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IOUT_CAL_GAIN (38h)
Definition: Sets the effective impedance across the current sense circuit for use in calculating output current at +25°C.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: B2AEh (0.67mfi)
Units: mfi
Equation: IOUT_CAL_GAIN = Y×2N
COMMAND
IOUT_CAL_GAIN (38h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
0
1
1
1
1
0
Function
Default Value
Signed Exponent, N
1
0
1
1
Signed Mantissa, Y
0
1
0
IOUT_CAL_OFFSET (39h)
Definition: Used to null out any offsets in the output current sensing circuit, and to compensate for delayed measurements of
current ramp due to the current sense blanking time (see “ISENSE_CONFIG (D0h)”).
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: BD00h (-1.5A)
Units: A
Equation: IOUT_CAL_OFFSET = Y×2N
COMMAND
IOUT_CAL_OFFSET (39h)
Format
Linear-11
Bit Position
15
Access
R/W
Function
Default Value
14
13
12
11
10
9
8
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Signed Exponent, N
1
0
1
1
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
Signed Mantissa, Y
1
1
0
1
0
0
0
0
tech.support@psbel.com
SRBP-80A2P0
43
VOUT_OV_FAULT_LIMIT (40h)
Definition: Sets the VOUT overvoltage fault threshold.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-16 Unsigned
Type: R/W
Protectable: Yes
Default Value: 1.10 x VSET pin-strap setting.
Units: V
Equation: VOUT OV fault limit = VOUT_OV_FAULT_LIMIT×2-13
Range: 0V to 7.99V
COMMAND
VOUT_OV_FAULT_LIMIT (40h)
Format
Linear-16 Unsigned
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
1.10 x VSET Pin-strap Setting
VOUT_OV_FAULT_RESPONSE (41h)
Definition: Configures the VOUT overvoltage fault response. The retry time is the time between restart attempts.
Paged or Global: Paged
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: 80h (shut down immediately, no retries)
Units: Retry time = 35ms increments
COMMAND
VOUT_OV_FAULT_RESPONSE (41h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
Function
Default Value
See Following Table
1
0
0
0
0
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North America
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Asia-Pacific
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SRBP-80A2P0
44
BIT
FIELD NAME
Response behavior, the device:
• Pulls SALRT low
• Sets the related fault bit in the status
registers. Fault bits are only cleared
by the CLEAR_FAULTS command.
7:6
VALUE
DESCRIPTION
00-01
Not used
10-11
Disable and retry according to the setting in bits [5:3].
000
No retry. The output remains disabled until the device is restarted.
001-110
5:3
Retry Setting
111
2:0
Retry Delay
000-111
Not used
Attempts to restart continuously, until it is commanded OFF (by the
ENABLE pin or OPERATION command or both), bias power is removed,
or another fault condition causes the unit to shut down. The time between
the start of each attempt to restart is set by the value in bits [2:0]
multiplied by 35ms.
Retry delay time = (Value +1)*35ms. Sets the time between retries in
35ms increments. Range is 35ms to 280ms.
VOUT_UV_FAULT_LIMIT (44h)
Definition: Sets the VOUT undervoltage fault threshold. This fault is masked during ramp, before power-good is asserted or
when the device is disabled. VOUT_UV_FAULT_LIMIT should be set to a value below POWER_GOOD
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-16 Unsigned.
Type: R/W
Protectable: Yes
Default Value: 0.85 x VSET pin-strap setting.
Units: V
Equation: VOUT UV fault limit = VOUT_UV_FAULT_LIMIT×2-13
Range: 0V to 7.99V
COMMAND
VOUT_UV_FAULT_LIMIT (44h)
Format
Linear-16 Unsigned
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
0.85 x VSET Pin-strap Setting
VOUT_UV_FAULT_RESPONSE (45h)
Definition: Configures the VOUT undervoltage fault response. Note that VOUT UV faults can only occur after Power-good (PG)
has been asserted. Under some circumstances this will cause the output to stay fixed below the power-good threshold
indefinitely. If this behavior is undesired, use setting 80h. The retry time is the time between restart attempts.
Paged or Global: Paged
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: 80h (shut down immediately, no retries)
tech.support@psbel.com
SRBP-80A2P0
45
Units: Retry time unit = 35ms
COMMAND
VOUT_UV_FAULT_RESPONSE (45h)
Format
Bit Field
Bit Position
7
6
5
Access
R/W
R/W
R/W
Function
Default Value
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
0
0
0
See Following Table
1
0
0
0
0
VOUT_UV_FAULT_RESPONSE (45h)
BIT
FIELD NAME
VALUE
DESCRIPTION
00-01
Not used
10-11
Disable and Retry according to the setting in bits [5:3].
000
No retry. The output remains disabled until the fault is cleared.
Response Behavior: the device:
• Pulls SALRT low
• Sets the related fault bit in the status
registers. Fault bits are only cleared
by the CLEAR_FAULTS command.
7:6
001-110
5:3
Retry Setting
111
2:0
Retry Delay
000-111
Not used
Attempts to restart continuously, until it is commanded OFF
(by the ENABLE pin or OPERATION command or both), bias
power is removed, or another fault condition causes the unit
to shut down. The time between the start of each attempt to
restart is set by the value in bits [2:0] multiplied by 35ms.
Retry delay time = (Value+1)*35ms. Sets the time between
retries in 35ms increments. Range is 35ms to 280ms.
IOUT_OC_FAULT_LIMIT (46h)
Definition: Sets the IOUT peak overcurrent fault threshold. This limit is applied to current measurement samples taken after the
Current Sense Blanking Time has expired (see “ISENSE_CONFIG (D0h)”)). A fault occurs after this limit is exceeded for the
number of consecutive samples as defined in ISENSE_CONFIG. This feature shares the OC fault bit operation (in STATUS_IOUT)
and OC fault response with IOUT_AVG_OC_FAULT_LIMIT.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: CFG pin-strap setting
Units: A
Equation: IOUT_OC_FAULT_LIMIT = Y×2N
Range: -100A to 100A
COMMAND
IOUT_OC_FAULT_LIMIT(46h)
Format
Linear-11
Bit Position
Access
Function
15
14
13
12
R/W R/W R/W R/W
11
10
9
8
7
6
5
4
3
2
1
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Signed Exponent, N
Signed Mantissa, Y
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North America
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Asia-Pacific
+86 755 298 85888
SRBP-80A2P0
46
Default Value
CFG Pin-strap Setting
IOUT_UC_FAULT_LIMIT (4Bh)
Definition: Sets the IOUT valley undercurrent fault threshold. This limit is applied to current measurement samples taken after the
Current Sense Blanking Time has expired. A fault occurs after this limit is exceeded for the number of consecutive sample as
defined in ISENSE_CONFIG. This feature shares the UC fault bit operation (in STATUS_IOUT) and UC fault response with
IOUT_AVG_UC_FAULT_LIMIT.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: -1 * IOUT_OC_FAULT_LIMIT from CFG pin-strap setting
Units: A
Equation: IOUT_OC_FAULT_LIMIT = Y×2N
Range: -100A to 100A
COMMAND
IOUT_UC_FAULT_LIMIT (4Bh)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Signed Exponent, N
Default Value
Signed Mantissa, Y
-1 * IOUT_OC_FAULT_LIMIT from CFG Pin-strap Setting
OT_FAULT_LIMIT (4Fh)
Definition: The OT_FAULT_LIMIT command sets the temperature at which the device should indicate an over-temperature fault.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: EBE8h (+125°C)
Units: Celsius
Equation: OT_FAULT_LIMIT = Y×2N
Range: 0 to 175°C
COMMAND
OT_FAULT_LIMIT(4Fh)
Format
Linear-11
Bit Position
15
14
13
12
11
Access
R/W
R/W
R/W
R/W
R/W
Function
Default Value
10
9
R/W R/W
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
0
0
0
Signed Exponent, N
1
1
1
0
Signed Mantissa, Y
1
0
1
1
1
0
tech.support@psbel.com
SRBP-80A2P0
47
OT_FAULT_RESPONSE (50h)
Definition: The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an overtemperature fault. The retry time is the time between restart attempts.
Paged or Global: Paged
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: BFh (Continuous retries, retry delay 280ms)
Units: Retry time unit = 35ms
COMMAND
OT_FAULT_RESPONSE(50h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
1
1
1
1
Function
Default Value
See Following Table
1
1
OT_FAULT_RESPONSE (50h)
BIT
FIELD NAME
Response Behavior: the device:
• Pulls SALRT low
• Sets the related fault bit in the
7:6
status registers. Fault bits are
only cleared by the
CLEAR_FAULTS command.
5:3
Retry Setting
2:0
Retry Delay
VALUE
DESCRIPTION
00-01
Not used
10
Disable and Retry according to the setting in bits [5:3].
11
Output is disabled while the fault is present. Operation resumes and the
output is enabled when the temperature falls below the OT_WARN_LIMIT.
000
No retry. The output remains disabled until the fault is cleared.
001-110
Not used
Attempts to restart continuously, until it is commanded OFF (by the
ENABLE pin or OPERATION command or both), bias power is removed, or
another fault condition causes the unit to shut down. A retry is attempted
111
after the temperature falls below the OT_WARN_LIMIT. The time between
the start of each attempt to restart is set by the value in bits [2:0] multiplied
by 35ms.
Retry delay time = (Value +1)*35ms. Sets the time between retries in 35ms
000-111
increments. Range is 35ms to 280ms.
Europe, Middle East
+353 61 225 977
North America
+1 408 785 5200
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BCD.20023_AG
Asia-Pacific
+86 755 298 85888
SRBP-80A2P0
48
OT_WARN_LIMIT (51h)
Definition: The OT_WARN_LIMIT command sets the temperature at which the device should indicate an over-temperature
warning alarm. In response to the OT_WARN_LIMIT being exceeded, the device: Sets the TEMPERATURE bit in
STATUS_WORD, sets the OT_WARNING bit in STATUS_TEMPERATURE and notifies the host.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: EB70h (+110°C)
Units: Celsius
Equation: OT_WARN_LIMIT = Y×2N
Range: 0 to 175°C
COMMAND
OT_WARN_LIMIT (51h)
Format
Linear-11
Bit Position
15
14
13
Access
R/W
R/W
R/W
Function
Default Value
12
11
R/W R/W
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
Signed Exponent, N
1
1
1
0
Signed Mantissa, Y
1
0
1
1
0
1
1
1
UT_WARN_LIMIT (52h)
Definition: The UT_WARN_LIMIT command set the temperature at which the device should indicate an under-temperature
warning alarm. In response to the UT_WARN_LIMIT being exceeded, the device: Sets the TEMPERATURE bit in
STATUS_WORD, sets the UT_WARNING bit in STATUS_TEMPERATURE and notifies the host.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: DC40h (-30°C)
Units: Celsius
Equation: UT_WARN_LIMIT = Y×2N
Range: -55°C to +25°C
COMMAND
UT_WARN_LIMIT (52h)
Format
Linear-11
Bit Position
15
14
13
Access
R/W
R/W
R/W
Function
Default Value
12
11
R/W R/W
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
Signed Exponent, N
1
1
0
1
Signed Mantissa, Y
1
1
0
0
0
1
0
0
tech.support@psbel.com
SRBP-80A2P0
49
UT_FAULT_LIMIT (53h)
Definition: The UT_FAULT_LIMIT command sets the temperature, in degrees Celsius, of the unit at which it should indicate an
under-temperature fault.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: E530h (-45°C)
Units: Celsius
Equation: UT_FAULT_LIMIT = Y×2N
Range: -55°C to +25°C
COMMAND
UT_FAULT_LIMIT (53h)
Format
Linear-11
Bit Position
15
14
13
Access
R/W
R/W
R/W
Function
Default Value
12
11
R/W R/W
10
9
8
7
6
5
4
3
2
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
Signed Exponent, N
1
1
1
0
0
R/W
Signed Mantissa, Y
0
1
0
1
0
0
1
1
0
UT_FAULT_RESPONSE (54h)
Definition: Configures the under-temperature fault response as defined by the table below. The retry time is the time between
restart attempts.
Paged or Global: Paged
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: BFh (Continuous retries, 280ms retry delay)
Units: Retry time unit = 35ms
COMMAND
UT_FAULT_RESPONSE (54h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
1
1
1
1
Function
Default Value
See Following Table
1
1
Europe, Middle East
+353 61 225 977
North America
+1 408 785 5200
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BCD.20023_AG
Asia-Pacific
+86 755 298 85888
SRBP-80A2P0
50
BIT
FIELD NAME
Response behavior, the device:
• Pulls SALRT low
• Sets the related fault bit in the
7:6
status registers. Fault bits are
only cleared by the
CLEAR_FAULTS command.
5:3
Retry Setting
2:0
Retry Delay
VALUE
DESCRIPTION
00-01
Not used
10
Disable and Retry according to the setting in bits [5:3].
11
Output is disabled while the fault is present. Operation resumes and the
output is enabled when the temperature rises above the UT_WARN_LIMIT.
000
No retry. The output remains disabled until the device is restarted.
001-110
Not used
Attempts to restart continuously, until it is commanded OFF (by the ENABLE
pin or OPERATION command or both), bias power is removed, or another
fault condition causes the unit to shut down. A retry is attempted after the
111
temperature rises above UT_WARN_LIMIT. The time between the start of
each attempt to restart is set by
the value in bits [2:0] multiplied by 35ms.
Retry delay time = (Value +1)*35ms. Sets the time between retries in 35ms
000-111
increments. Range is 35ms to 280ms.
VIN_OV_FAULT_LIMIT(55h)
Definition: Sets the VIN overvoltage fault threshold.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: D380h (14V)
Units: V
Equation: VIN_OV_FAULT_LIMIT = Y×2N
Range: 0 to 19V
COMMAND
VIN_OV_FAULT_LIMIT(55h)
Format
Linear-11
Bit Position
15
Access
R/W
Function
Default Value
14
13
R/W
R/W
12
11
R/W R/W
10
9
8
7
R/W
R/W
R/W
R/W
Signed Exponent, N
1
1
0
1
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
Signed Mantissa, Y
0
0
1
1
1
0
0
0
tech.support@psbel.com
SRBP-80A2P0
51
VIN_OV_FAULT_RESPONSE (56h)
Definition: Configures the VIN overvoltage fault response as defined by the table below.
Paged or Global: Global
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: 80h (Disable, no retry)
Units: N/A
COMMAND
VIN_OV_FAULT_RESPONSE (56h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
0
0
0
0
Function
Default Value
BIT
See Following Table
FIELD NAME
Response behavior, the device:
• Pulls SALRT low
• Sets the related fault bit in the
7:6
status registers. Fault bits are
only cleared by the
CLEAR_FAULTS command.
5:3
VALUE
DESCRIPTION
Not used
10
Disable and Retry according to the setting in bits [5:3].
11
Output is disabled while the fault is present. Operation resumes and
the output is enabled when VIN falls below the VIN_OV_WARN_LIMIT.
000
No retry. The output remains disabled until the fault is cleared.
001-110
Not used
Retry Setting
Retry Delay
0
00-01
111
2:0
0
000-111
Attempts to restart continuously, until it is commanded OFF (by the
ENABLE pin or OPERATION command or both), bias power is
removed, or another fault condition causes the unit to shut down. A
retry is attempted after the output falls below the
VIN_OV_WARN_LIMIT. The time between the start of each attempt to
restart is set by the value in bits [2:0] multiplied by 35ms.
Retry delay time = (Value +1)*35ms. Sets the time between retries in
35ms increments. Range is 35ms to 280ms.
Europe, Middle East
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North America
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BCD.20023_AG
Asia-Pacific
+86 755 298 85888
SRBP-80A2P0
52
VIN_OV_WARN_LIMIT (57h)
Definition: Sets the VIN overvoltage warning threshold as defined by the table below. In response to the OV_WARN_LIMIT being
exceeded, the device: Sets the NONE OF THE ABOVE and INPUT bits in STATUS_WORD, sets the VIN_OV_WARNING bit in
STATUS_INPUT and notifies the host.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: D360h (13.5V)
Units: V
Equation: VIN_OV_FAULT_LIMIT = Y×2N
Range: 0 to 19V
COMMAND
VIN_OV_WARN_LIMIT (57h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
Function
Default Value
Signed Exponent, N
1
1
0
1
Signed Mantissa, Y
0
0
1
1
0
1
1
0
VIN_UV_WARN_LIMIT (58h)
Definition: Sets the VIN undervoltage warning threshold. If a VIN_UV_FAULT occurs, the input voltage must rise above
VIN_UV_WARN_LIMIT to clear the fault, which provides hysteresis to the fault threshold. In response to the UV_WARN_LIMIT
being exceeded, the device: Sets the NONE OF THE ABOVE and INPUT bits in STATUS_WORD, Sets the VIN_UV_WARNING
bit in STATUS_INPUT, and notifies the host.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: 1.10 x UVLO pin-strap setting
Units: V
Equation: VIN_UV_WARN_LIMIT = Y×2N
Range: 0 to 19V
COMMAND
VIN_UV_WARN_LIMIT (58h)
Format
Linear-11
Bit Position
15
14
Access
R/W
R/W
Function
13
12
R/W R/W
Signed Exponent, N
11
10
9
8
7
6
5
4
3
2
1
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Signed Mantissa, Y
tech.support@psbel.com
SRBP-80A2P0
53
Default Value
1.10 x UVLO Pin-strap Setting
VIN_UV_FAULT_LIMIT (59h)
Definition: Sets the VIN undervoltage fault threshold.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: UVLO pin-strap setting
Units: V
Equation: VIN_UV_FAULT_LIMIT = Y×2N
Range: 0 to 19V
COMMAND
VIN_UV_FAULT_LIMIT (59h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Signed Exponent, N
Signed Mantissa, Y
Default Value
UVLO pin-strapped value
VIN_UV_FAULT_RESPONSE (5Ah)
Definition: Configures the VIN undervoltage fault response as defined by the table below. The retry time is the time between
restart attempts.
Paged or Global: Global
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: BFh (continuous retries, 280ms retry delay)
Units: Retry time unit = 35ms
COMMAND
VIN_UV_FAULT_RESPONSE (5Ah)
Format
Bit Field
Bit Position
7
6
5
Access
R/W
R/W
R/W
Function
Default Value
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
0
0
0
See Following Table
1
0
0
0
0
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54
BIT
7:6
FIELD NAME
VALUE
Response behavior, the
device:
• Pulls SALRT low
• Sets the related fault bit in
the status registers. Fault
bits are only cleared by the
CLEAR_FAULTS command.
DESCRIPTION
00-01
Not used
10
Disable and retry according to the setting in bits [5:3].
11
Output is disabled while the fault is present. Operation resumes and
the output is enabled when VIN rises above the VIN_UV_WARN_LIMIT.
000
No retry. The output remains disabled until the fault is cleared.
001-110
5:3
Retry Setting
111
2:0
Retry Delay
000-111
Not used
Attempts to restart continuously, until it is commanded OFF (by the
ENABLE pin or OPERATION command or both), bias power is
removed, or another fault condition causes the unit to shut down. A
retry is attempted after the input voltage rises above the
VIN_UV_WARN_LIMIT. The time between the start of each attempt to
restart is set by the value in bits [2:0] multiplied by 35ms.
Retry delay time = (Value +1)*35ms. Sets the time between retries in
35ms increments. Range is 35ms to 280ms.
POWER_GOOD_ON (5Eh)
Definition: Sets the voltage threshold for power-good indication. Power-good asserts when the output voltage exceeds
POWER_GOOD_ON and reasserts when the output voltage is less than VOUT_UV_FAULT_LIMIT. POWER_GOOD_ON should
be set to a value above VOUT_UV_FAULT_LIMIT.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-16 Unsigned
Type: R/W
Protectable: Yes
Default Value: 0.9 x VSET pin-strap setting.
Units: V
COMMAND
POWER_GOOD_ON (5Eh)
Format
Linear-16 Unsigned
Bit Position
15
14
13
12
11
10
Access
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0.9 x VSET Pin-strap Setting
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TON_DELAY (60h)
Definition: Sets the delay time from when the device is enabled to the start of VOUT rise.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: CA80h (5ms)
Units: ms
Equation: TON_DELAY = Y×2N
Range: 0 to 5 seconds
COMMAND
TON_DELAY (60h)
Format
Linear-11
Bit Position
15
Access
R/W
Function
Default Value
14
13
12
11
10
9
8
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Signed Exponent, N
1
1
0
0
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
Signed Mantissa, Y
1
0
1
0
1
0
0
0
TON_RISE (61h)
Definition: Sets the rise time of VOUT after ENABLE and TON_DELAY for single and dual channel operation. To adjust the rise
time in 4-, 6- or 8-phase operation, use MULTI_PHASE_RAMP_GAIN (D5h).
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: CA80h (5ms)
Units: ms
Equation: TON_RISE = Y×2N
Range: 0 to 100ms. Although values can be set below 0.50ms, rise time accuracy cannot be guaranteed. In addition, short rise
times may cause excessive input and output currents to flow, thus triggering overcurrent faults at start-up.
COMMAND
TON_RISE (61h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
Function
Default Value
Signed Exponent, N
1
1
0
0
Signed Mantissa, Y
1
0
1
0
1
0
0
0
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56
TOFF_DELAY (64h)
Definition: Sets the delay time from DISABLE to start of VOUT fall.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: CA80h (5ms)
Units: ms
Equation: TON_DELAY = Y×2N
Range: 0 to 5 seconds
COMMAND
TOFF_DELAY (64h)
Format
Linear-11
Bit Position
15
Access
R/W
Function
Default Value
14
13
12
11
10
9
8
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Signed Exponent, N
1
1
0
0
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
Signed Mantissa, Y
1
0
1
0
1
0
0
0
TOFF_FALL (65h)
Definition: Sets the fall time for VOUT after DISABLE and TOFF_DELAY. This setting is only valid in single or 2-phase operation.
Setting the TOFF_FALL to values less than 0.5ms will cause the ZL8802 to turn-off both the high and low-side FETs (or disable
the DrMOS device) immediately after the expiration of the TOFF_DELAY time. In 4-, 6- or 8-phase operation, the ZL8802 will
always turn-off both the high and low-side FETs (or disable the DrMOS device) immediately after the expiration of the
TOFF_DELAY time.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: CA80h (5ms)
Units: ms
Equation: TOFF_FALL = Y×2N
Range: 0 to 100ms. Values less than 0.5ms will cause the ZL8802 to tri-state the PWM signal (turn-off both the high and lowside FETs) immediately after the expiration of the TOFF_DELAY time.
COMMAND
TOFF_FALL (65h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
Function
Default Value
Signed Exponent, N
1
1
0
0
Signed Mantissa, Y
1
0
1
0
1
0
0
0
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STATUS_BYTE (78h)
Definition: The STATUS_WORD command returns two bytes of information with a summary of the unit’s fault condition. Based
on the information in these bytes, the host can get more information by reading the appropriate status registers. The low byte of
the STATUS_WORD is the same register as the STATUS_BYTE (78h) command.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Bit Field
Type: Read Only
Protectable: No
Default Value: 00h
Units: N/A
COMMAND
STATUS_BYTE (78h)
Format
Bit Field
Bit Position
7
6
5
Access
R
R
R
Function
Default Value
4
3
2
1
0
R
R
R
R
R
0
0
0
See Following Table
0
0
0
0
0
BIT NUMBER
STATUS BIT NAME
MEANING
7
BUSY
A fault was declared because the device was busy and unable to respond.
6
OFF
This bit is asserted if the unit is not providing power to the output, regardless of
the reason, including simply not being enabled.
5
VOUT_OV_FAULT
An output overvoltage fault has occurred.
4
IOUT_OC_FAULT
An output overcurrent fault has occurred.
3
VIN_UV_FAULT
An input undervoltage fault has occurred.
2
TEMPERATURE
A temperature fault or warning has occurred.
1
CML
A communications, memory or logic fault has occurred.
None of the above
A fault other than the faults listed in bits 7:1 above has occurred. The source of
the fault will be in bits 15:8 of the STATUS_WORD
0
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58
STATUS_WORD (79h)
Definition: The STATUS_WORD command returns two bytes of information with a summary of the unit’s fault condition. Based
on the information in these bytes, the host can get more information by reading the appropriate status registers. The low byte of
the STATUS_WORD is the same register as the STATUS_BYTE (78h) command.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Bit Field
Type: Read Only
Protectable: No
Default Value: 0000h
Units: N/A
COMMAND
STATUS_WORD (79h)
Format
Bit Field
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
Function
Default Value
See Following Table
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
STATUS BIT NAME
MEANING
15
VOUT
An output voltage fault or warning has occurred.
14
IOUT
An output current fault has occurred.
13
INPUT
An input voltage fault or warning has occurred.
12
MFG_SPECIFIC
A manufacturer specific fault or warning has occurred.
11
POWER_GOOD #
The POWER_GOOD signal, if present, is negated. (Note 15)
10
NOT USED
Not used
9
OTHER
A bit in STATUS_VOUT, STATUS_IOUT, STATUS_INPUT, STATUS_TEMPERATURE,
STATUS_CML, or STATUS_MFR_SPECIFIC is set.
8
Not Used
Not used
7
BUSY
A fault was declared because the device was busy and unable to respond.
6
OFF
This bit is asserted if the unit is not providing power to the output, regardless of the
reason, including simply not being enabled.
5
VOUT_OV_FAULT
An output overvoltage fault has occurred.
4
IOUT_OC_FAULT
An output overcurrent fault has occurred.
3
VIN_UV_FAULT
An input undervoltage fault has occurred.
2
TEMPERATURE
A temperature fault or warning has occurred.
1
CML
A communications, memory or logic fault has occurred.
0
None of the above
A fault other than the faults listed in bits 7:1 above has occurred. The source of the
fault will be in bits 15:8 of the STATUS_WORD
NOTE:15. If the POWER_GOOD# bit is set, this indicates that the POWER_GOOD signal, if present, is signaling that the output
power is not good.
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STATUS_VOUT (7Ah)
Definition: The STATUS_VOUT command returns one data byte with the status of the output voltage.
Paged or Global: Paged
Data Length in Bytes: 1
Data Format: Bit Field
Type: Read Only
Protectable: No
Default Value: 00h
Units: N/A
COMMAND
STATUS_VOUT (7Ah)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
0
0
0
0
0
0
Function
See Following Table
Default Value
0
0
BIT NUMBER
STATUS BIT NAME
MEANING
7
VOUT_OV_FAULT
Indicates an output overvoltage fault.
6
VOUT_OV_WARNING
Not used
5
VOUT_UV_WARNING
Not used
4
VOUT_UV_FAULT
Indicates an output undervoltage fault.
3:0
Not Used
Not used
STATUS_IOUT (7Bh)
Definition: The STATUS_IOUT command returns one data byte with the status of the output current.
Paged or Global: Paged
Data Length in Bytes: 1
Data Format: Bit Field
Type: Read Only
Protectable: No
Default Value: 00h
Units: N/A
COMMAND
STATUS_IOUT (7Bh)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
0
0
0
Function
Default Value
See Following Table
0
0
0
0
0
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BIT NUMBER
STATUS BIT NAME
MEANING
7
IOUT_OC_FAULT
An output overcurrent fault has occurred.
6
Not Used
Not used
5
Not Used
Not used
4
IOUT_UC_FAULT
An output undercurrent fault has occurred.
3:0
Not Used
Not used
STATUS_INPUT (7Ch)
Definition: The STATUS_INPUT command returns input voltage and input current status information.
Paged or Global: Global
Data Length in Bytes: 1
Data Format: Bit Field
Type: Read-only
Protectable: No
Default Value: 00h
Units: N/A
COMMAND
STATUS_INPUT (7Ch)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
0
0
0
0
0
0
Function
Default Value
See Following Table
BIT NUMBER
STATUS BIT NAME
0
0
MEANING
7
VIN_OV_FAULT
An input overvoltage fault has occurred.
6
VIN_OV_WARNING
An input overvoltage warning has occurred.
5
VIN_UV_WARNING
An input undervoltage warning has occurred.
4
VIN_UV_FAULT
An input undervoltage fault has occurred.
3:0
Not Used
Not used
STATUS_TEMPERATURE (7Dh)
Definition: The STATUS_TEMPERATURE command returns one byte of information with a summary of any temperature related
faults or warnings.
Paged or Global: Paged
Data Length in Bytes: 1
Data Format: Bit Field
Type: Read-only
Protectable: No
Default Value: 00h
Units: N/A
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COMMAND
STATUS_TEMP (7Dh)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
0
0
0
Function
Default Value
See Following Table
0
0
0
0
0
BIT NUMBER
STATUS BIT NAME
MEANING
7
OT_FAULT
An over-temperature fault has occurred.
6
OT_WARNING
An over-temperature warning has occurred.
5
UT_WARNING
An under-temperature warning has occurred.
4
UT_FAULT
An under-temperature fault has occurred.
3:0
Not Used
Not used
STATUS_CML (7Eh)
Definition: The STATUS_WORD command returns one byte of information with a summary of any communications, logic and/or
memory errors.
Paged or Global: Global
Data Length in Bytes: 1
Data Format: Bit Field
Type: Read Only
Protectable: No
Default Value: 00h
Units: N/A
COMMAND
STATUS_CML (7Eh)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
0
0
0
0
0
0
Function
Default Value
See Following Table
0
0
BIT NUMBER
MEANING
7
Invalid or unsupported Power Management bus command was received.
6
The Power Management bus command was sent with invalid or unsupported data.
5
A packet error was detected in the Power Management bus command.
4:2
Not used
1
A Power Management bus command tried to write to a read-only or protected command, or a
communication fault other than the ones listed in this table has occurred.
0
Not used
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62
STATUS_MFR_SPECIFIC (80h)
Definition: The STATUS_MFR_SPECIFIC command returns one byte of information providing the status of the device’s voltage
monitoring and clock synchronization faults.
Paged or Global: Global
Data Length in Bytes: 1
Data Format: Bit Field
Type: Read Only
Protectable: No
Default Value: 00h
Units: N/A
COMMAND
STATUS_MFR_SPECIFIC (80h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
0
0
0
Function
See Following Table
Default Value
BIT
0
FIELD NAME
0
0
0
0
MEANING
7
Not Used
Not used
6
DDC Warning
An error was detected on the DDC bus.
5
VMON UV Warning
4
VMON OV Warning
3
External Switching Period Fault
2
Not Used
1
VMON UV Fault
0
VMON OV Fault
The voltage on the VMON pin has dropped 10% below the level set by
MFR_VMON_UV_FAULT.
The voltage on the VMON pin has risen 10% above the level set by
MFR_VMON_OV_FAULT.
Loss of external clock synchronization has occurred.
Not used
The voltage on the VMON pin has dropped below the level set by
MFR_VMON_UV_FAULT.
The voltage on the VMON pin has risen above the level set by
MFR_VMON_OV_FAULT.
READ_VIN (88h)
Definition: Returns the input voltage reading.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Linear-11
Type: Read Only
Protectable: No
Default Value: N/A
Units: V
Equation: READ_VIN = Y×2N
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Range: N/A
COMMAND
READ_VIN (88h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
N/A
N/A
Function
Signed Exponent, N
Default Value
N/A
N/A
N/A
N/A
Signed Mantissa, Y
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
6
5
4
3
2
1
0
R
R
R
R
R
R
R
N/A
N/A
N/A
N/A
READ_IIN (89h)
Definition: Returns the input current reading.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Linear-11
Type: Read Only
Protectable: No
Default Value: N/A
Units: A
Equation: READ_IIN = Y×2N
Range: N/A
COMMAND
READ_IIN (89h)
Format
Linear-11
Bit Position
15
Access
R
Function
Default Value
14
13
12
11
10
9
8
7
R
R
R
R
R
R
R
R
Signed Exponent, N
N/A
N/A
N/A
N/A
Signed Mantissa, Y
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
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64
READ_VOUT (8Bh)
Definition: Returns the output voltage reading.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-16 Unsigned
Type: Read Only
Protectable: No
Default Value: N/A
Equation: READ_VOUT = READ_VOUT × 2-13
Units: V
COMMAND
READ_VOUT (8Bh)
Format
Linear-16 Unsigned
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
6
5
4
3
2
1
0
R
R
R
R
R
R
R
N/A
N/A
N/A
N/A
READ_IOUT (8Ch)
Definition: Returns the output current reading.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: Read Only
Protectable: No
Default Value: N/A
Units: A
Equation: READ_IOUT = Y×2N
Range: N/A
COMMAND
READ_IOUT (8Ch)
Format
Linear-11
Bit Position
15
Access
R
Function
Default Value
14
13
12
11
10
9
8
7
R
R
R
R
R
R
R
R
Signed Exponent, N
N/A
N/A
N/A
N/A
Signed Mantissa, Y
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
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65
READ_TEMPERATURE_1 (8Dh)
Definition: Returns the temperature reading internal to the device.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Linear-11
Type: Read Only
Protectable: No
Default Value: N/A
Units: °C
Equation: READ_TEMPERATURE_1 = Y×2N
Range: N/A
COMMAND
READ_TEMPERATURE_1 (8Dh)
Format
Linear-11
Bit Position
15
Access
R
Function
Default Value
14
13
12
11
10
9
8
7
R
R
R
R
R
R
R
R
Signed Exponent, N
N/A
N/A
N/A
N/A
6
5
4
3
2
1
0
R
R
R
R
R
R
R
N/A
N/A
N/A
N/A
Signed Mantissa, Y
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
READ_TEMPERATURE_2 (8Eh)
Definition: Returns the temperature reading from the external temperature device connected to XTEMP.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: Read Only
Protectable: No
Default Value: N/A
Units: °C
Equation: READ_TEMPERATURE_2 = Y×2N
Range: N/A
COMMAND
READ_TEMPERATURE_2 (8Eh)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Function
Default Value
Signed Exponent, N
N/A
N/A
N/A
N/A
Signed Mantissa, Y
N/A
N/A
N/A
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READ_TEMPERATURE_3 (8Fh)
Definition: Returns the temperature reading from the VMON/TMON pin when the device is configured to read temperature on the
VMON/TMON pin by setting bit 12 in the USER_GLOBAL_CONFIG command to 1. The voltage on the VMON/TMON pin is
converted to °C by the equation TEMPERTATURE 3 = (VMON voltage - 0.6V)/0.008. See MFR_VMON commands starting on page
85 (F5h, F6h, F8h, F9H) for fault limits when reading temperature on the VMON/TMON pin. When using the Intersil ISL9922X smart
power stage, a 2:1 voltage divider is needed between the TMON pin of the ISL9922X and the VMON/TMON pin of the ZL8802.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Linear-11
Type: Read Only
Protectable: No
Default Value: N/A
Units: °C
Equation: READ_TEMPERATURE_3 = Y×2N
Range: N/A
COMMAND
READ_TEMPERATURE_3 (8Fh)
Format
Linear-11
Bit Position
15
Access
R
Function
Default Value
14
13
12
11
10
9
8
7
R
R
R
R
R
R
R
R
Signed Exponent, N
N/A
N/A
N/A
N/A
6
5
4
3
2
1
0
R
R
R
R
R
R
R
Signed Mantissa, Y
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
READ_DUTY_CYCLE (94h)
Definition: Reports the actual duty cycle of the converter during the enable state.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: Read Only
Protectable: No
Default Value: N/A
Units: %
Equation: READ_DUTY_CYCLE = Y×2N
Range: 0 to 100%
COMMAND
READ_DUTY_CYCLE (94h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Function
Default Value
Signed Exponent, N
N/A
N/A
N/A
N/A
Signed Mantissa, Y
N/A
N/A
N/A
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READ_FREQUENCY (95h)
Definition: Reports the actual switching frequency of the converter during the enable state.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Linear-11
Type: Read Only
Default Value: N/A
Units: kHz
Equation: READ_FREQUENCY = Y×2N
Range: N/A
COMMAND
READ_FREQUENCY (95h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Function
Signed Exponent, N
Default Value
N/A
N/A
N/A
Signed Mantissa, Y
N/A N/A
N/A
N/A
N/A
POWER MANAGEMENT BUS_REVISION (98h)
Definition: The POWER MANAGEMENT BUS_REVISION command returns the revision of the PBus Specification to which the
device is compliant.
Data Length in Bytes: 1
Data Format: Bit Field
Type: Read Only
Protectable: N/A
Default Value: 22h (Part 1 Revision 1.2, Part 2 Revision 1.2)
Units: N/A
COMMAND
POWER MANAGEMENT BUS_REVISION (98h)
Format
Bit Field
Bit Position
7
6
5
Access
R
R
R
Function
Default Value
4
3
2
1
0
R
R
R
R
R
0
1
0
See Following Table
0
0
1
0
0
BITS 7:4
PART 1 REVISION
BITS 3:0
PART 2 REVISION
0000
1.0
0000
1.0
0001
1.1
0001
1.1
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0010
1.2
0010
1.2
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MFR_ID (99h)
Definition: MFR_ID sets a user defined identification string not to exceed 32 bytes. The sum total of characters in MFR_ID,
MFR_MODEL, MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command
cannot exceed 128bytes. This limitation includes multiple writes of this command before a STORE command. To clear multiple
writes, perform a RESTORE, write this command then perform a STORE/RESTORE.
Paged or Global: Global
Data Length in Bytes: User defined
Data Format: ASCII, ISO/IEC 8859-1
Type: Block R/W
Protectable: Yes
Default Value: Null
Units: N/A
MFR_MODEL (9Ah)
Definition: MFR_MODEL sets a user defined model string not to exceed 32 bytes. The sum total of characters in MFR_ID,
MFR_MODEL, MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command
cannot exceed 128bytes. This limitation includes multiple writes of this command before a STORE command. To clear multiple
writes, perform a RESTORE, write this command then perform a STORE/RESTORE.
Paged or Global: Global
Data Length in Bytes: User defined
Data Format: ASCII, ISO/IEC 8859-1
Type: Block R/W
Protectable: Yes
Default Value: Null
Units: N/A
MFR_REVISION (9Bh)
Definition: MFR_REVISION sets a user defined revision string not to exceed 32 bytes. The sum total of characters in MFR_ID,
MFR_MODEL, MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command
cannot exceed 128bytes. This limitation includes multiple writes of this command before a STORE command. To clear multiple
writes, perform a RESTORE, write this command then perform a STORE/RESTORE.
Paged or Global: Global
Data Length in Bytes: User defined
Data Format: ASCII. ISO/IEC 8859-1
Type: Block R/W
Protectable: Yes
Default Value: Null
Units: N/A
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MFR_LOCATION (9Ch)
Definition: MFR_LOCATION sets a user defined location identifier string not to exceed 32 bytes. The sum total of characters in
MFR_ID, MFR_MODEL, MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per
command cannot exceed 128bytes. This limitation includes multiple writes of this command before a STORE command. To
clear multiple writes, perform a RESTORE, write this command then perform a STORE/RESTORE.
Paged or Global: Global
Data Length in Bytes: User defined
Data Format: ASCII. ISO/IEC 8859-1
Type: Block R/W
Protectable: Yes
Default Value: Null
Units: N/A
MFR_DATE (9Dh)
Definition: MFR_DATE sets a user defined date string not to exceed 32 bytes. The sum total of characters in MFR_ID,
MFR_MODEL, MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command
cannot exceed 128bytes. This limitation includes multiple writes of this command before a STORE command. To clear multiple
writes, perform a RESTORE, write this command then perform a STORE/RESTORE.
Paged or Global: Global
Data Length in Bytes: User defined
Data Format: ASCII. ISO/IEC 8859-1
Type: Block R/W
Protectable: Yes
Default Value: Null
Units: N/A
MFR_SERIAL (9Eh)
Definition: MFR_SERIAL sets a user defined serialized identifier string not to exceed 32 bytes. The sum total of characters in
MFR_ID, MFR_MODEL, MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per
command cannot exceed 128bytes. This limitation includes multiple writes of this command before a STORE command. To
clear multiple writes, perform a RESTORE, write this command then perform a STORE/RESTORE.
Paged or Global: Global
Data Length in Bytes: User defined
Data Format: ASCII. ISO/IEC 8859-1
Type: Block R/W
Protectable: Yes
Default Value: Null
Units: N/A
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IC_DEVICE_ID (ADh)
Definition: Reports device identification information.
Data Length in Bytes: 4
Data Format: CUS
Type: Block Read
Protectable: No
Default Value: 49A02D00h (ZL8802)
Units: N/A
COMMAND
IC_DEVICE_ID (ADh)
Format
Block Read
Byte Position
3
2
1
0
Function
MFR code
ID High Byte
ID Low Byte
Reserved
Default Value
49h
A0h
2Ah
00h
IC_DEVICE_REV (AEh)
Definition: Reports device revision information.
Data Length in Bytes: 4
Data Format: CUS
Type: Block Read
Protectable: No
Default Value: 01000000h (initial release)
Units: N/A
COMMAND
IC_DEVICE_REV (AEh)
Format
Block Read
Byte Position
3
2
1
0
Function
Firmware Major
Firmware Minor
Factory Configuration
Reserved
Default Value
01h
00h
00h
00h
USER_DATA_00 (B0h)
Definition: USER_DATA_00 sets a user defined data string not to exceed 32 bytes. The sum total of characters in MFR_ID,
MFR_MODEL, MFR_REVISION, MFR_LOCATION, MFR_DATE, MFR_SERIAL and USER_DATA_00 plus one byte per command
cannot exceed 128bytes This limitation includes multiple writes of this command before a STORE command. To clear multiple
writes, perform a RESTORE, write this command then perform a STORE/RESTORE.
Paged or Global: Global
Data Length in Bytes: User defined
Data Format: ASCII. ISO/IEC 8859-1
Type: Block R/W
Protectable: Yes
Default Value: Null
Units: N/A
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MIN_VOUT_REG (CEh)
Definition: Sets the minimum output voltage in millivolts (mV) that the device will attempt to regulate to during start-up and
shutdown ramps.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: 0000h (0mV)
Units: A
Equation: MIN_VOUT_REG = Y x 2N
COMMAND
MIN_VOUT_REG (CEh)
Format
Linear-11
Bit Position
15
14
13
12
11
Access
R/W
R/W
R/W
R/W
R/W
Function
10
9
R/W R/W
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
0
0
Signed Exponent, N
Default Value
1
1
1
1
Signed Mantissa, Y
0
0
1
0
0
1
0
1
ISENSE_CONFIG (D0h)
Definition: Configures current sense circuitry.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Bit Field
Type: R/W word
Protectable: Yes
Default Value: 620Eh (384ns blanking, SPS sensing, high range)
Units: N/A
Range: N/A
COMMAND
ISENSE_CONFIG (D0h)
Format
Bit Field
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
1
1
0
Function
Default Value
See Following Table
0
1
1
0
0
0
1
0
0
0
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ISENSE_CONFIG (D0h)
BIT
VALUE
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
Current Sense Blanking
15:11
01101
Time
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
000
001
Current Sense Fault
10:8
010
Count
10.8
FIELD NAME
Current Sense Fault
Count
7:4
Not Used
3:2
Current Sense Control
1:0
Current Sense Range
SETTING
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
1
3
5
DESCRIPTION
Sets the blanking time current sense blanking time in
increments of 32ns
011
7
100
101
110
9
11
13
111
15
0000
00
01
10
11
00
01
10
11
Not Used
Not Used
DCR (Down Slope)
DCR (Up Slope)
SPS
Low Range
Medium Range
High Range
Not Used
Sets the number of consecutive overcurrent (OC) or
undercurrent (UC) events required for a fault. An event can
occur once during each switching cycle. For example, if 5 is
selected, an OC or UC event must occur for 5 consecutive
switching cycles, resulting in a delay of at least 5 switching
periods.
Sets the number of consecutive overcurrent (OC) or
undercurrent (UC) events required for a fault. An event can
occur once during each switching cycle. For example, if 5 is
selected, an OC or UC event must occur for 5 consecutive
switching cycles, resulting in a delay of at least 5 switching
periods.
Not used
Selection of current sensing method (SPS IMON)
Low range ±25mV, medium range ±35mV, high range ±50mV
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74
USER_CONFIG (D1h)
Definition: Configures several user-level features. This command should be saved immediately after being written to the desired
user or default store. This is recommended when written as an individual command or as part of a series of commands in a
configuration file or script.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: Set by CFG pin-strap setting
Units: N/A
COMMAND
USER_CONFIG (D1h)
Format
Bit Field
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
See Following Table
Default Value
CFG Pin-strap Setting
USER_CONFIG (D1h)
BIT
FIELD NAME
15:11
Minimum Duty Cycle
VALUE
SETTING
DESCRIPTION
00000
0-31d
Sets the minimum duty-cycle to 2X(VALUE+1)/512. Must
be enabled with Bit 7
10
Not Used
1
Not Used
Not used
9:8
Not Used
00
Not Used
Not used
Minimum Duty Cycle
Control
0
Disable
7
1
Enable
6
Not Used
0
Not Used
5
VSET Select
4
Not Used
0
VSET0
1
VSET1
0
0
Not Used
Control for minimum duty cycle
Not used
0 = Uses only VSET0 to set the pin-strapped output
voltage
1 = Uses only VSET1 to set the pin-strapped output
voltage
Not used
Low when disabled PWML is low (off) when device is disabled (bit 3 set to 0),
or high (on) when device is disabled (bit 3 set to 1)
High when disabled
3
PWML disabled state
1
Power-good
Configuration
0
Open Drain
0 = PG is open-drain output
2
1
Push-Pull
1 = PG is push-pull output
0
Disable
1
XTEMP Enable
1
Enable
0
XTEMP Fault Select
0
Disable
Enable external temperature sensor
Selects external temperature sensor to determine
temperature faults
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IIN_CAL_GAIN (D2h)
Definition: Sets the effective impedance across the current sense circuit for use in calculating input current at +25°C.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: C200h (2mΩ)
Units: mΩ
Equation: IIN_CAL_GAIN = Y×2N
COMMAND
IIN_CAL_GAIN (D2h)
Format
Linear-11
Bit Position
15
Access
14
13
12
11
10
9
R/W R/W R/W R/W R/W R/W
Function
8
7
1
1
0
0
5
4
3
2
1
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Signed Exponent, N
Default Value
6
Signed Mantissa, Y
0
0
1
0
0
0
0
0
0
0
0
0
DDC_CONFIG (D3h)
Definition: Configures DDC addressing and current sharing for up to 8 phases. To operate as a 2-phase controller, set both
phases to the same rail ID, set phases in rail to 2, then set each phase ID sequentially as 0 and 1. To operate as a 4-phase
controller, set all phases to the same rail ID, set phases in rail to 4, then set each phase ID alternately, for example, the first
ZL8802 will be set to 0 and 2, the second ZL8802 will be set to 1 and 3. The ZL8802 will automatically equally offset the phases
in the rail. Phase spreading is done automatically as part of the DDC_CONFIG command. When using CFG pin-strap settings,
the DDC_CONFIG command is set automatically.
NOTE: The output MUST be connected to VSEN0P and VSEN0N when operating as a 2-phase controller.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: Power Management bus address pin-strap dependent.
Units: N/A
COMMAND
DDC_CONFIG (D3h)
Format
Bit Field
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
Function
See Following Table
Default Value
Lower 5 bits of device address
0
0
BIT
FIELD NAME
VALUE
SETTING
DESCRIPTION
15:13
Phase ID
0 to 7
0
Sets the output's phase position within the rail
12:8
Rail ID
0 to 31d
0
Identifies the device as part of a current sharing rail (Shared output)
7:3
Not Used
00
00
Not used
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2:0
Phases In Rail
0 to 7
0
Identifies the number of phases on the same rail (+1)
POWER_GOOD_DELAY (D4h)
Definition: Sets the delay applied between the output exceeding the PG threshold (POWER_GOOD_ON) and asserting the PG
pin. The delay time can range from 0ms up to 500ms, in steps of 125ns. A 1ms minimum configured value is recommended to
apply proper debounce to this signal.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: BA00h, 1ms
Units: ms
Equation: POWER_GOOD_DELAY = Y×2N
Range: 0 to 500ms
COMMAND
POWER_GOOD_DELAY (D4h)
Format
Linear-11
Bit Position
15
14
13
12
11
Access
R/W
R/W
R/W
R/W
R/W
Function
Default Value
10
9
R/W R/W
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
Signed Exponent, N
1
0
1
1
Signed Mantissa, Y
1
0
1
0
0
0
0
0
MULTI_PHASE_RAMP_GAIN (D5h)
Definition: MULTI_PHASE_RAMP_GAIN command value indirectly determines the output voltage rise time during the turn-on
ramp. Typical gain values range from 1 to 10. Lower gain values produce longer ramp times.
MULTI_PHASE_RAMP_GAIN mode is automatically selected when the ZLS8802 is configured to operate in a 4-phase current
sharing group. When in MULTI_PHASE_RAMP_GAIN mode, the turn-on ramp up is done with the high bandwidth ASCR control
circuitry disabled, resulting in a lower loop bandwidth during start-up ramps. Once POWER_GOOD has been asserted, ASCR
circuitry is enabled and the ZLS8802 operates normally. When MULTI_PHASE_RAMP_GAIN mode is enabled, soft-off ramps are
not allowed (TOFF_FALL is ignored). When the ZL8802 is commanded to shut down, the PWMHO/1 output is tri-stated, turning
both the high-side and low-side MOSFETs off, and the PWML0/1 pin is pulled low (DrMOS disabled). Large load current
transitions during multiphase ramp-ups will cause output voltage discontinuities.
When the phase count is 2; i.e., when the ZL8802 is operating standalone, ASCR is enabled at all times and all commands
associated with turn-on and turn-off (TON_RISE, TOFF_FALL, Soft-Off) operate normally.
Rise time can be calculated using Equation:
Rise time = VOUT_COMMAND 14 • Input Voltage • FREQUENCY_SWITCH (in MHz) • MULTI_PHASE_RAMP_GAIN
Paged or Global: Global
Data Length in Bytes: 1
Data Format: Custom
Type: R/W
Protectable: Yes
Default Value: 03h
Units: N/A
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COMMAND
MULTI_PHASE_RAMP_GAIN (D5h)
Format
1 Byte Binary
Bit Position
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
0
0
0
0
0
0
1
1
BIT
FIELD NAME
VALUE
DESCRIPTION
7:0
Gain
00-FF
Start-up ramp gain
INDUCTOR (D6h)
Definition: Informs the device of the circuit’s inductor value. This is used in adaptive algorithm calculations relating to the
inductor ripple current.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: B133h (0.3μH)
Units: μH
Equation: INDUCTOR = Y×2N
Range: 0 to 100μH
COMMAND
INDUCTOR (D6h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
1
Function
Default Value
Signed Exponent, N
1
0
1
1
Signed Mantissa, Y
0
0
0
1
0
0
1
1
SNAPSHOT_FAULT_MASK (D7h)
Definition: Prevents faults from causing a SNAPSHOT event (and store) from occurring.
Data Length in Bytes: 2
Data Format: BIT
Type: R/W
Protectable: Yes
Default Value: 0000h
Units: NA
Range: NA
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78
COMMAND
SNAPSHOT_FAULT_MASK (D7h)
Format
Bit Field
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
Function
Default Value
See Following Table
0
0
0
BIT NUMBER
STATUS BIT NAME
MEANING
15:14
Not Used
Not used
13
Group
Ignore Fault Spreading faults
12
Phase
Ignore Other Phase faults
11
CPU
Ignore CPU faults
10
CRC
Ignore CRC Memory faults
9
Not Used
Not used
8
Not Used
Not used
7
IOUT_UC_FAULT
Ignore output undercurrent faults
6
IOUT_OC_FAULT
Ignore output overcurrent faults
5
VIN_UV_FAULT
Ignore input undervoltage faults
4
VIN_OV_FAULT
Ignore Input undervoltage faults
3
UT_FAULT
Ignore under-temperature faults
2
OT_FAULT
Ignore over-temperature faults
1
VOUT_UV_FAULT
Ignore output undervoltage faults
0
VOUT_OV_FAULT
Ignore output overvoltage faults
OVUV_CONFIG (D8h)
Definition: Configures the output voltage OV and UV fault detection feature
Paged or Global: Paged
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: 00h
Units: N/A
COMMAND
OVUV_CONFIG (D8h)
Format
Bit Position
Bit Field
7
6
5
4
3
2
1
0
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SRBP-80A2P0
Access
79
R/W
R/W
R/W
R/W
Function
R/W
R/W
R/W
R/W
0
0
0
See Following Table
Default Value
0
BITS
0
0
0
0
PURPOSE
VALUE
DESCRIPTION
Controls how an OV fault response shutdown
sets the output driver state
0
An OV fault does not enable low-side power device
1
An OV fault enables the low-side power device
6:4
Not Used
0
Not used
3:0
Defines the number of consecutive limit
violations required to declare an OV or UV fault
N
N+1 consecutive OV or UV violations initiate a fault
response
7
XTEMP_SCALE (D9h)
Definition: Sets a scalar value that is used for calibrating the external temperature. The constant is applied in the equation below
to produce the read value of XTEMP via the Power Management bus command READ_TEMPERATURE_2.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: BA00h (1.0)
Units: 1/°C
Range: 0.1 to 10
COMMAND
XTEMP_SCALE (D9h)
Format
Linear-11
Bit Position
15
Access
R/W
Function
Default Value
14
13
12
11
10
9
8
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Signed Exponent, N
1
0
1
1
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
Signed Mantissa, Y
1
0
1
0
0
0
0
0
XTEMP_OFFSET (DAh)
Definition: Sets an offset value that is used for calibrating the external temperature. The constant is applied in the equation
below to produce the read value of XTEMP via the Power Management bus command READ_TEMPERATURE_2.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: 0000h (0)
Units: °C
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80
Range: -100°C to 100°C
COMMAND
XTEMP_OFFSET (DAh)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
Function
Default Value
Signed Exponent, N
0
0
0
0
Signed Mantissa, Y
0
0
0
0
0
0
0
0
MFR_SMBALERT_MASK (DBh)
Definition: The MFR_SMBALERT_MASK command is used to prevent faults from activating the SALRT pin. The bits in each byte
correspond to a specific fault type as defined in the STATUS command.
Data Length in Bytes: 7
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: 00 00 00 00 00 00 00h (No faults masked)
Units: N/A
COMMAND
MFR_SMBALT_MASK (DBh)
Format
Bit Field
Access
R/W
R/W
R/W
Bit Position
55
54
53
52
Default Value Byte 6
0
0
0
Function
R/W
R/W
R/W
R/W
R/W
51
50
49
48
0
0
0
0
0
See following table
Bit Position
47
46
45
44
43
42
41
40
Default Value Byte 5
0
0
0
0
0
0
0
0
Bit Position
39
38
37
36
35
34
33
32
Default Value Byte 4
0
0
0
0
0
0
0
0
Bit Position
31
30
29
28
27
26
25
24
Default Value Byte 3
0
0
0
0
0
0
0
0
Bit Position
23
22
21
20
19
18
17
16
Default Value Byte 2
0
0
0
0
0
0
0
0
Bit Position
15
14
13
12
11
10
9
8
Default Value Byte 1
0
0
0
0
0
0
0
0
Bit Position
7
6
5
4
3
2
1
0
Default Value Byte 0
0
0
0
0
0
0
0
0
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SRBP-80A2P0
81
MFR_SMBALERT_MASK (DBh)
BYTE
STATUS BYTE NAME
MEANING
6
STATUS_MFR_SPECIFIC
Mask manufacturer specific faults as identified in the STATUS_MFR_SPECIFIC
byte.
5
STATUS_OTHER
4
STATUS_CML
3
STATUS_TEMPERATURE
2
STATUS_INPUT
Not used
Mask communications, memory or logic specific faults as identified in the
STATUS_CML byte.
Mask temperature specific faults as identified in the STATUS_TEMPERATURE
byte
Mask input specific faults as identified in the STATUS_INPUT byte
1
STATUS_IOUT
Mask output current specific faults as identified in the STATUS_IOUT byte
0
STATUS_VOUT
Mask output voltage specific faults as identified in the STATUS_VOUT byte
TEMPCO_CONFIG (DCh)
Definition: Configures the correction factor and temperature measurement source when performing temperature coefficient
correction for current sense. TEMPCO_CONFIG values are applied as negative correction to a positive temperature coefficient.
TEMPCO_CONFIG should be set to 3900ppm (27h) when using inductor DCR current sensing in order to compensate for the
variation in inductor resistance due to the temperature coefficient of copper. When using the ISL9922X Smart Power Stage,
TEMPCO_CONFIG should be set to 0ppm (00h) since the IMON signal from the ISL9922X is internally compensated for
temperature.
Paged or Global: Paged
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: 00h (0ppm/°C, copper)
Equation: To determine the hex value of the Tempco Correction factor (TC) for current scale of a power stage current sensing,
first determine the temperature coefficient of resistance for the sensing element, a. This is found with Equation:
=
RREF-R
RREF(TREF-T)
Where:
R = Sensing element resistance at temperature “T”
RREF = Sensing element resistance at reference temperature TREF
a = Temperature coefficient of resistance for the sensing element material
T = Temperature measured by temperature sensor, in degrees Celsius
TREF = Reference temperature that a is specified at for the sensing element material
After a is determined, convert the value in units of 100ppm/°C. This value is then converted to a hex value with Equation:
a
TC= 100
Range: 0 to 12700ppm/˚C
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82
COMMAND
TEMPCO_CONFIG (DCh)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
Function
See Following Table
Default Value
BITS
0
0
PURPOSE
Selects the temp sensor source for tempco
correction
7
6:0
Sets the tempco correction in units of
100ppm/˚C for IOUT_CAL_GAIN
0
0
0
VALUE
DESCRIPTION
0
Selects the internal temperature sensor
1
TC
Selects the XTEMP pin for temperature measurements
(2N3904 Junction) Note that XTEMP must be enabled in
USER_CONFIG, bit 1.
RSEN (DCR) = IOUT_CAL_GAIN x (1+TC x (T-25))
Where RSEN = resistance of sense element
PINSTRAP_READ_STATUS (DDh)
Definition: Reads back 7 bytes of 8 bit values that represent the pin-strap settings of each of the device’s pin-strap pins. This
value corresponds to a resistor value, a high, a low or an open condition. The pin decode values correspond to pin-strap
settings according to Table:
TABLE.
R (kfi)
10
11
12.1
13.3
14.7
16.2
17.8
19.6
21.5
23.7
26.1
28.7
31.6
34.8
38.3
42.2
46.4
DECODE
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
Unmeasured
R (kfi)
51.1
56.2
61.9
68.1
75
82.5
90.9
100
110
121
133
147
162
178
LOW
OPEN
HIGH
DECODE
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
F1
F2
F3
F4
Paged or Global: Global
Data Length in Bytes: 7
Data Format: Bit Field
Type: Read Only
Protectable: Yes
Default Value: Pin-strap settings
Units: N/A
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83
PINSTRAP_READ_STATUS (DDh)
COMMAND
READ_PINSTRAP (DDh)
Format
Bit Field
Bit Position
55
54
53
52
51
50
49
48
Access
R
R
R
R
R
R
R
R
Function
ASCRCFG Pin Decode
Default Value
ASCRCFG Pin-strap Setting
Format
Bit Field
Bit Position
47
46
45
Access
R
R
R
44
43
42
41
40
39
38
37
R
R
R
R
R
R
R
R
36
35
34
33
32
R
R
R
R
R
Function
CFG Pin Decode
SYNC Pin Decode
Default Value
CFG Pin-strap Setting
SYNC Pin-strap Setting
Format
Bit Field
COMMAND
READ_PINSTRAP (DDh) (Continued)
Bit Position
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Function
UVLO Pin Decode
VSET0 Pin Decode
Default Value
UVLO Pin-strap Setting
VSET0 Pin-strap Setting
Format
Bit Field
Bit Position
15
14
13
12
11
10
9
8
7
6
5
Access
R
R
R
R
R
R
R
R
R
R
R
4
3
2
1
0
R
R
R
R
R
Function
VSET1 Pin Decode
Reserved
Default Value
VSET1 Pin-strap Setting
N/A
PINSTRAP_READ_STATUS (DDh)
BITS
PURPOSE
VALUE
DESCRIPTION
55:48
ASCRCFG Pin Decode
00-F4h
Decode value of ASCRCFG pin-strap setting
47:40
CFG Pin Decode
00-F4h
Decode value of CFG pin-strap setting
39:32
SYNC Pin Decode
00-F4h
Decode value of SYNC pin-strap setting
31:24
UVLO Pin Decode
00-F4h
Decode value of UVLO pin-strap setting
23:16
VSET0 Pin Decode
00-F4h
Decode value of VSET0 pin-strap setting
15:8
VSET1 Pin Decode
00-F4h
Decode value of VSET1 pin-strap setting
7:0
Not Used
FF
Not used
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84
ASCR_CONFIG (DFh)
Definition: Allows user configuration of ASCR settings. ASCR gain and residual value are automatically set by the ZL8802 based
on input voltage and output voltage. ASCR gain is analogous to bandwidth, ASCR residual is analogous to damping. To improve
load transient response performance, increase ASCR gain. To lower transient response overshoot, increase ASCR residual.
Increasing ASCR gain can result in increased PWM jitter and should be evaluated in the application circuit. Excessive ASCR gain
can lead to excessive output voltage ripple. Increasing ASCR residual to improve transient response damping can result in slower
recovery times, but will not affect the peak output voltage deviation. Typical ASCR gain settings range from 100 to 1000, and
ASCR residual settings range from 10 to 90.
Paged or Global: Paged
Data Length in Bytes: 4
Data Format: Bit Field and unsigned binary
Type: R/W
Protectable: Yes
Default Value: ASCRCFG pin-strap setting
Units: N/A
COMMAND
ASCR_CONFIG (DFh)
Format
Bit Field/Linear-8 Unsigned
Bit Position
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17 16
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/ R/
W W
0
0
0
0
0
0
Function
See Following Table
Default Value
Format
0
1
ASCRCFG Pin-strap Setting (residual)
Linear-16 Unsigned
Bit Position
15
Access
R/W
14
R/W
13
R/W
12
11
R/W
10
R/W
R/W
9
R/W
8
R/W
7
R/W
6
R/W
Function
See Following Table
Default Value
ASCRCFG Pin-strap Setting (gain)
5
R/W
4
3
R/W
R/W
2
BITS
PURPOSE
VALUE
DESCRIPTION
31:25
Not Used
0000000h
Not used
1
Enable
0
Disable
24
1
0
R/ R/
R/W
W W
ASCR Enable
23:16
ASCR Residual Setting
0 - 7Fh
ASCR residual
15:0
ASCR Gain Setting
0-FFh
ASCR gain
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SRBP-80A2P0
85
SEQUENCE (E0h)
Definition: Identifies the Rail DDC ID of the prequel and sequel rails when performing multi-rail sequencing. The device will
enable its output when its EN or OPERATION enable state, as defined by ON_OFF_CONFIG, is set and the prequel device has
issued a power-good event on the DDC bus as a result of the prequel’s Power-good (PG) signal going high. The device will
disable its output (using the programmed delay values) when the sequel device has issued a power-down event on the DDC bus
at the completion of its ramp-down (its output voltage is 0V).
The data field is a two-byte value. The most-significant byte contains the 5-bit Rail DDC ID of the prequel device. The leastsignificant byte contains the 5-bit Rail DDC ID of the sequel device. The most significant bit of each byte contains the enable of
the prequel or sequel mode. This command overrides the corresponding sequence configuration set by the CONFIG pin
settings.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: 00h (prequel and sequel disabled)
Units: N/A
COMMAND
SEQUENCE (E0h)
Format
Bit Field
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
Function
See Following Table
Default Value
BIT
FIELD NAME
15
Prequel Enable
14:13
Not Used
12:8
Prequel Rail DDC ID
7
Sequel Enable
0
0
0
VALUE
SETTING
DESCRIPTION
0
Disable
Disable, no prequel preceding this rail
1
Enable
Enable, prequel to this rail is defined by bits 12:8
0
Not Used
Not used
0-31d
DDC ID
Set to the DDC ID of the prequel rail
0
Disable
Disable, no sequel following this rail
1
Enable
Enable, sequel to this rail is defined by bits 4:0
6:5
Not Used
0
Not Used
Not used
4:0
Sequel Rail DDC ID
0-31d
DDC ID
Set to the DDC ID of the sequel rail
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86
TRACK_CONFIG (E1h)
Definition: Configures the voltage tracking modes of the device. Single device (Channel 0, Channel 1 or 2-phase) tracking is
supported. Tracking as part of a 4-, 6- or 8-phase current sharing group is not supported. When tracking, the TOFF_DELAY in
the tracking device must be greater than TOFF_DELAY + TOFF_FALL in the device being tracked. When configured to track,
VOUT_COMMAND must be set to the desired steady state output voltage.
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: 00h
Units: N/A
COMMAND
TRACK_CONFIG (E1h)
Format
Bit Field
Bit Position
7
6
5
Access
R/W
R/W
R/W
Function
Default Value
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
0
0
0
See Following Table
0
0
0
0
0
BIT
FIELD NAME
VALUE
SETTING
DESCRIPTION
Voltage Tracking
Control
0
Disable
Tracking is Disabled.
7
1
Enable
Tracking is Enabled.
6:3
Not Used
0000
Not Used
Not used
0
100%
Output Tracks at 100% ratio of VTRK input.
2
Tracking Ratio Control
1
0
1
50%
Output Tracks at 50% ratio of VTRK input.
0
Target Voltage
Output Voltage is Limited by Target Voltage.
1
VTRK Voltage
Output Voltage is Limited by VTRK Voltage.
0
Not Used
Not used
Tracking Upper Limit
Not Used
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SRBP-80A2P0
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DDC_GROUP (E2h)
Definition: Rails (output voltages) are assigned Group numbers in order to share specified behaviors. The DDC_GROUP
command configures fault spreading group ID and enable, broadcast OPERATION group ID and enable, and broadcast
VOUT_COMMAND group ID and enable. Note that DDC Groups are separate and unique from DDC Rail IDs (see “DDC_CONFIG
(D3h)”). Current sharing rails need to be in the same DDC Group in order to respond to broadcast VOUT_COMMAND and
OPERATION commands. Power fail event responses (and phases) are automatically spread in Phase 0 and 1 when the ZL8802
is operating in 2-phase current sharing mode when it is configured using DDC_CONFIG, regardless of its setting in
DDC_GROUP.
Paged or Global: Paged
Data Length in Bytes: 34
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: Set by CFG pin-strap setting
Units: N/A
COMMAND
DDC_GROUP (E2h)
Format
Bit Field
Bit Position
31
30
29
28
27
26
25
24
23
22
21
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Not Used
Default Value
EN>
20
19
18
R/W R/W R/W
17
16
R/W
R/W
VOUT_COMMAND Group ID
Set by CFG Pin-strap Setting
Format
Bit Field
Bit Position
15
14
13
12
11
10
9
8
7
6
5
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Not Used
EN>
OPERATION Group ID
Default Value
Not Used
4
3
2
R/W R/W R/W
EN>
1
0
R/W
R/W
Power Fail Group ID
Set by CFG Pin-strap Setting
DDC_GROUP (E2h)
BITS
PURPOSE
VALUE
DESCRIPTION
31:22
Not Used
00
Not used
1
Responds to broadcast VOUT_COMMAND with same Group ID
21
BROADCAST_VOUT_COMMAND response
0
Ignores broadcast VOUT_COMMAND
20:16
15:14
13
BROADCAST_VOUT_COMMAND group ID 0-31d
Not Used
Group ID sent as data for broadcast VOUT_COMMAND events
00
Not used
1
Responds to broadcast OPERATION with same Group ID
0
Ignores broadcast OPERATION
BROADCAST_OPERATION response
12:8
BROADCAST_OPERATION group ID
0-31d
Group ID sent as data for broadcast OPERATION events
7:6
Not Used
00
Not used
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88
Responds to POWER_FAIL events with same Group ID by shutting
down immediately
Responds to POWER_FAIL events with same Group ID with
sequenced shutdown
1
5
POWER_FAIL response
0
4:0
POWER_FAIL group ID
0-31d
Group ID sent as data for broadcast POWER_FAIL events
DEVICE_ID (E4h)
Definition: Returns the 16-byte (character) device identifier string. The format is: Part number, Major Revision, (period), Minor
Revision, Engineering version letter
Paged or Global: Global
Data Length in Bytes: 16
Data Format: ASCII. ISO/IEC 8859-1
Type: Block Read
Protectable: Read Only
Default Value: ZL8802, current major revision, (period), current minor revision, current engineering version letter
Units: N/A
COMMAND
DEVICE_ID (E4h)
Format
Characters (Bytes)
Characters
15
14
13
12
Access
R
R
R
R
Function
Default Value
11
10
9
8
7
6
R
R
R
R
R
R
Part Number
Z
L
8
8
0
5
4
3
R
R
Maj. Rev.
0
*
*
2
1
R
R
R
.
Min. Rev
*
*
*
0
R
Engr.
*
* Current revision at time of manufacture
MFR_IOUT_OC_FAULT_RESPONSE (E5h)
Definition: Configures the IOUT overcurrent fault response as defined by the table below. The command format is the same as
the Power Management bus standard fault responses except that it sets the overcurrent status bit in STATUS_IOUT. The retry
time is the time between restart attempts.
Paged or Global: Paged
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: 80h (immediate shutdown, no retries)
Units: Retry time
unit = 35ms
COMMAND
MFR_IOUT_OC_FAULT_RESPONSE (E5h)
Format
Bit Field
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SRBP-80A2P0
89
Bit Position
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
0
0
0
0
Function
Default Value
See Following Table
0
0
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90
MFR_IOUT_OC_FAULT_RESPONSE (E5h)
BIT
FIELD NAME
VALUE
DESCRIPTION
00
Not used
7:6
Response behavior, for all modes,
the device:
• Pulls SALRT low
• Sets the related fault bit in the
status registers. Fault bits are only
cleared by the CLEAR_FAULTS
command.
5:3
Retry Setting
2:0
Retry Delay
01
Not used
10
Disable without delay and retry according to the setting in bits 5:3.
11
Output is disabled while the fault is present. Operation resumes and the
output is enabled when the fault is no longer present.
000
No retry. The output remains disabled until the fault is cleared.
001110
Not used
Attempts to restart continuously, without checking if the fault is still present,
until it is commanded OFF (by the CONTROL pin or OPERATION command
111 or both), bias power is removed, or another fault condition causes the unit to
shut down. The time between the start of each attempt to restart is set by
the value in bits [2:0] multiplied by 35ms.
000- Retry delay time = (Value +1)*35ms. Sets the time between retries in 35ms
111
increments. Range is 35ms to 280ms.
MFR_IOUT_UC_FAULT_RESPONSE (E6h)
Definition: Configures the IOUT undercurrent fault response as defined by the table below. The command format is the same as
the Power Management bus standard fault responses except that it sets the undercurrent status bit in STATUS_IOUT. The retry
time is the time between
restart attempts.
Data Length in Bytes: 1
Paged or Global: Paged
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: 80h (Immediate shutdown, no retries)
Units: Retry time
unit = 35ms
COMMAND
MFR_IOUT_UC_FAULT_RESPONSE (E6h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
Function
Default Value
See Following Table
1
0
0
0
0
tech.support@psbel.com
SRBP-80A2P0
BIT
7:6
91
FIELD NAME
VALUE
DESCRIPTION
00
Not used
Response behavior, for all modes, the
device:
• Pulls SALRT low
• Sets the related fault bit in the status
registers. Fault bits are only cleared by
the CLEAR_FAULTS command.
01
Not used
Disable without delay and retry according to the setting in bits
5:3.
Output is disabled while the fault is present. Operation
resumes and the output is enabled when the fault is no longer
present.
10
11
000
No retry. The output remains disabled until the fault is cleared.
001-110
5:3
Retry Setting
2:0
Retry Delay
Not used
Attempts to restart continuously, without checking if the fault
is still present, until it is commanded OFF (by the CONTROL
pin or OPERATION command or both), bias power is removed,
111
or another fault condition causes the unit to shut down. The
time between the start of each attempt to restart is set by the
value in bits [2:0] multiplied by 35ms.
Retry delay time = (Value +1)*35ms. Sets the time between
000-111
retries in 35ms increments. Range is 35ms to 280ms.
IOUT_AVG_OC_FAULT_LIMIT (E7h)
Definition: Sets the IOUT average overcurrent fault threshold. For down-slope sensing, this corresponds to the average of all the
current samples taken during the (1-D) time interval, excluding the current sense blanking time (which occurs at the beginning of
the 1-Dinterval). For up-slope sensing, this corresponds to the average of all the current samples taken during the D time
interval, excluding the current sense blanking time (which occurs at the beginning of the D interval). This feature shares the OC
fault bit operation (in STATUS_IOUT) and OC fault response with IOUT_ OC_FAULT_LIMIT.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: CFG pin-strap setting
Units: Amperes
Equation: IOUT_AVG_OC_FAULT_LIMIT = Y×2N
Range: -100A to 100A
COMMAND
IOUT_AVG_OC_FAULT_LIMIT (E7h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Default Value
Signed Exponent, N
Signed Mantissa, Y
CFG Pin-strap Setting
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92
IOUT_AVG_UC_FAULT_LIMIT (E8h)
Definition: Sets the IOUT average undercurrent fault threshold. For down-slope sensing, this corresponds to the average of all
the current samples taken during the (1-D) time interval, excluding the current sense blanking time (which occurs at the
beginning of the 1-D interval). For up-slope sensing, this corresponds to the average of all the current samples taken during the
D time interval, excluding the current sense blanking time (which occurs at the beginning of the D interval). This feature shares
the UC fault bit operation (in STATUS_IOUT) and UC fault response with IOUT_ UC_FAULT_LIMIT.
Paged or Global: Paged
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: -1 X IOUT_AVG_OC_FAULT_LIMIT as set by CFG pin-strap setting
Units: Amperes
Equation: IOUT_AVG_UC_FAULT_LIMIT = Y×2N
Range: -100A to 100A
COMMAND
IOUT_AVG_UC_FAULT_LIMIT (E8h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Signed Exponent, N
Default Value
Signed Mantissa, Y
-1 X IOUT_AVG_OC_FAULT_LIMIT as set by CFG Pin-strap Setting
USER_GLOBAL_CONFIG (E9h)
Definition: This command is used to set options for output voltage sensing, VMON/TMON pin configuration, SMBus time-out
and DDC and SYNC output configurations.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: Set by CFG pin-strap setting
Units: N/A
COMMAND
USER_GLOBAL_CONFIG (E9h)
Format
Bit Field
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
See Following Table
Default Value
Set by CFG Pin-strap Setting
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USER_GLOBAL_CONFIG (E9h)
BITS
PURPOSE
VALUE
15:13
Not Used
000000
0
12
VMON/TMON Config
1
11:10
Not Used
9:8
SENSE Select for monitoring and
fault detection
7
Not Used
6
DDC output Configuration
5
Not Used
4
Disable SMBus Time-Outs
3
Not Used
2:1
Sync I/O Control
0
Not Used
DESCRIPTION
Not used
MFR_READ_VMON returns voltage on VMON pin in Volts. External
16:1 voltage divider needed on VMON/TMON pin (pin 6) to voltage
being monitored.
READ_TEMPERATURE_3 returns TMON in °C. External 2:1
voltage divider needed on VMON/TMON pin (pin 6) to SPS TMON
pin.
00
Not used
00
Output 0 uses VSEN0, Output 1 uses VSEN1
01
Both outputs use VSEN0
10-11
Not used
0
Not used
0
DDC output open drain
1
DDC output push-pull
0
Not used
0
SMBus time-outs enabled
1
SMBus time-outs disabled
0
Not used
00
Use internal clock (frequency initially set with pin-strap)
01
Use internal clock and output internal clock (not for use with pinstrap)
10
Use external clock
11
Not used
0
Not used
SNAPSHOT (EAh)
Definition: The SNAPSHOT command is a 32-byte read-back of parametric and status values. It allows monitoring and status
data to be stored to flash either during a fault condition or via a system-defined time using the SNAPSHOT_CONTROL
command. Snapshot is continuously updated in RAM and can be read using the SNAPSHOT command. When a fault occurs,
the latest snapshot in RAM is stored to flash. Snapshot data can read back by writing a 01h to the SNAPSHOT_CONTROL
command, then reading SNAPSHOT.
Paged or Global: Paged
Data Length in Bytes: 32
Data Format: Bit Field
Type: Block Read
Protectable: No
Default Value: N/A
Units: N/A
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SRBP-80A2P0
94
BYTE NUMBER
VALUE
Power Management bus COMMAND
FORMAT
31:23
Not Used
Not Used
0000h
22
Flash Memory Status Byte
N/A
Bit Field
21
Manufacturer Specific Status Byte
STATUS_MFR_SPECIFIC (80h)
1 Byte Bit Field
20
CML Status Byte
STATUS_CML (7Eh)
1 Byte Bit Field
19
Temperature Status Byte
STATUS_TEMPERATURE (7Dh)
1 Byte Bit Field
18
Input Status Byte
STATUS_INPUT (7Ch)
1 Byte Bit Field
17
IOUT Status Byte
STATUS_IOUT (7Bh)
1 Byte Bit Field
16
VOUT Status Byte
STATUS_VOUT (7Ah)
1 Byte Bit Field
15:14
Switching Frequency
READ_FREQUENCY (95h)
2 Byte Linear-11
13:12
External Temperature
READ_TEMPERATURE_2 (8Eh)
2 Byte Linear-11
11:10
Internal Temperature
READ_TEMPERATURE_1 (8Dh)
2 Byte Linear-11
9:8
Duty Cycle
READ_DUTY_CYCLE (94h)
2 Byte Linear-11
7:6
Highest Measured Output Current
N/A
2 Byte Linear-11
5:4
Output Current
READ_IOUT (8Ch)
2 Byte Linear-11
3:2
Output Voltage
READ_VOUT (8Bh)
2 Byte Linear-16
Unsigned
1:0
Input Voltage
READ_VIN (88h)
2 Byte Linear-11
LEGACY_FAULT_GROUP (F0h)
Definition: This command allows the ZL8802 to sequence and fault spread with devices other than the ZL8800 family of ICs.
This command sets which rail DDC IDs should be listened to for fault spreading information. The data sent is a 4-byte, 32-bit bit
vector where every bit represents a rail’s DDC ID. A bit set to 1 indicates a device DDC ID to which the configured device will
respond upon receiving a fault spreading event. In this vector, bit 0 of byte 0 corresponds to the rail with DDC ID 0. Following
through, Bit 7 of byte 3 corresponds to the rail with DDC ID 31.
NOTE: The device/rail’s own DDC ID should not be set within the LEGACY_FAULT_GROUP command for that device/rail.
All devices in a current share rail (devices other than the ZL8800 family ICs) must shut down for the rail to report a shutdown.
If fault spread mode is enabled in USER_CONFIG, the device will immediately shut down if one of its DDC_GROUP members
fail. The device/rail will attempt its configured restart only after all devices/rails within the DDC_GROUP have cleared their faults.
If fault spread mode is disabled in USER_CONFIG, the device will perform a sequenced shutdown as defined by the SEQUENCE
command setting. The rails/devices in a sequencing set only attempt their configured restart after all faults have cleared within
the DDC_GROUP. If fault spread mode is disabled and sequencing is also disabled, the device will ignore faults from other
devices and stay enabled.
Paged or Global: Paged
Data Length in Bytes: 4
Data Format: Bit field
Type: Block R/W
Protectable: Yes
Default Value: 00000000h
Units: N/A
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SRBP-80A2P0
95
COMMAND
LEGACY_FAULT_GROUP (F0h)
Format
Bit Field
Bit Position
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
Function
See Following Table
Default Value
Format
0
0
0
Bit Field
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Function
See Following Table
Default Value
0
0
0
0
0
0
0
0
0
0
BIT
FIELD NAME
VALUE
SETTING
DESCRIPTION
31:0
Fault Group
NA
00000000h
Identifies the devices in the fault spreading group.
SNAPSHOT_CONTROL (F3h)
Definition: Writing a 01h will cause the device to copy the current SNAPSHOT values from NVRAM to the 32-byte SNAPSHOT
command parameter. Writing a 02h will cause the device to write the current SNAPSHOT values to NVRAM, 03h will erase all
SNAPSHOT values from NVRAM. Write (02h) and Erase (03h) may only be used when the device is disabled. All other values will
be ignored. SNAPSHOT 03h must be written to the device when the device is DISABLED. Data will not be updated, or written to
NVRAM after a fault occurs until the SNAPSHOT 03h command has been written.
Paged or Global: Paged
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W Byte
Protectable: Yes
Default Value: 00h
Units: N/A
COMMAND
SNAPSHOT_CONTROL (F3h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Function
Default Value
See Following Table
0
0
VALUE
DESCRIPTION
01
Read SNAPSHOT values from NVRAM
02
Write SNAPSHOT values to NVRAM
03
Erase SNAPSHOT values from NVRAM
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96
SRBP-80A2P0
tech.support@psbel.com
SRBP-80A2P0
97
RESTORE_FACTORY (F4h)
Definition: Restores the device to the hard-coded factory default values and pin-strap definitions. The device retains the
DEFAULT and USER stores for restoring. Security level is changed to Level 1 following this command.
Paged or Global: Global
Data Length in Bytes: 0
Data Format: N/A
Type: Write Only
Protectable: Yes
Default Value: N/A
Units: N/A
MFR_VMON_OV_FAULT_LIMIT (F5h)
Definition: Sets the VMON over-temperature fault threshold. The VMON overvoltage warn limit is automatically set to 90% of this
fault value. If VMON is not used, set VMON_OV_FAULT_RESPONSE to 00h, which will disable VMON OV faults entirely.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: C266h (2.4V)
Units: Volts
Equation: MFR_VMON_OV_FAULT_LIMIT = Y×2N
Range: 0 to 20V
COMMAND
MFR_VMON_OV_FAULT_LIMIT (F5h)
Format
Linear-11
Bit Position
15
Access
R/W
Function
Default Value
14
13
12
11
10
9
8
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Signed Exponent, N
1
1
1
0
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
1
1
0
Signed Mantissa, Y
0
0
1
0
0
1
1
0
MFR_VMON_UV_FAULT_LIMIT (F6h)
Definition: Sets the VMON undervoltage fault threshold. The VMON undervoltage warn limit is automatically set to 110% of this
fault value. If VMON is not used, set VMON_UV_FAULT_RESPONSE to 00h, which will disable VMON UV faults entirely.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Linear-11
Type: R/W
Protectable: Yes
Default Value: B0CCh (0.2V)
Units: Volts
Equation: MFR_VMON_UV_FAULT_LIMIT = Y x 2N
Range: 0 to 20V
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SRBP-80A2P0
98
COMMAND
MFR_VMON_UV_FAULT_LIMIT (F6h)
Format
Linear-11
Bit Position
15
14
13
12
11
Access
R/W
R/W
R/W
R/W
R/W
Function
10
9
R/W R/W
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
0
0
Signed Exponent, N
Default Value
1
0
1
1
Signed Mantissa, Y
0
0
0
0
1
1
0
0
MFR_READ_VMON (F7h)
Definition: Reads the voltage on the VMON pin.
Paged or Global: Global
Data Length in Bytes: 2
Data Format: Linear-11
Type: Read Only
Protectable: No
Default Value: N/A
Units: °C
Equation: MFR_READ_VMON = Y x 2N
Range: -200°C to +200°C
COMMAND
MFR_READ_VMON (F7h)
Format
Linear-11
Bit Position
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Function
Default Value
Signed Exponent, N
N/A
N/A
N/A
N/A
Signed Mantissa, Y
N/A
N/A
N/A
VMON_OV_FAULT_RESPONSE (F8h)
Definition: Configures the VMON overvoltage fault response as defined by the table below. Note: The retry time is the time
between restart attempts. If VMON is not used, set this response to 00h, which will disable VMON OV faults entirely
Paged or Global: Global
Data Length in Bytes: 1
Data Format: Bit Field
Type: R/W
Protectable: Yes
Default Value: BFh (continuous retries)
Units: N/A
COMMAND
VMON_OV_FAULT_RESPONSE (F8h)
Format
Bit Field
Bit Position
7
6
5
Access
R/W
R/W
R/W
Function
Default Value
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
1
1
1
See Following Table
1
0
1
1
1
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SRBP-80A2P0
BIT
7:6
99
FIELD NAME
Response behavior, the device:
• Pulls SALRT low
• Sets the related fault bit in
the status registers. Fault bits
are only cleared by the
CLEAR_FAULTS command.
VALUE
DESCRIPTION
00
Ignore faults
01
Not used
10
Disable without delay and retry according to the setting in bits 5:3.
11
Output is disabled while the fault is present. Operation resumes and the
output is enabled when VMON falls below 95% of the
VMON_OV_FAULT_LIMIT setting.
000
No retry. The output remains disabled until the fault is cleared.
001-110
5:3
Retry Setting
111
2:0
Retry Delay
000-111
Not used
Attempts to restart continuously, without checking if the fault is still
present, until it is commanded OFF (by the CONTROL pin or
OPERATION command or both), bias power is removed, or another fault
condition causes the unit to shut down. A retry is attempted after VMON
falls below 95% of the VMON_OV_FAULT_LIMIT. The time between the
start of each attempt to restart is set by the value in bits [2:0] multiplied
by 35ms.
Retry delay time = (Value +1)*35ms. Sets the time between retries in
35ms increments. Range is 35ms to 280ms.
VMON_UV_FAULT_RESPONSE (F9h)
Definition: Configures the VMON undervoltage fault response as defined by the table below. Note: The retry time is the time
between restart attempts. If VMON is not used, set this response to 00h, which will disable VMON UV faults entirely
Paged or Global: Global
Data Length in Bytes: 1
Data Format: Bit Field.
Type: R/W
Protectable: Yes
Default Value: BFh (continuous retries)
Units: Retry time
unit = 35ms
COMMAND
VMON_UV_FAULT_RESPONSE (F9h)
Format
Bit Field
Bit Position
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
1
1
1
1
Function
Default Value
See Following Table
1
1
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SRBP-80A2P0
100
BIT
FIELD NAME
Response behavior, the device:
• Pulls SALRT low
• Sets the related fault bit in
7:6
the status registers. Fault bits
are only cleared by the
CLEAR_FAULTS command.
5:3
VALUE
DESCRIPTION
00
Fault ignored
01
Not used
10
Disable without delay and retry according to the setting in bits 5:3.
11
Output is disabled while the fault is present. Operation resumes and the output
is enabled when VMON rises above 105% of the VMON_UV_FAULT_LIMIT
setting.
000
No retry. The output remains disabled until the fault is cleared.
001110
Not used
Retry Setting
111
2:0
Retry Delay
000111
Attempts to restart continuously, without checking if the fault is still present,
until it is commanded OFF (by the CONTROL pin or OPERATION command or
both), bias power is removed, or another fault condition causes the unit to shut
down. A retry is attempted after VMON has risen above 105% of
VMON_UV_FAULT_LIMIT. The time between the start of each attempt to restart
is set by the value in bits [2:0] multiplied by 35ms.
Retry delay time = (Value +1)*35ms. Sets the time between retries in 35ms
increments. Range is 35ms to 280ms.
SECURITY_LEVEL (FAh)
Definition: The device provides write protection for individual commands. Each bit in the UNPROTECT parameter controls
whether its corresponding command is writeable (commands are always readable). If a command is not writeable, a password
must be entered in order to change its parameter (i.e., to enable writes to that command). There are two types of passwords,
public and private. The public password provides a simple lock-and-key protection against accidental changes to the device. It
would typically be sent to the device in the application prior to making changes. Private passwords allow commands marked as
nonwritable in the UNPROTECT parameter to be changed. Private passwords are intended for protecting default-installed
configurations and would not typically be used in the application. Each store (USER and DEFAULT) can have its own
UNPROTECT string and private password. If a command is marked as nonwritable in the DEFAULT UNPROTECT parameter (its
corresponding bit is cleared), the private password in the DEFAULT store must be sent in order to change that command. If a
command is writeable according to the default UNPROTECT parameter, it may still be marked as nonwritable in the user store
UNPROTECT parameter. In this case, the user private password can be sent to make the command writeable.
The device supports four levels of security. Each level is designed to be used by a particular class of users, ranging from module
manufacturers to end users, as discussed below. Levels 0 and 1 correspond to the public password. All other levels require a
private password. Writing a private password can only raise the security level. Writing a public password will reset the level
down to 0 or 1.
Figure on next page shows the algorithm used by the device to determine if a particular command write is allowed.
Paged or Global: Global
Data Length in Bytes: 1
Data Format: Hex
Type: Read Byte
Protectable: No
Default Value: 01h
Units: N/A
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SRBP-80A2P0
101
SECURITY_LEVEL (FAh)
Default
UNPROTECT
== 0
User
UNPROTECT
== 0
Figure 55. ALGORITHM USED TO DETERMINE WHEN A COMMAND IS WRITEABLE
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Security Level 3 – Module Vendor
Level 3 is intended primarily for use by module vendors to protect device configurations in the default store. Clearing a
UNPROTECT bit in the default store implies that a command is writeable only at Level 3 and above. The device’s security level is
raised to Level 3 by writing the private password value previously stored in the default store. To be effective, the module vendor
must clear the UNPROTECT bit corresponding to the STORE_DEFAULT_ALL and RESTORE_DEFAULT commands. Otherwise,
Level 3 protection is ineffective since the entire store could be replaced by the user, including the enclosed private password.
Security Level 2 – User
Level 2 is intended for use by the end user of the device. Clearing a UNPROTECT bit in the user store implies that a command is
writeable only at Level 2 and above. The device’s security level is raised to Level 2 by writing the private password value
previously stored in the User Store. To be effective, the user must clear the UNPROTECT bit corresponding to the
STORE_USER_ALL, RESTORE_DEFAULT_ALL, STORE_DEFAULT_ALL and RESTORE_DEFAULT commands. Otherwise, Level
2 protection is ineffective since the entire store could be replaced, including the enclosed private password.
Security Level 1 – Public
Level 1 is intended to protect against accidental changes to ordinary commands by providing a global write-enable. It can be
used to protect the device from erroneous bus operations. It provides access to commands whose UNPROTECT bit is set in
both the default and User Store. Security is raised to Level 1 by writing the public password stored in the user store using the
PUBLIC_PASSWORD command. The public password stored in the default store has no effect.
Security Level 0 - Unprotected
Level 0 implies that only commands which are always writeable (e.g., PUBLIC_PASSWORD) are available. This represents the
lowest authority level and hence the most protected state of the device. The level can be reduced to 0 by using
PUBLIC_PASSWORD to write any value which does not match the stored public password.
PRIVATE_PASSWORD (FBh)
Definition: Sets the private password string.
Paged or Global: Global
Data Length in Bytes: 9
Data Format: ASCII. ISO/IEC 8859-1
Type: Block R/W
Protectable: No
Default Value: 000000000000000000h
Units: N/A
PUBLIC_PASSWORD (FCh)
Definition: Sets the public password string.
Paged or Global: Global
Data Length in Bytes: 4
Data Format: ASCII. ISO/IEC 8859-1
Type: Block R/W
Protectable: No
Default Value: 00000000h
Units: N/A
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103
UNPROTECT (FDh)
Definition: Sets a 256-bit (32-byte) parameter which identifies which commands are to be protected against write-access at lower
security levels. Each bit in this parameter corresponds to a command according to the command’s code. The command with a
code of 00h (PAGE) is protected by the least-significant bit of the least-significant byte, followed by the command with a code of
01h and so forth. Note that all possible commands have a corresponding bit regardless of whether they are protectable or
supported by the device. Clearing a command’s UNPROTECT bit indicates that write-access to that command is only allowed if
the device’s security level has been raised to an appropriate level. The UNPROTECT bits in the default store require a security
level 3 or greater to be writeable. The UNPROTECT bits in the user store require a security level of 2 or higher.
Data Length in Bytes: 32
Paged or Global: Global
Data Format: Custom
Type: Block R/W
Protectable: No
Default Value: FF…FFh
Units: N/A
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SRBP-80A2P0
104
The SRBP-80A2P0 modules are designed to be compatible with reflow soldering process. The suggested Pb-free solder paste is
Sn/Ag/Cu(SAC). The recommended reflow profile using Sn/Ag/Cu solder is shown in the following. Recommended reflow peak
temperature is 245 C. This profile should be used only as a guideline. Many other factors influence the success of SMT reflow
soldering. Since your production environment may differ, please thoroughly review these guidelines with your process engineers.
Figure 56.
The SRBP-80A2P0 modules have a MSL rating of 3.
The SRBP-80A2P0 modules are designed to be compatible with J-STD-033 Rev: A (Handling, Packing, Shipping and Use of
Moisture /Reflow Sensitive surface Mount devices). Moisture barrier bags (MBB) with desiccant are applied. The recommended
storage environment and handling procedure is detailed in J-STD-033.
This component has been designed, handled, and packaged ready for Pb-free reflow soldering. If the assembly shop follows JSTD-033 guidelines, no pre-bake of this component is required before being reflowed to a PCB. However, if the J-STD-033
guidelines are not followed by the assembler, Bel recommends that the modules should be pre-baked @ 120~125°C for a
minimum of 4 hours (preferably 24 hours) before reflow soldering. Our packaging tray can only withstand temperature of 70°C
max.
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SRBP-80A2P0
105
0.88 [22.35]
0.847 [21.50]
(4X)
0.809 [20.55]
0.738 [18.75]
0.667 [16.95]
0.597 [15.15]
0.526 [13.35]
0.455 [11.55]
0.384 [9.75]
0.026 [0.65]
(2X)
0.234 [5.95]
0.305 [7.75]
0.051 [1.30]
(12X)
0.268 [6.80]
0.138 [3.50]
0.084 [2.14]
1.00 [25.40]
TOP VIEW
0.014 [0.35]
0.062 [1.57]
(19x)
0.50 [12.70]
0.062 [1.57]
(9X)
0.398 [10.10]
Pick & place plate
0.13 [3.30]
0.242 [6.15]
0.092 [2.35]
0.163 [4.15]
0.313 [7.95]
0.09 [2.29]
(9X)
0.128 [3.25]
0.256 [6.50]
0.384 [9.75]
0.48
[12.20]
MAX.
0.512 [13.00]
0.039 [1.00]
(19X)
0.616 [15.65]
0.685 [17.40]
0.754 [19.15]
0.823 [20.90]
0.062
[1.57]
0.005 [0.13]
0.892 [22.65]
SIDE VIEW
BOTTOM VIEW
Figure 57. Outline
NOTES:
1) All Pins: Material - Copper Alloy;
Finish – Matte Tin
2) Un-dimensioned components are shown for visual reference only.
3) All dimensions in inches (mm); Tolerances: x.xx +/-0.02 inch. (x.x +/-0.5 mm); x.xxx +/-0.010 inch. (x.xx +/-0.25 mm).
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SRBP-80A2P0
106
26
25
24
23
22
21
20
19
18
16
17
27
15
14
28
1
2
3
4
5
6
7
8
9
10
13
11
12
Figure 58. Recommended pad layout
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SRBP-80A2P0
2
1
3
4
5
107
7
6
8
9
10
28
11
13
12
14
15
27
26
25
24
23
22
21
Figure 59. Pins
20
19
16
18
17
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
FUNCTION
Vin
GND
PG1
PG2
EN1
EN2
SYNC
SHARE
ADDR
SCL
SDA
SALERT
SGND
ASCRCFG
PIN
15
16
17
18
19
20
21
22
23
24
25
26
27
28
FUNCTION
CFG
Vtrim1
VS1+
VS1Vtrim2
VS2VS2+
Vout1
Vout1
GND
Vout2
Vout2
GND
Vin
NOTE:
1) Un-dimensioned components are shown for visual reference only.
2) All dimensions in inches (mm); Tolerances: x.xx +/-0.02 inch. (x.x +/-0.5 mm); x.xxx +/-0.010 inch. (x.xx +/-0.25 mm).
PIN
NAME
TYPE
FUNCTION
1
2
3
4
5
6
7
8
Vin
GND
PG1
PG2
EN1
EN2
SYNC
SHARE
Power
Power
Out
Out
In
In
In/Out
In/Out
9
ADDR
In
10
11
SCL
SDA
In/Out
In/Out
12
ALERT
Out
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SGND
ASCRCFG
CFG
Vtrim1
VS1+
VS1Vtrim2
VS2VS2+
Vo1
Vo1
GND
Vo2
Vo2
GND
Vin
Power
In
In
In
In
In
In
In
In
Power
Power
Power
Power
Power
Power
Power
Input voltage.
Power ground.
Vo1 power-good output. Default is push-pull, can be set as an open-drain.
Vo2 power-good output. Default is push-pull, can be set as an open-drain.
Enable or disable Vo1 of the module.
Enable or disable Vo2 of the module
Clock synchronization input. Set the switching frequency. Refer to Switching Frequency Setting.
Current sharing, communication bus between multiple modules.
Serial address select pin. Connect resistor to SGND to assign unique address for each individual
module.
Serial clock. Requires a pull-up resistor to a 2.5V to 5.5V source, the source must be always on.
Serial data. Requires a pull-up resistor to a 2.5V to 5.5V source, the source must be always on.
Serial alert. Asserted low when any fault or alarms are triggered. Requires a pull-up resistor to a
2.5V to 5.5V source, the source must be always on.
Signal ground. SGND is shorted to GND internally.
Control loop configuration settings. Refer to control Loop(ASCR) Setting.
Setting current sense, current limit and operating mode. Refer to Configuration Setting.
Setting output voltage Vo1. Connect resistor to SGND. Refer to Trim/Output Voltage Adjustment.
Positive sense for Vo1. Connect to Vo1 close to the load.
Negative sense fro Vo1. Connect to GND close to the load.
Setting output voltage Vo2. Connect resistor to SGND. Refer to Trim/Output Voltage Adjustment.
Negative sense fro Vo2. Connect to GND close to the load.
Positive sense for Vo2. Connect to Vo2 close to the load.
Output Vo1.
Output Vo1.
Power ground.
Output Vo2.
Output Vo2.
Power ground.
Input voltage.
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SRBP-80A2P0
108
DATE
REVISION
CHANGES DETAIL
APPROVAL
2017-07-14
AA
First release
Z.Tang
2017-11-08
AB
Update the MD, Startup & Shutdown, PG, TR, NR, TD and OCP.
Z.Tang
2018-03-26
AC
Update the Abs Max, Input Specs, Output Specs and Switching Frequency
Z.Tang
2018-04-23
AD
Update the MD, Model Selection, Output Specifications, General, OCP, OTP, Input undervoltage lockout and Power Good. Add Trim, ASCR, RCFG, SYNC, Package, SHARE and
Power Management bus
Z.Tang
2019-06-03
AE
Delete OVP.
XF.Jiang
2019-08-06
AF
Update the Load Regulation in 4-phase, 6-phase 8-phase Mode.
Delete package.
XF.Jiang
2021-03-17
AG
Add object ID, MTBF and input reflected ripple current waveform.
XF.Jiang
NUCLEAR AND MEDICAL APPLICATIONS - Products are not designed or intended for use as critical components in life support systems,
equipment used in hazardous environments, or nuclear control systems.
TECHNICAL REVISIONS - The appearance of products, including safety agency certifications pictured on labels, may change depending on the
date manufactured. Specifications are subject to change without notice.
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