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products are available
Delivers up to 25 A
Input range 10 - 14 V
Small size and low profile: 1.25” x 2.00” x 0.335”
(31.7 x 50.8 x 8.50 mm)
Start-up into pre-biased output
No minimum load required
Operating ambient temperature: -40 °C to 85 °C
Remote output sense
Remote ON/OFF
Fixed frequency operation (500 kHz)
Auto-reset output overcurrent protection
High reliability, MTBF = 23 Million Hours
All materials meet UL94, V-0 flammability rating
Approved to the latest edition and amendment of ITE
Safety standards, UL/CSA 60950-1 and IEC60950-1
Bel Power Solutions point-of-load converters are
recommended for use with regulated bus converters in an
Intermediate Bus Architecture (IBA). The YV-Series of nonisolated dc-dc converters deliver up to 25 Amps of output
current in a through-hole (SIP) package. Operating from a 10
- 14 VDC input, the YV12T25 converter is an ideal choice for
Intermediate Bus Architectures where Point-of-Load (POL)
power delivery is a requirement. The converter provides an
extremely tight regulated programmable output voltage of
0.80 V to 5.5 V.
The YV-Series of converters provide exceptional thermal
performance, even in high temperature environments with
minimal airflow. This performance is accomplished through
the use of advanced circuitry, packaging and processing
techniques to achieve a design possessing ultra-high
efficiency, excellent thermal management, and a very low
body profile.
The low body profile minimizes impedance to system airflow,
thus enhancing cooling for both upstream and downstream
devices. The use of automation for assembly, coupled with
advanced power electronics and thermal design, results in a
product with extremely high reliability.
Intermediate Bus Architectures
Telecommunications
Data Communications
Distributed Power Architectures
Servers, Workstations
High Efficiency– no heat sink required
Cost Effective
Reduces Total Solution Board Area
North America
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Europe, Middle East
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BCD.00690_AA
YV12T25
1. ELECTRICAL SPECIFICATIONS
Conditions: TA = 25 ºC, Airflow = 300 LFM (1.5 m/s), Vin = 12.0 VDC, Vout = 0.8 – 5.5 V, unless otherwise specified.
PARAMETERS
CONDITIONS / DESCRIPTION
MIN
Continuous
-0.3
TYP
MAX
UNITS
14
VDC
Absolute Maximum Ratings
Input Voltage
Operating Ambient Temperature
- 40
85
°C
Storage Temperature
-55
125
°C
5.5
VDC
0.5
VDC
Feature Characteristics
Switching Frequency
Output Voltage Trim Range1
500
By external resistor, See Trim Table 1
0.7887
Remote Sense Compensation1
kHz
Turn-On Delay Time2
Full resistive load
With Vin = (Converter Enabled, then Vin applied)
From Vin = Vin(min) to Vo = 0.1* Vo(nom)
0.5
ms
With Enable (Vin = Vin(nom) applied, then enabled)
From enable to Vo = 0.1*Vo(nom)
1.0
ms
Rise time2 (Full resistive load; No ext. output capacitor)
From 10%Vo(set) to 90%Vo(set)
2.0
ms
SEQ/ENA Control Signal3
Vin=Vin(on) to Vin(max); Open collector or
equivalent; (Signal referenced to GND)
Logic High (Module OFF)
Logic Low (Module ON)
SEQ/ENA Current
0.5
2.33
mA
SEQ/ENA Voltage
3.5
14
VDC
SEQ/ENA Current
200
μA
SEQ/ENA Voltage
0.8
VDC
14
VDC
9.9
VDC
Input Characteristics
Operating Input Voltage Range
Input Undervoltage Lockout
Maximum Input Current
10
12
Turn-on Threshold
Turn-off Threshold
8.1
VDC
25 ADC Output @ 10 VDC Input
VOUT = 5.0 VDC
13.2
ADC
VOUT = 3.3 VDC
8.9
ADC
VOUT = 2.5 VDC
6.9
ADC
VOUT = 2.0 VDC
5.6
ADC
VOUT = 1.8 VDC
5.1
ADC
VOUT = 1.5 VDC
4.3
ADC
VOUT = 1.2 VDC
3.5
ADC
2.5
ADC
VOUT = 0.8 VDC
Input Standby Current (Converter disabled)
25
mA
VOUT = 5.0 VDC
113
mA
VOUT = 3.3 VDC
94
mA
VOUT = 2.5 VDC
84
mA
VOUT = 2.0 VDC
78
mA
VOUT = 1.8 VDC
78
mA
VOUT = 1.5 VDC
77
mA
VOUT = 1.2 VDC
77
mA
VOUT = 0.8 VDC
77
mA
Input Reflected-Ripple Current - is
See Fig. E for setup. (BW = 20 MHz)
30
mAP-P
Input Voltage Ripple Rejection
120 Hz
60
dB
Input No Load Current (Converter enabled)
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BCD.00690_AA
YV12T25
Output Characteristics
Output Voltage Set Point (No Load)
- 1.2
Vout
+1.2
%Vout
Full resistive load
0.01
0.1
%Vout
Over Load
From no load to full load
0.1
0.2
%Vout
Output Voltage Range
Overall operating input voltage, resistive load
and temperature conditions until end of life
+3.0
%Vout
Output Ripple and Noise – 20 MHz bandwidth
Over line, load and temperature
Output Regulation
Over Line
Peak-to-Peak
-3.0
VOUT = 5.0 VDC
40
Output Overvoltage Protection (Non-Latching)
All output voltages
5.7
Overtemperature protection
All output voltages
External Load Capacitance
Plus full load (resistive)
mVP-P
6.0
6.3
V
125
°C
Min ESR > 1mΩ
1000
μF
Min ESR > 10mΩ
10000
μF
6800
μF
Min ESR > 10mΩ
VOUT = 5.0 VDC
Output Current Range
0
Output Current Limit Inception (IOUT)
Output Short-Circuit Current , RMS Value
125
Short = 10 mΩ, continuous
25
A
150
%Iout
3
Arms
Dynamic Response
Load current change from 12.5 A – 25 A,
di/dt = 5 A/μs
No external output capacitance
150
Settling Time (VOUT < 10% peak deviation)
Unloading current change from 25 A – 12.5 A,
di/dt = -5 A/μs
mV
25
µs
No external output capacitance
150
Settling Time (VOUT < 10% peak deviation)
mV
25
µs
VOUT = 5.5 VDC
94.3
%
VOUT = 3.3 VDC
92.2
%
VOUT = 2.5 VDC
90.7
%
VOUT = 2.0 VDC
88.9
%
VOUT = 1.8 VDC
88.0
%
VOUT = 1.5 VDC
86.3
%
VOUT = 1.2 VDC
83.7
%
VOUT = 0.8 VDC
77.7
%
Full Load (25 A)
Efficiency
Notes:
1
2
3
The output voltage should not exceed 5.5 V (taking into account both the programming and remote sense compensation).
Note that startup time is the sum of turn-on delay time and rise time.
The converter is ON if the SEQ/ENA pin is left open.
2. GENERAL SPECIFICATIONS
PARAMETER
NOTES
Calculated MTBF
50% Stress, Ta = 40 °C
Weight
MIN
TYP
MAX
UNITS
23
Million Hours
19 (0.67)
g (oz.)
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BCD.00690_AA
YV12T25
3. OPERATIONS
3.1 INPUT AND OUTPUT IMPEDANCE
The YV-Series converter should be connected via a low impedance to the DC power source. In many applications, the inductance
associated with the distribution from the power source to the input of the converter can affect the stability of the converter. It is
recommended to use low - ESR tantalum, POS or ceramic decoupling capacitors (minimum 150 μF) placed as close as possible to
the converter input pins in order to ensure stability of the converter and reduce input ripple voltage. Internally, the converter has 40
μF (low ESR ceramics) of input capacitance.
The YV12T25-0 has been designed for stable operation with or without external output capacitance.
It is important to keep low resistance and low inductance PCB traces for connecting load to the output pins of the converter in
order to maintain good load regulation.
3.2 SEQ/ENA (PIN 13)
The SEQ/ENA pin is used to turn the power converter on or off remotely via a system signal. If not using the remote ON/OFF, leave
the pin open (module will be on). The SEQ/ENA signal is referenced to ground. The typical connections are shown in Fig. A.
The converter is ON when the SEQ/ENA pin is at a logic low or left open, and OFF when the SEQ/ENA pin is at a logic high (3.5V
min) or connected to Vin. The external resistor R1 should be chosen to maintain 3.5V minimum on the SEQ/ENA pin to insure that
the unit is OFF when Q1 is turned OFF. Note that the external diode is required for proper operation.
Fig. A: Circuit configuration for ON/OFF function.
3.3 REMOTE SENSE (PINS 1 AND 2)
The remote sense feature of the converter compensates for voltage drops occurring between the output pins of the converter and
the load. The SENSE(-) (Pin 2) and SENSE(+) (Pin 1) pins should be connected at the load or at the point where regulation is
required (see Fig. B).
Fig. B: Remote sense circuit configuration.
Because the sense lead carries minimal current, large trace on the end-user board are not required. However, sense trace should
be located close to a ground plane to minimize system noise and ensure the optimum performance.
When utilizing the remote sense feature, care must be taken not to exceed the maximum allowable output power capability of the
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BCD.00690_AA
YV12T25
converter, which is equal to the product of the nominal output voltage and the allowable output current for the given conditions.
When using remote sense, the output voltage at the converter can be increased up to 0.5 V above the nominal rating in order to
maintain the required voltage across the load. Therefore, the designer must, if necessary, decrease the maximum current
(originally obtained from the derating curves) by the same percentage to ensure output power remains at or below the maximum
allowable output power.
3.4 OUTPUT VOLTAGE PROGRAMMING
The output voltage can be programmed from
0.8 V to 5.5 V by connecting an external resistor (RTRIM) between SENSE(+) pin (Pin 1) and Vout pin (see Fig. C).If the RTRIM is not
used and SENSE(+) is shorted to Vout, the output voltage of the module will be 0.7887V. If the SENSE(+) is not connected to the
Vout, the output of the module will reach overvoltage shutdown. A 1μF multilayer ceramic capacitor is required from RTRIM to
SENSE(-) pin to minimize noise.
A trim resistor, RTRIM, for a desired output voltage can be calculated using the following equation:
RTRIM: = 775 (
VO−REQ
0.7887
− 1)
[Ω]
where,
RTRIM Required value of trim resistor [Ω]
VO-REQ Desired (trimmed) output voltage [V]
Fig. C: Configuration for programming output voltage.
Note that the tolerance of a trim resistor directly affects the output voltage tolerance. It is recommended to use standard 1% or
0.5% resistors; for tighter tolerance, two resistors in parallel are recommended rather than one standard value from Table 1.
V0-REG [V]
RTRIM [Ω]
0.8
11
1.0
208
1.2
404
1.5
699
1.8
994
2.0
1190
2.5
1682
3.3
2468
5.0
4138
Overvoltage Shutdown
Open
Table 1: Trim Resistor Values
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BCD.00690_AA
YV12T25
4. PROTECTION FEATURES
4.1. INPUT UNDERVOLTAGE LOCKOUT
Input undervoltage lockout is standard with this converter. The converter will shut down when the input voltage drops below a
pre-determined voltage; it will start automatically when Vin returns to a specified range. .
4.2. OUTPUT OVERCURRENT PROTECTION (OCP)
The converter is protected against overcurrent and short circuit conditions. Upon sensing an overcurrent condition, the converter
will enter hiccup mode. Once over-load or short circuit condition is removed, Vout will return to nominal value.
4.3. OVERTEMPERATURE PROTECTION (OTP)
The converter will shut down under an overtemperature condition to protect itself from overheating caused by operation outside
the thermal derating curves, or operation in abnormal conditions such as system fan failure. After the converter has cooled to a
safe operating temperature, it will automatically restart.
4.4. SAFETY REQUIREMENTS
The converter meets North American and International safety regulatory requirements per UL60950 and EN60950. The maximum
DC voltage between any two pins is Vin under all operating conditions. Therefore, the unit has ELV (extra low voltage) output; it
meets SELV requirements under the condition that all input voltages are ELV. The converter is not internally fused. To comply with
safety agencies’ requirements, a recognized fuse with a maximum rating of 30 Amps must be used in series with the input line.
5. CHARACTERIZATION
5.1. GENERAL INFORMATION
The converter has been characterized for many operational aspects, to include thermal derating (maximum load current as a
function of ambient temperature and airflow) for vertical and horizontal mountings, efficiency, startup and shutdown parameters,
output ripple and noise, transient response to load step-change, overload, and short circuit.
The following pages contain specific plots or waveforms associated with the converter. Additional comments for specific data are
provided below.
5.2. TEST CONDITIONS
All data presented were taken with the converter soldered to a test board, specifically a 0.060” thick printed wiring board (PWB)
with four layers. The top and bottom layers were not metalized. The two inner layers, comprised of two-ounce copper, were used
to provide traces for connectivity to the converter.
The lack of metalization on the outer layers as well as the limited thermal connection ensured that heat transfer from the converter
to the PWB was minimized. This provides a worst-case but consistent scenario for thermal derating purposes.
All measurements requiring airflow were made in the vertical and horizontal wind tunnels using Infrared (IR) thermography and
thermocouples for thermometry.
Ensuring components on the converter do not exceed their ratings is important to maintaining high reliability. If one anticipates
operating the converter at or close to the maximum loads specified in the derating curves, it is prudent to check actual operating
temperatures in the application. Thermographic imaging is preferable; if this capability is not available, then thermocouples may
be used. The use of AWG #40 gauge thermocouples is recommended to ensure measurement accuracy. Careful routing of the
thermocouple leads will further minimize measurement error. Refer to Fig. D for the optimum measuring thermocouple location.
5.3. THERMAL DERATING
Load current vs. ambient temperature and airflow rates are given in Figures 13 to 16 for maximum temperature of 110 °C. Ambient
temperature was varied between 25 °C and 85 °C, with airflow rates from 30 to 400 LFM (0.15 m/s to 2.0 m/s), and vertical and
horizontal converter mountings. The airflow during the testing is parallel to the long axis of the converter.
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BCD.00690_AA
YV12T25
Fig. D: Location of the thermocouples for thermal testing.
For each set of conditions, the maximum load current is defined as the lowest of:
(i)
(ii)
The output current at which any MOSFET temperature does not exceed a maximum specified temperature (110 °C)
as indicated by the thermographic image, or
The maximum current rating of the converter during normal operation, derating curves with maximum FET temperature
less than or equal to 110°C should not be exceeded. Temperature on the MOSFET at the thermocouple location shown
in Fig. D should not exceed 110 °C in order to operate inside the derating curves.
5.4. EFFICIENCY
Figures 1 to 6 shows the efficiency vs. load current plot for ambient temperature of 25 ºC and input voltages of 10.8 V, 12 V, and
13.2 V.
5.5. RIPPLE AND NOISE
The output voltage ripple waveform is measured at full rated load current. Note that all output voltage waveforms are measured
across a 1 μF ceramic capacitor. The output voltage ripple and input reflected ripple current waveforms are obtained using the
test setup shown in Fig. E.
1 uH
Source
Inductance
Vsource
VIN
Cin=150uF
Tantalum
Capacito r
VOUT
Module
Cout = 1uF
VOUT
Ceramic
Capacito r
GND
Fig. E: Test setup for measuring input reflected-ripple currents, is and output voltage ripple.
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YV12T25
Fig. 1: Efficiency vs. load current and input voltage for Vout = 5.0 V.
Fig. 3: Efficiency vs. load current and input voltage for Vout = 2.5 V.
Fig. 2: Efficiency vs. load current and input voltage for Vout = 3.3 V.
Fig. 4: Efficiency vs. load current and input voltage for Vout = 1.8 V.
90
85
80
75
70
Vin = 13.2 Vdc
Vin = 12.0 Vdc
65
Vin = 10.8 Vdc
60
0
5
10
15
20
25
Load Current (Adc)
Fig. 5: Efficiency vs. load current and input voltage for Vout = 1.5 V.
Fig. 6: Efficiency vs. load current and input voltage for Vout = 1.2 V.
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YV12T25
Fig. 7: Available load current vs. ambient temperature and airflow
rates for Vout = 5.0 V with Vin = 12 V, and maximum MOSFET
temperature ≤110 °C. Horizontal Orientation
(Airflow from Vin pin to GND pin.)
Fig. 8: Available load current vs. ambient temperature and airflow
rates for Vout = 3.3 V with Vin = 12 V, and maximum MOSFET
temperature ≤ 110 °C. Horizontal Orientation
(Airflow from Vin pin to GND pin.)
Fig. 9: Available load current vs. ambient temperature and airflow
rates for Vout = 1.8 V with Vin = 12 V, and maximum MOSFET
temperature ≤110 °C. Horizontal Orientation
(Airflow from Vin pin to GND pin.)
Fig. 10: Available load current vs. ambient temperature and airflow
rates for Vout = 1.2 V with Vin = 12 V, and maximum MOSFET
temperature ≤110 °C. Horizontal Orientation
(Airflow from Vin pin to GND pin.)
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YV12T25
Fig. 11: Turn-on transient for Vout = 3.3 V with the application of
SEQ/ENA signal at full rated load current (resistive) and 1 μF
external capacitance at Vin = 12 V. Top Trace:
SEQ/ENA Signal (5 V/div.);
Bottom Trace: Output Voltage (1 V/div.); Time Scale: 1 ms/div.
Fig. 13: Turn-on transient for Vout = 3.3 V with the application of
the input voltage at full rated load current (resistive) and 1 μF
external capacitance at Vin = 12 V. Top Trace:
Input Voltage Signal (5 V/div.);
Bottom Trace: Output Voltage (1 V/div.); Time Scale: 1 ms/div.
Fig. 12: Turn-on transient for Vout = 3.3 V and 5.0 V with the
application of SEQ/ENA signal at full rated load current (resistive)
and 1 μF external capacitance at Vin = 12 V. SEQ/ENA pins are tied
together. Top Trace: SEQ/ENA Signal (5 V/div.); Middle Trace:
Output Voltage of 5V POL (2V/div.); Bottom Trace: Output Voltage
of 3.3V POL (2 V/div.); Time Scale: 2 ms/div.
Fig. 14: Turn-off transient for Vout = 3.3 V and 5.0 V with the
removal of SEQ/ENA signal at full rated load current (resistive) and
1 μF external capacitance at Vin = 12 V. SEQ/ENA pins are tied
together. Top Trace: SEQ/ENA Signal (5 V/div.); Middle Trace:
Output Voltage of 5V POL (2V/div.); Bottom Trace: Output Voltage
of 3.3V POL (2 V/div.); Time Scale: 2 ms/div.
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YV12T25
Fig. 15: Output voltage ripple (20 mV/div.) at full rated load current
into a resistive load with external capacitance 1 μF ceramic and
Vin = 12 V for Vout = 3.3 V. Time Scale: 1 μs/div.
Fig. 16: Output voltage ripple (20 mV/div.) at full rated load current
into a resistive load with external capacitance 1 μF ceramic and
Vin = 12 V for Vout = 1.2 V. Time Scale: 1 μs/div.
Fig. 17: Output voltage response for Vout = 3.3 V to positive load
current step change from 12.5 A to 25 A with slew rate of 5 A/μs at
Vin = 12 V. Top Trace: Output Voltage (100 mV/div.); Bottom Trace:
Load Current (10 A/div.) Co =1 μF ceramic. Time Scale: 10 μs/div.
Fig. 18: Output voltage response for Vout = 3.3 V to negative load
current step change from 25 A to 12.5 A with slew rate of -5 A/μs
at Vin = 12 V. Top Trace: Output Voltage (100 mV/div.);
Bottom Trace: Load Current (10 A/div.) Co = 1 μF ceramic.
Time Scale: 10 μs/div.
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BCD.00690_AA
YV12T25
6. PHYSICAL INFORMATION
PAD/PIN CONNECTIONS
Pad/Pin #
Function
1
SENSE+
2
SENSE-
3
Vin
4
Ground
5
Vout
6
Vout
7
Ground
8
Ground
9
Vout
10
Vout
11
GROUND
12
Vin
13
SEQ/ENA
14
SHARE
YV12T25 Platform Notes
•
•
•
Through-hole – SIP
All dimensions are in inches [mm]
All pins are .032 x .032
Pin Material & Finish: Copper C11000 with
Matte Tin over Nickel
Tolerances:
x.xxx in. +/- .010 [x.xx mm +/- 0.25]
x.xx in. +/- .020 [x.x mm +/- 0.5]
7. ORDERING INFORMATION
PRODUCT
SERIES
INPUT
VOLTAGE
MOUNTING
SCHEME
RATED LOAD
CURRENT
YV
12
T
25
YV-Series
10 – 14 V
T SIP
Through-hole
25 A
(0.8 V to 5.5 V)
ENABLE LOGIC
–
ENVIRONMENTAL
0
G
0 Standard
(Negative Logic)
No Suffix RoHS lead-solder
exemption compliant
G RoHS lead-free solder compliant
The example above describes P/N YV12T25-0: 10 – 14 V input, through-hole (SIP), 25 A at 0.8 V to 5.5 V output, standard enable logic,
and Eutectic Tin/Lead solder. Please consult factory for the complete list of available options.
NUCLEAR AND MEDICAL APPLICATIONS - Products are not designed or intended for use as critical components in life support systems,
equipment used in hazardous environments, or nuclear control systems.
TECHNICAL REVISIONS - The appearance of products, including safety agency certifications pictured on labels, may change depending on the
date manufactured. Specifications are subject to change without notice.
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BCD.00690_AA
