LP3982-15J5F

Preliminary Datasheet LP3982 300mA,Ultra-low noise, Small Package Ultra-Fast CMOS LDO Regulator General Description The The LP3982 is designed for portable RF and wireless applications with demanding performance and space requirements. The LP3982 performance is optimized for battery-powered systems to deliver ultra low noise and low quiescent current. A noise bypass pin is available for further reduction of output noise. Regulator ground current increases only slightly in dropout, further prolonging the battery life. The LP3982 also works with low-ESR ceramic capacitors, reducing the amount of board space necessary for power applications, critical in hand-held wireless devices. The LP3982 consumes less than 0.01µA in shutdown mode and has fast turn-on time less than 50µs. The other features include ultra low dropout voltage, high output accuracy, current limiting protection, and high ripple rejection ratio. Available in the 5-lead of SC-70 packages. Features Ultra-Low-Noise for RF Application 　 2V- 6V Input Voltage Range Low Dropout : 220mV @ 300mA 　 1.2V, 1.5V, 1.8V, 2.5V, 2.8V 3.0V and 3.3V Fixed 300mA Output Current, 550A Peak Current High PSSR:-80dB at 1KHz  < 0.01uA Standby Current When Shutdown Available in SC-70-5 Package 　 TTL-Logic-Controlled Shutdown Input 　 Ultra-Fast Response in Line/Load transient 　 Current Limiting and Thermal Shutdown Protection Quick start-up (typically 50uS) Ordering Information LP3982 □□ □□ □ F: Pb-Free Package Type J5: SC-70 Output Voltage Type 15: 1.5V 18: 1.8V 25: 2.5V 28: 2.8V 30: 3.0V 33: 3.3V Applications Portable Media Players/MP3 players Cellular and Smart mobile phone LCD DSC Sensor Wireless Card Pin Configurations Typical Application Circuit SC-70(Top View) Marking Information Please see website. LP3982 – Ver. 1.0 Datasheet Dec.-2006 Page 1 of 8 Preliminary Functional Pin Description Pin Name EN BP GND VOUT VIN Pin Function Datasheet LP3982 Chip Enable (Active High). Note that this pin is high impedance. There should be a pull low 100kΩ resistor connected to GND when the control signal is floating. Reference Noise Bypass Ground Output Voltage Power Input Voltage Function Block Diagram Absolute Maximum Ratings Supply Input Voltage------------------------------------------------------------------------------------------------------6V Power Dissipation, PD @ TA = 25°C SC-70 ----------------------------------------------------------------------------------------------------400mW Package Thermal Resistance SC-70, θJA ---------------------------------------------------------------------------------------------------------------250°C/W Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------------------260°C Storage Temperature Range --------------------------------------------------------------------------------- −65°C to 150°C ESD Susceptibility HBM (Human Body Mode) -------------------------------------------------------------------------------------------2kV MM(Machine-Mode)-----------------------------------------------------------------------------------------------------200V Recommended Operating Conditions Supply Input Voltage-----------------------------------------------------------------------------------------2.5V to 5.5V EN Input Voltage -----------------------------------------------------------------------------------------------0V to 5.5V Operation Junction Temperature Range --------------------------------------------------------−40°C to 125°C Operation Ambient TemperatureRange-----------------------------------------------------------−40°C to 85°C LP3982 – Ver. 1.0 Datasheet Dec.-2006 Page 2 of 8 Preliminary Electrical Characteristics Parameter Output Voltage Accuracy Current Limit Quiescent Current Symbol ΔVOUT ILIM IQ Datasheet LP3982 (VIN = VOUT + 1V, CIN = COUT = 1µF, CBP = 22nF, TA = 25° C, unless otherwise specified) Test Conditions IOUT = 1mA RLOAD = 1Ω VEN ≥ 1.2V, IOUT = 0mA IOUT = 200mA, VOUT > Dropout Voltage VDROP 2.8V IOUT = 300mA, VOUT > 2.8V Line Regulation Load Regulation Standby Current EN Input Bias Current Logic-Low EN Threshold Voltage Logic-High Voltage Output Noise Voltage Power Supply Rejection Rate f = 100Hz f = 10kHz TSD PSRR COUT = 1µF, IOUT = 10mA VIH ΔVLINE ΔLOAD ISTBY IIBSD VIL VIN = (VOUT + 1V) to 5.5V, IOUT = 1mA 1mA < IOUT < 300mA VEN = GND, Shutdown VEN = GND or VIN VIN = 3V to 5.5V, Shutdown VIN = 3V to 5.5V, Start-Up 10Hz to 100kHz, IOUT = 200mA COUT = 1µF 1.2 100 −80 −55 165 dB °C uVRMS 0.01 0 Min −2 360 Typ -400 90 170 220 130 200 mV 300 0.3 0.6 1 100 0.4 V % % μA nA Max +2 Units % mA μA Thermal Shutdown Temperature LP3982 – Ver. 1.0 Datasheet Dec.-2006 Page 3 of 8 Preliminary Typical Operating Characteristics Datasheet LP3982 LP3982 – Ver. 1.0 Datasheet Dec.-2006 Page 4 of 8 Preliminary Datasheet LP3982 LP3982 – Ver. 1.0 Datasheet Dec.-2006 Page 5 of 8 Preliminary Datasheet Applications Information Like any low-dropout regulator, the external capacitors used with the LP3982 must be carefully selected for regulator stability and performance. Using a capacitor whose value is > 1µF on the LP3982 input and the amount of capacitance can be increased without limit. The input capacitor must be located a distance of not more than 0.5 inch from the input pin of the IC and returned to a clean analog ground. Any good quality ceramic or tantalum can be used for this capacitor. The capacitor with larger value and lower ESR (equivalent series resistance) provides better PSRR and line-transient response. The output capacitor must meet both requirements for minimum amount of capacitance and ESR in all LDOs application. The LP3982 is designed specifically to work with low ESR ceramic output capacitor in space-saving and performance consideration. Using a ceramic capacitor whose value is at least 1µF with ESR is > 25mΩ on the LP3982 output ensures stability. The LP3982 still works well with output capacitor of other types due to the wide stable ESR range. Figure 1 shows the curves of allowable ESR range as a function of load current for various output capacitor values. Output capacitor of larger capacitance can reduce noise and improve load transient response, stability, and PSRR. The output capacitor should be located not more than 0.5 inch from the VOUT pin of the LP3982 and returned to a clean analog ground. LP3982 Start-up Function Enable Function The LP3982 features an LDO regulator enable/disable function. To assure the LDO regulator will switch on, the EN turn on control level must be greater than 1.2 volts. The LDO regulator will go into the shutdown mode when the voltage on the EN pin falls below 0.4 volts. For to protecting the system, the LP3982 have a quick-discharge function. If the enable function is not needed in a specific application, it may be tied to VIN to keep the LDO regulator in a continuously on state. Bypass Capacitor and Low Noise Connecting a 22nF between the BP pin and GND pin significantly reduces noise on the regulator output, it is critical that the capacitor connection between the BP pin and GND pin be direct and PCB traces should be as short as possible. There is a relationship between the bypass capacitor value and the LDO regulator turn on time. DC leakage on this pin can affect the LDO regulator output noise and voltage regulation performance. Thermal Considerations Thermal protection limits power dissipation in LP3982. When the operation junction temperature exceeds 165°C, the OTP circuit starts the thermal shutdown function turn the pass element off. The pass element turn on again after the junction temperature cools by 30°C. For continue operation, do not exceed absolute maximum operation junction temperature 125°C. LP3982 – Ver. 1.0 Datasheet Dec.-2006 Page 6 of 8 Preliminary Datasheet The power dissipation definition in device is : PD = (VIN−VOUT) x IOUT + VIN x IQ The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula : PD(MAX) = ( TJ(MAX) − TA ) /θJA Where TJ(MAX) is the maximum operation junction temperature 125°C, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. For recommended operating conditions specification of LP3982, where TJ(MAX) is the maximum junction temperature of the die (125°C) and TA is the maximum ambient temperature. The junction to ambient thermal resistance (θJA is layout dependent) for SC-70-5 package is 250°C/W. PD(MAX) = (125°C−25°C) / 250 = 400mW (SC-70-5) PD(MAX) = (125°C−25°C) / 165 = 606mW The maximum power dissipation depends on operating ambient temperature for fixed TJ(MAX) and thermal resistance θJA. LP3982 LP3982 – Ver. 1.0 Datasheet Dec.-2006 Page 7 of 8 Preliminary Packaging Information Datasheet LP3982 LP3982 – Ver. 1.0 Datasheet Dec.-2006 Page 8 of 8