LP3987-1.8B5G

LP3987 300mA,Ultra-LowNoise Ultra-fast CMOS LDO Regrlator General Description The LP3987 is designed for portable RF and wireless applications with demanding performance and space requirements. The LP3987 performance is optimized for battery-powered systems to deliver ultra low noise and low quiescent current. A noise bypass pin is available for further reduction of output noise. Regulator ground current increases only slightly in dropout, further prolonging the battery life. The LP3987 also works with low-ESR ceramic capacitors, reducing the amount of board space necessary for power applications, critical in hand-held wireless devices. The LP3987 consumes less than 0.01µA in shutdown mode and has fast turn-on time less than 50µs. The other features include ultra low dropout voltage, high output accuracy, current limiting protection, and high ripple rejection ratio. Available in the 5-lead of SOT-23 packages. Features Ultra-Low-Noise for RF Application 2.5V- 6V Input Voltage Range Low Dropout : 220mV @ 300mA High PSSR:-80dB at 1KHz < 0.01 A Standby Current When Shutdown TTL-Logic-Controlled Shutdown Input Custom Voltage Available Ultra-Fast Response in Line/Load Transient Quick Start-Up (Typically 50 s) Current Limiting and Thermal Shutdown Protection Applications PMP/PDA/MP3 players Cellular and Mobile phone RF Module Sensor Module Pin Configurations Ordering Information LP3987 - □□ □ □□ F:PB-Free Package Type B5: SOT-23-5 B3: SOT-23 Output Voltage: SOT23-5(B5) Type: Type AB Voltage(V) 1.5 1.8 SOT23 (B3) Type: Type AB Voltage(V) 1.5 1.8 CDEH F G 2.5 2.7 2.8 2.85 3.0 3.3 CDEH 2.0 2.1 2.5 2.8 F G 3.0 3.3 SOT-23-5 SOT-23 Typical Application Circuit Note: 1. Output Voltage range from 1.5V to 3.3V; 2. 2.85V output order is LP3987-HB5F. LP3987-datasheet Oct.-2003 1-1 LP3987 Functional Pin Description Pin Name EN BP GND VOUT VIN Pin Function Chip Enable (Active High). Note that this pin is high impedance. There should be a pull low 100kΩ resistor connected to GND when the control signal is floating. Reference Noise Bypass Ground Output Voltage Power Input Voltage Function Block Diagram Absolute Maximum Ratings Supply Input Voltage-----------------------------------------------------------------------------------------------------------6V Power Dissipation, PD @ TA = 25°C SOT-23-5 --------------------------------------------------------------------------------------------------------------------400mW Package Thermal Resistance SOT-23-5, θJA -------------------------------------------------------------------------------------------------------------250°C/W Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------------260°C Storage Temperature Range --------------------------------------------------------------------------------−65°C to 150°C ESD Susceptibility HBM (Human Body Mode) ---------------------------------------------------------------------------------------------------2kV MM(Machine-Mode)-----------------------------------------------------------------------------------------------------------200V Recommended Operating Conditions Supply Input Voltage-----------------------------------------------------------------------------------------------2.5V to 5.5V EN Input Voltage ------------------------------------------------------------------------------------------------------0V to 5.5V Operation Junction Temperature Range --------------------------------------------------------------−40°C to 125°C Operation Ambient Temperature Range-----------------------------------------------------------------−40°C to 85°C LP3987-datasheet Oct.-2003 2-2 LP3987 Electrical Characteristics (VIN = VOUT + 1V, CIN = COUT = 1µF, CBP = 22nF, TA = 25° C, unless otherwise specified) Parameter Output Voltage Accuracy Current Limit Quiescent Current Dropout Voltage Line Regulation Load Regulation Standby Current EN Input Bias Current Logic-Low EN Threshold Voltage Logic-High Voltage Output Noise Voltage Power Supply f = 100Hz VIH eNO PSRR VIN = 3V to 5.5V, Start-Up 10Hz to 100kHz, IOUT = 200mA COUT = 1µF Symbol ΔVOUT ILIM IQ VDROP ΔVLINE ΔVLOAD ISTBY IIBSD VIL Test Conditions IOUT = 1mA RLOAD = 1Ω VEN ≥ 1.2V, IOUT = 0mA IOUT = 200mA, VOUT > 2.8V IOUT = 300mA, VOUT > 2.8V VIN = (VOUT + 1V) to 5.5V, IOUT = 1mA 1mA < IOUT < 300mA VEN = GND, Shutdown VEN = GND or VIN VIN = 3V to 5.5V, Shutdown Min −2 360 Typ -400 90 170 220 Max +2 Units % mA 130 200 300 0.3 0.6 μA mV % % μA nA 0.01 0 1 100 0.4 V 1.2 100 −80 μ VRMS DB Rejection Rate f= 10kHz TSD COUT = 1µF, IOUT = 10mA −55 165 Thermal Shutdown Temperature °C LP3987-datasheet Oct.-2003 3-3 LP3987 Typical Operating Characteristics LP3987-datasheet Oct.-2003 4-4 LP3987 LP3987-datasheet Oct.-2003 5-5 LP3987 Applications Information Like any low-dropout regulator, the external capacitors used with the LP3987 must be carefully selected for regulator stability and performance. Using a capacitor whose value is > 1µF on the LP3987 input and the amount of capacitance can be increased without limit. The input capacitor must be located a distance of not more than 0.5 inch from the input pin of the IC and returned to a clean analog ground. Any good quality ceramic or tantalum can be used for this capacitor. The capacitor with larger value and lower ESR (equivalent series resistance) provides better PSRR and line-transient response. The output capacitor must meet both requirements for minimum amount of capacitance and ESR in all LDOs application. The LP3987 is designed specifically to work with low ESR ceramic output capacitor in space-saving and performance consideration. Using a ceramic capacitor whose value is at least 1µF with ESR is > 25mΩ on the LP3987 output ensures stability. The LP3987 still works well with output capacitor of other types due to the wide stable ESR range. Figure 1 shows the curves of allowable ESR range as a function of load current for various output capacitor values. Output capacitor of larger capacitance can reduce noise and improve load transient response, stability, and PSRR. The output capacitor should be located not more than 0.5 inch from the VOUT pin of the LP3987 and returned to a clean analog ground. Enable Function The LP3987 features an LDO regulator enable/disable function. To assure the LDO regulator will switch on, the EN turn on control level must be greater than 1.2 volts. The LDO regulator will go into the shutdown mode when the voltage on the EN pin falls below 0.4 volts. For to protecting the system, the LP3987 have a quick-discharge function. If the enable function is not needed in a specific application, it may be tied to VIN to keep the LDO regulator in a continuously on state. Bypass Capacitor and Low Noise Connecting a 22nF between the BP pin and GND pin significantly reduces noise on the regulator output, it is critical that the capacitor connection between the BP pin and GND pin be direct and PCB traces should be as short as possible. There is a relationship between the bypass capacitor value and the LDO regulator turn on time. DC leakage on this pin can affect the LDO regulator output noise and voltage regulation performance. Start-up Function Thermal Considerations Thermal protection limits power dissipation in LP3987. When the operation junction temperature exceeds 165°C, the OTP circuit starts the thermal shutdown function turn the pass element off. The pass element turn on again after the junction temperature cools by 30°C. For continue operation, do not exceed absolute LP3987-datasheet Oct.-2003 6-6 LP3987 maximum operation junction temperature 125°C. The power dissipation definition in device is : PD = (VIN−VOUT) x IOUT + VIN x IQ The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula : PD(MAX) = ( TJ(MAX) − TA ) /θJA Where TJ(MAX) is the maximum operation junction temperature 125°C, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. For recommended operating conditions specification of LP3987, where TJ(MAX) is the maximum junction temperature of the die (125°C) and TA is the maximum ambient temperature. The junction to ambient thermal resistance (θJA is layout dependent) for SOT-23-5 package is 250°C/W. PD(MAX) = (125°C−25°C) / 250 = 400mW (SOT-23-5) PD(MAX) = (125°C−25°C) / 165 = 606mW The maximum power dissipation depends on operating ambient temperature for fixed TJ(MAX) and thermal resistance θJA. LP3987-datasheet Oct.-2003 7-7 LP3987 Package Information LP3987-datasheet Oct.-2003 8-8