CAPZero Family
Zero1 Loss Automatic X Capacitor Discharge IC
Product Highlights
R1
• Blocks current through X capacitor discharge resistors when AC
•
•
•
•
•
•
•
voltage is connected
Automatically discharges X capacitors through discharge resistors
when AC is disconnected
Simplifies EMI filter design – larger X capacitor allows smaller
inductive components with no change in consumption
Only two terminals – meets safety standards for use before or after
system input fuse
>4 mm creepage on package and PCB
Self supplied – no external bias required
High common mode surge immunity – no external ground
connection
High differential surge withstand – 1000 V internal MOSFETs
EcoSmart™ – Energy Efficient
D1
AC
X Capacitor
CAPZero
MOV
and Other
EMI Filter
Components
D2
R2
PI-6599-110711
Figure 1. Typical Application – Not a Simplified Circuit.
• 100 nF
Appliances requiring EuP Lot 6 compliance
Adapters requiring ultra low no-load consumption
All converters requiring very low standby power
Description
When AC voltage is applied, CAPZero™ blocks current flow in the X
capacitor safety discharge resistors, reducing the power loss to less
than 5 mW, or essentially zero1 at 230 VAC. When AC voltage is
disconnected, CAPZero automatically discharges the X capacitor by
connecting the series discharge resistors. This operation allows total
flexibility in the choice of the X capacitor to optimize differential mode
EMI filtering and reduce inductor costs, with no change in power
consumption.
Designing with CAPZero is simply a matter of selecting the appropriate
CAPZero device and external resistor values in Table 1 for the
X capacitor value being used. This design choice will provide a worst
case RC time constant, when the AC supply is disconnected, of less
than 1 second as required by international safety standards.
Component Selection Table
Product4
BVDSS
CAP002DG
825 V
CAP012DG
1000 V
CAP003DG
825 V
CAP013DG
1000 V
CAP004DG
825 V
CAP014DG
1000 V
CAP005DG
825 V
CAP015DG
1000 V
CAP006DG
825 V
CAP016DG
1000 V
CAP007DG
825 V
CAP017DG
1000 V
The simplicity and ruggedness of the two terminal CAPZero IC makes it
an ideal choice in systems designed to meet EuP Lot 6 requirements.
CAP008DG
825 V
CAP018DG
1000 V
The CAPZero family has two voltage grades: 825 V and 1000 V. The
voltage rating required depends on surge requirement and circuit
configuration of the application. See Key Applications Considerations
section for details.
CAP009DG
825 V
CAP019DG
1000 V
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Maximum Total
X Capacitance
Total Series
Resistance2
(R1 + R2)
≤500 nF
1.5 MW
750 nF
1.02 MW
1 mF
780 kW
1.5 mF
480 kW
2 mF
360 kW
2.5 mF
300 kW
3.5 mF
200 kW
5 mF
150 kW3
Table 1. Component Selection Table.
Notes:
1. IEC 62301 clause 4.5 rounds standby power use below 5 mW to zero.
2. Values are nominal. RC time constant is 1.5 kV it is recommended that the MOV is
always placed in the location shown in Figure 3 as MOVPOS1.
The pin configuration of Figure 2 ensures that the width of the SO-8
package is used to provide creepage and clearance distance of over
4 mm.
Although electrical connections are only made to pins 2, 3, 6 and 7, it
is recommended that pins 1-4 and pins 5-8 are coupled together on
the PCB – see Applications Section.
D Package (SO-8)
NC
D1
D1
NC
1
8
2
7
3
6
4
5
NC
It is always recommended that the peak voltage between terminals
D1 and D2 of CAPZero is measured during surge tests in the final
system. Measurements of peak voltage across CAPZero during surge
tests should be made with oscilloscope probes having appropriate
voltage rating and using an isolated supply to the oscilloscope to
avoid ground currents influencing measurement results. When
making such measurements, it is recommended that 50 V engineering margin is allowed below the breakdown voltage specification (for
example 950 V with the 1000 V CAPZero).
If the measured peak Drain voltage exceeds 950 V, an external 1 kV
ceramic capacitor can be placed between D1 and D2 terminals to
attenuate the voltage applied between the CAPZero terminals during
surge. Please refer to the Application Note AN-48 for the details.
This optional external capacitor placement is shown as CEXT in Figure
3. It should be noted that use of an external capacitor in this way will
increase power consumption slightly due to the CEXT charge/discharge
currents flowing in R1 and R2 while AC is connected.
D2
D2
NC
PI-5608-060810
Figure 2. Pin Configuration.
Key Application Considerations
Breakdown Voltage Selection
Figure 3 illustrates possible system configurations influencing the
choice of CAPZero breakdown voltage. The system configuration
variables include the placement of the system MOV and X capacitor(s)
as well as the differential surge voltage specifications of the
application.
As shown in Table 1, each device in the CAPZero family has a 825 V
or 1000 V option. For applications where the system MOV is placed
in position 1 (MOVPOS1 in Figure 3), the 825 V option will typically
provide adequate voltage withstand for surge requirements up to 3 kV
or more. The 1 kV CAPZero would be recommended for higher surge
requirements or if additional voltage margin is required.
PCB Layout and External Resistor Selection
Figure 4 shows a typical PCB layout configuration for CAPZero. The
external resistors in this case are divided into two separate surface
mount resistors to distribute loss under fault conditions – for example
where a short-circuit exists between CAPZero terminals D1 and D2.
R1 and R2 values are selected according to Table 1.
Under a fault condition where CAPZero terminals D1 and D2 are
shorted together, each resistor will dissipate a power that can be
calculated from the applied AC voltage and the R1 and R2 values. For
example in an application using CAP004 or CAP014, R1=R2=390 kW.
If CAPZero is shorted out at 265 VAC R1 and R2 will each dissipate
45 mW.
Resistors R1 and R2 should also be rated for 50% of the system input
voltage again to allow for the short-circuitry of CAPZero D1 to D2 pins
during single point fault testing.
R1
D1
MOVPOS1
AC
MOVPOS2
Other EMI
Filter
Components
CEXT
X Capacitor1
X Capacitor2
D2
CAPZero
R2
PI-6600-110711
Figure 3. Placement Options of MOV and CEXT.
2
Rev. H 03/18
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CAPZero
If lower dissipation or lower voltage across each resistor is required
during fault tests, the total external resistance can be divided into
more discrete resistors, however the total resistance must be equal to
that specified in Table 1.
Safety
CAPZero meets safety requirements even if placed before the system
input fuse. If a short-circuit is placed between D1 and D2 terminals
of CAPZero, the system is identical to existing systems where
CAPZero is not used.
With regard to open circuit tests, it is not possible to create a fault
condition through a single pin fault (for example lifted pin test) since
there are two pins connected to each of D1 and D2. If several pins
are lifted to create an open circuit, the condition is identical to an
open circuit X capacitor discharge resistor in existing systems where
CAPZero is not used. If redundancy against open circuit faults is
required, two CAPZero and R1 / R2 configurations can be placed in
parallel.
Discharge Operation
To meet the safety regulations, when the AC supply is disconnected,
CAPZero will discharge the X capacitor to the safety extra low voltage
(SELV) levels according to the above functional description. Although
there are no specific safety requirements below SELV, CAPZero still
continues the discharge until the X capacitor is fully discharged. As
such CAPZero can be safely used at low input voltages such as the
common industrial 18 VAC and 24 VAC supply rails while retaining X
capacitor discharge when the AC source is disconnected.
X Capacitor
R1
R2
≥4 mm
PI-5610-041310
Figure 4. Typical PCB Layout.
3
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Rev. H 03/18
CAPZero
Absolute Maximum Ratings(4)
DRAIN Pin Voltage(1) CAP002-CAP009 ..............................825 V
CAP012-CAP019 .............................1000 V
DRAIN Peak Current(2) CAP002/CAP012............................ 0.553 mA
CAP003/CAP013............................ 0.784 mA
CAP004/CAP014............................ 1.026 mA
CAP005/CAP015............................ 1.667 mA
CAP006/CAP016............................2.222 mA
CAP007/CAP017............................. 2.667 mA
CAP008/CAP018............................4.000 mA
CAP009/CAP019............................ 5.333 mA
Storage Temperature...............................................-65 °C to 150 °C
Lead Temperature(3)............................................................... 260 °C
Operating Ambient Temperature .............................. -10 °C to 105 °C
Maximum Junction Temperature .............................. -10 °C to 110 °C
Notes:
1. Voltage of D1 pin relative to D2 pin in either polarity.
2. The peak DRAIN current is allowed while the DRAIN voltage is
simultaneously less than 400 V.
3. 1/16 in. from case for 5 seconds.
4. The Absolute Maximum Ratings specified may be applied one at
a time without causing permanent damage to the product.
Exposure to Absolute Maximum Rating conditions for extended
periods of time may affect product reliability.
Thermal Resistance
Thermal Resistance: D Package1:
(qJA)..................160 °C/W (Single layer JEDEC PCB)
(qJC)...........................................40 °C/W (Bottom)
(qJC)................................................ 75 °C/W (Top)
Parameter
Notes:
1. Reference thermal resistance test conditions: JEDEC
JESD51-3, SEMI Test Method #G43-87, and MIL-STD-883
Method 10121.1.
Symbol
Conditions
TA = -10 to 105 °C
(Unless Otherwise Specified)
tDETECT
Line Cycle Frequency 47-63 Hz
Min
Typ
Max
Units
22
31.4
ms
Control Functions
AC Removal
Detection Time
Drain Saturation
Current A,B
Supply Current
IDSAT
ISUPPLY
CAP002/012
0.25
CAP003/013
0.37
CAP004/014
0.48
CAP005/015
0.78
CAP006/016
1.04
CAP007/017
1.25
CAP008/018
1.88
CAP009/019
2.5
TA = 25 °C
mA
21.7
mA
Notes:
A. Saturation current specifications ensure a natural RC discharge characteristic at all voltages up to 265 VAC pk with the external resistor
values specified in Component Selection Table 1.
B. Specifications are guaranteed by characterization and design.
4
Rev. H 03/18
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CAPZero
Typical Performance Characteristics
PI-6020-062110
1.20
1.10
ISUPPLY (Normalized to 25 °C)
1.00
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
-25
0
25
50
75
100
125
Temperature (°C)
Figure 5. ISUPPLY vs. Temperature.
5
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Rev. H 03/18
CAPZero
SO-8 (D Package)
4
B
0.10 (0.004) C A-B 2X
2
DETAIL A
4.90 (0.193) BSC
A
4
8
D
5
2 3.90 (0.154) BSC
GAUGE
PLANE
SEATING
PLANE
6.00 (0.236) BSC
C
0-8
1.04 (0.041) REF
0.10 (0.004) C D
2X
1
Pin 1 ID
4
0.25 (0.010)
BSC
0.40 (0.016)
1.27 (0.050)
0.20 (0.008) C
2X
7X 0.31 - 0.51 (0.012 - 0.020)
0.25 (0.010) M C A-B D
1.27 (0.050) BSC
1.25 - 1.65
(0.049 - 0.065)
1.35 (0.053)
1.75 (0.069)
o
DETAIL A
0.10 (0.004)
0.25 (0.010)
0.10 (0.004) C
H
7X
SEATING PLANE
0.17 (0.007)
0.25 (0.010)
C
Reference
Solder Pad
Dimensions
+
1.45 (0.057) 4.00 (0.157)
+
D08A
+
5.45 (0.215)
+
1.27 (0.050)
Notes:
1. JEDEC reference: MS-012.
2. Package outline exclusive of mold flash and metal burr.
3. Package outline inclusive of plating thickness.
4. Datums A and B to be determined at datum plane H.
5. Controlling dimensions are in millimeters. Inch dimensions
are shown in parenthesis. Angles in degrees.
0.60 (0.024)
PI-5615-041210
Part Ordering Information
• CAPZero Product Family
• 002 Series Number
• Package Identifier
D
Plastic SO-8
• Package Material
G
GREEN: Halogen Free and RoHS Compliant
• Tape & Reel and Other Options
CAP 002 D G - TL
Blank
Standard Configurations
TL
Tape & Reel, 2.5 k pcs.
6
Rev. H 03/18
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CAPZero
Revision Notes
Date
A
Code A release.
04/14/10
B
Updated ISUPPLY condition. Added figure 5. Parameter TDETECT was updated.
06/08/10
C
Updated Table 1. Updated Note 1 in Table 1. Added “Discharge Operation” paragraph. Updated Absolute Maximum
Ratings Table.
02/11
C
Added Maximum Junction Temperature specification.
04/11
D
Updated Figures 1 and 3.
E
Added RDS(ON) max. at 105 °C for CAPZero parts.
11/07/11
E
Added Thermal Resistance section.
F
Updated with new Brand Style.
05/15
G
Removed RDS(ON) information.
07/15
H
Added Note 3 in Table 1. Updated text on page 2, 3rd paragraph right column.
03/18
03/12
09/16/13
7
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Rev. H 03/18
For the latest updates, visit our website: www.power.com
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does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY
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The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one
or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of
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