CHY103DG

CHY103 ChiPhy™ Family Charger Interface Physical Layer IC with Complete System Level Protection Product Highlights VOUT • Supports Quick Charge 3.0 Class A and Class B specification D+ D- • Adaptive output overvoltage protection (AOVP) GND • Secondary over-temperature protection (SOTP) • Output soft short-circuit protection (OSSP) • Remote shutdown protection (RESP) • Enables Powered Device to shutdown adapter • Selectable hysteretic or latching shutdown BP • Power consumption below 1 mW at 5 V output • Supports InnoSwitch™, TinySwitch™, and TOPSwitch™ Typical Applications • Battery chargers for smart phones, tablets, netbooks, FBD Voltage Feedback Network TM D+ CHY103 U1 FA/P digital cameras, and bluetooth accessories • USB power output ports such as battery banks or car chargers R GND Fault Handling Circuit Description CHY103 is a USB mobile device charger interface IC which implements the Qualcomm’s Quick Charge 3.0 specification for adaptive voltage battery charging. It incorporates all necessary functions to add Quick Charge 3.0 capability to circuits incorporating Power Integrations’ switcher ICs such as InnoSwitch, TinySwitch, TOPSwitch and other charger solutions employing traditional secondary-side feedback schemes. D- PI-7612-091015 Figure 1. Typical Application Schematic. CHY103 supports the full output voltage range of Quick Charge 3.0, including 200 mV micro-stepped voltage levels from 3.6 V to 12 V (Class A) and up to 20 V (Class B). CHY103 provides a suite of system level protection features protecting the power supply and connected Powered Device (PD) from excessive output voltages, secondary-side thermal overload, and faulty power delivery while adapter is unplugged. Additionally it allows the PD to remotely shutdown the power supply through USB data lines. The shutdown type can be configured as either hysteretic or latching. CHY103 automatically detects whether a connected PD is Quick Charge 3.0 or Quick Charge 2.0 capable before enabling output voltage adjustment. If a PD that is not compliant to Quick Charge 2.0 or 3.0 is detected, the CHY103 disables output voltage adjustment to ensure safe operation with legacy 5 V only USB PDs. Figure 2. SO-8 (D Package). www.power.com June 2016 This Product is Covered by Patents and/or Pending Patent Applications. CHY103 BYPASS (BP) + 2.65 V 6V REFERENCE (R) CLASS A/B SELECT BANDGAP FEEDBACK DRIVE (FBD) + + 2V VTH(OV) IT(UP) + 0.325 V IT(DO) TEMPERATURE MONITOR (TM) 1.26 V + CONTROL LOGIC (LOOKUP TABLE, TIMER, FAULTS) S SET Q R CLR Q 900 kΩ N1 D- 150 µA 100 µA D+ + 0.325 V FAULT MONITOR/ PROTECTION MODE (FA/P) 19.53 kΩ + + 2V 0.325 V 1V GROUND (GND) N2 PI-7611-090415 Figure 3. Functional Block Diagram. Pin Functional Description TEMPERATURE MONITOR (TM) Pin: Connection point for optional external temperature sensor (NTC resistor). DATA LINE (D+) Pin: USB D+ data line input. DATA LINE (D-): Pin: USB D- data line input. FAULT MONITOR/PROTECTION MODE (FA/P) Pin: Protection mode output driving external shutdown circuitry in case a fault is detected. Optional monitor input for faulty power delivery while output cable is unplugged. GROUND (GND) Pin: Ground. FEEDBACK DRIVE (FBD) Pin: Feedback loop drive output connected to reference input of external power supply error amplifier to set output voltage. Monitors output voltage through voltage divider connected to output rail. BYPASS (BP) Pin: Connection point for an external bypass capacitor for the internally generated supply voltage. REFERENCE (R) Pin: Connected to internal band-gap reference. Provides reference current and output voltage range selection (Class A or Class B) through connected resistor. D Package (SO-8) TM FA/P GND FBD 1 8 2 7 3 6 4 5 BP R D+ D- PI-7610-040615 Figure 4. Pin Configuration. 2 Rev. G 06/16 www.power.com CHY103 Functional Description gap reference and provides an accurate reference current for internal timing circuits. Resistor RREF is furthermore used to select the output voltage range. RREF = 38.3 kΩ ±1% selects Class A (12 V maximum output voltage) and RREF = 12.4 kΩ ±1% selects Class B (20 V maximum output voltage). CHY103 is a USB high-voltage dedicated charging port (HVDCP) interface IC for the Quick Charge 3.0 specification. It incorporates all necessary functions to add Quick Charge 3.0 capability to Power Integrations’ switcher ICs such as InnoSwitch, TinySwitch, and TOPSwitch. Quick Charge 3.0 Interface At power-up CHY103 turns on switch N1 (see Figure 3) short-circuiting USB data lines D+ and D- for the initial handshake between AC-DC adapter (DCP) and powered device (PD) as described in the USB Battery Charging specification revision 1.2. After the USB BC 1.2 handshake is completed, CHY103 will turn off switch N1 if it detects a Quick Charge 3.0 or Quick Charge 2.0 compliant PD. At this point the Quick Charge 2.0 handshake followed by the Quick Charge 3.0 handshake can take place as described in the Quick Charge 2.0 and Quick Charge 3.0 protocol specification. Upon completion of the Quick Charge 2.0 and Quick Charge 3.0 handshakes, CHY103 will turn on switch N2 (see Figure 3) connecting a 19.53 kΩ pull-down resistor to USB data line D-. CHY103 also supports other solutions with traditional secondary-side feedback schemes such as TL431 for instance. Figure 5 depicts CHY103 interfacing with Power Integrations’ InnoSwitch switcher IC in a configuration with hysteretic power supply shutdown, secondary thermal protection, and faulty power delivery protection when USB cable is unplugged. CHY103 supports the full output range of Quick Charge 3.0 Class A (3.6 V to 12 V) or Class B (3.6 V to 20 V) and its subset Quick Charge 2.0 Class A (5 V, 9 V, or 12 V) or Class B (5 V, 9 V, 12 V, and 20 V). It automatically detects either Quick Charge 3.0 or Quick Charge 2.0 capable powered devices (PD) or legacy PDs compliant with USB Battery Charging Specification revision 1.2 and only enables output voltage adjustments accordingly. Table 1 summarizes the output voltage lookup and model select table and corresponding AC-DC adapter output voltages. Shunt Regulator The internal shunt regulator clamps the BYPASS pin at 6 V when current is provided through an external resistor (RBP in Figure 5). This facilitates powering CHY103 externally over a wide output voltage range of 3.6 V to 20 V. Recommended values are RBP = 2.21 kΩ ±1% and CBP = 470 nF. Portable Device (PD) BYPASS Pin Undervoltage The BYPASS pin undervoltage circuitry resets the CHY103 when the BYPASS pin voltage drops below 2.9 V. Once the BYPASS pin voltage drops below 2.9 V it must rise back to 3.1 V to commence correct operation. Reference and Output Voltage Range Selection Input Resistor RREF at the REFERENCE pin is connected to an internal band CHY103 D+ D- Power Supply Output Note 0.6 V 0.6 V 12 V Class A 3.3 V 0.6 V 9V Class A 0.6 V 3.3 V Continuous Mode Class A/B with ±0.2 V step size 3.3 V 3.3 V 20 V Class B 0.6 V GND 5V Default mode Table 1. Quick Charge 3.0 Output Voltage Lookup and Mode Select Table. B+ VOUT R11 D+ R1 C1 D- C11 GND Q1 D11 CFR RFR R4 R6 RBP T1 CBPS GND BPS VO SR/P D C10 InnoSwitch U1 RNTC -t R3 D10 FWD R10 CONTROL CBP O Q2 R2 D1 Q1 FB BP FBD S BPP IS TM D+ ChiPhy U2 FA/P DR CBPP GND RREF PI-7692-091815 Figure 5. CHY103 with Power Integrations InnoSwitch Switcher IC with Hysteretic Fault Shutdown Protection. 3 www.power.com Rev. G 06/16 CHY103 VOUT VOUT + VTH(OV) R1 FB ST(DO) FBD + FA/P Logic tD(OV) VTH(OV) R1 IT(DO) BP R3 ST(UP) IT(DO) ST(DO) FBD BP FA/P Logic tD(OV) ST(UP) FB R2 IT(UP) IT(UP) R2 GND GND PI-7694-081915 PI-7693-081915 Figure 6. CHY103 FEEDBACK Pin Drive Output and Overvoltage Monitor Input. Figure 7. CHY103 interface with control loop reference voltages 10 V) so as to minimize no-load input power at these voltages. Diodes D7 and D8 should be used at the output terminal, to offer ESD protection for D+ and D- pins. InnoSwitch FEEDBACK Pin It is recommended to use a 1 nF capacitor for the InnoSwitch IC FEEDBACK pin decoupling capacitor. The feedback divider network R8 and R11 must be 100 kW ±1% and 34 kW ±1% respectively for the CHY103 IC to have a fixed step size of 200 mV. Resistor R9 and capacitor C12 form a phase lead (feed-forward) network that ensures stable operation and minimizes output voltage overshoot and undershoot during transient load conditions. This phase lead network prevents pulse bunching. Recommended values are R9 = 1 kW and C12 = 1000 pF. Fault Protection Fault protection by primary-side latching shutdown can be achieved by using an optocoupler U3 as shown in Figure 8. This circuit should be designed such that the InnoSwitch PRIMARY BYPASS pin current should be more than at least 9.6 mA (i.e. the PRIMARY BYPASS pin 8 Rev. G 06/16 www.power.com CHY103 shutdown threshold current of the InnoSwitch IC) at the time as per to InnoSwitch-IC data sheet when the optocoupler conducts. If the optocoupler transistor current is such that the primary bypass current does not exceed the PRIMARY BYPASS pin shutdown threshold current value, then even though CHY103 IC’s protection feature would work (CHY103 IC FAULT MONITOR/PROTECTION MODE pin goes high), the power supply would not latch off to protect the device from any damage. switching for a time equal to tAR(SK) (as per to InnoSwitch data sheet), auto-restart of the InnoSwitch IC will follow. This process will repeat until the fault condition is removed. Layout Design Considerations Alternatively a non-latching protection scheme can be implemented as described in the Protection Mode section of the data sheet (Figure 5). With the circuit proposed in Figure 5, during a fault condition (CHY103 IC FAULT MONITOR/PROTECTION MODE pin goes high), the InnoSwitch-IC FEEDBACK pin voltage will be raised above the maximum VFB value (=1.28 V as per the InnoSwitch data sheet), which causes the InnoSwitch IC to stop switching. Once the InnoSwitch IC has stopped R18 for providing bias supply to the IC should be placed as close to the IC as possible and should be routed with short traces. • The FEEDBACK DRIVE pin of CHY103 is connected to the FEEDBACK pin of InnoSwitch and hence a close placement of the two ICs is recommended. • It is also recommended to place capacitor C16 close to the CHY103 IC. • The decoupling capacitor C17 must be located directly adjacent to the BYPASS pin and should be routed with short traces. • Resistors R19 for providing reference current to the IC and resistor REFERENCE pin resistor R19 and BYPASS pin resistor R18 should be close to the CHY103 IC and routed with short traces BYPASS pin decoupling capacitor C17 must be close to the CHY103 IC PCB – Bottom Side PCB – Top Side PI-7701-090415 Figure 14. PCB Layout Design. 9 www.power.com Rev. G 06/16 CHY103 Absolute Maximum Ratings3 BYPASS Pin Voltage ....................................................... -0.3 to 9 V REFERENCE Pin Voltage .................................................. -0.3 to 9 V TM/FA/P/FBD Pin Voltage ................................................ -0.3 to 9 V D+/D- Pin Voltage ....................................................... -0.3 to 6.5 V BYPASS Pin Current ...............................................................25 mA D+/D- Pin Current .................................................................. 1 mA1 Operating Junction Temperature............................ -40 °C to +150 °C Operating Ambient Temperature............................ -40 °C to +105 °C Storage Temperature...............................................-65 °C to 150 °C Parameter Symbol Lead Temperature2................................................................ 260 °C Notes: 1. Per USB BC 1.2 and HVDCP specifications. 2. 1/16 in. from case for 5 seconds. 3. The Absolute Maximum Ratings specified may be applied one at a time without causing permanent damage to the product. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect product reliability. Conditions SOURCE = 0 V; TJ = -20 °C to +85 °C (Unless Otherwise Specified) Min Typ Max Units TJ = +25 °C 3.1 4.3 6.3 V 2.7 2.9 3.1 V 200 µA V Supply and Reference Function BYPASS Pin Voltage Power-Up Reset Threshold Voltage VBP VBP(RESET) BYPASS Pin Source Current IBPSC VBP = 4.3 V, RREF = 38.3 k W, TJ = 25 °C BYPASS Pin Shunt Voltage VBP(SHUNT) IBP = 8 mA 5.7 6 6.3 RREF = 38.3 kW Class A 0.350 0.383 0.395 RREF = 12.4 kW Class B 0.350 0.372 0.400 REFERENCE Pin Voltage VR V Data Line D+ and D- Functions (HVDCP Interface) Data Detect Voltage VDAT(REF) 0.250 0.325 0.400 V Output Voltage Selection Reference VSEL(REF) 1.8 2 2.2 V Data Lines Short-Circuit Delay TDAT(SHORT) 10 20 ms D+ High Glitch Filter Time TGLITCH(BC) 1500 ms D- Low Glitch Filter Time TGLITCH(DM) Output Voltage Glitch Filter Time TGLITCH(V) Continuous Mode Glitch Filter Time TGLITCH(CONT) VOUT ≥ 0.8 V 1000 DONE 1 ms LOW 20 40 60 ms 200 µs CHANGE 100 CHANGE VBP = 3.1-6.3 V, VD+ = 0.5-3.6 V Switch N1 is Off D+ Leakage Resistance RDAT(LKG) D- Pull-Down Resistance RDM(DWN) Switch N1 On-Resistance RDS(ON)N1 VBP = 4.3 V, VD+ ≤ 3.6 V, IDRAIN = 200 mA Data Line Capacitance CDCP(PWR) See Note A 300 900 1500 kΩ 14.25 19.53 24.5 kΩ 17 25 Ω 1 nF 10 Rev. G 06/16 www.power.com CHY103 Parameter Symbol Conditions SOURCE = 0 V; TJ = -20 °C to +85 °C (Unless Otherwise Specified) Min Typ Max Units FEEDBACK Pin Drive Functions Toggle Up Current Source Step ∆IT(UP) 1.737 1.930 2.123 mA Toggle Down Current Source Step ∆IT(DO) 1.737 1.930 2.123 mA IT(UP) = 0 (5 V) 1.44 1.52 1.60 IT(UP) = 40 mA (9 V) 1.60 1.72 1.84 IT(UP) = 70 mA (12 V) 1.74 1.87 2.00 IT(UP) = 150 mA (20 V) 2.12 2.28 2.44 RREF = 38.3 k W 1.74 1.87 2.00 RREF = 12.4 k W 2.12 2.28 2.44 Protection Functions QC 2.0 Mode Class A / Class B Output Overvoltage Threshold V TH(OV) QC 3.0 Continuous Mode Class A Class B Output OV Detection Delay Time tD(OV) Output OV Detection Blanking Time tB(OV) 500 Output Socket Fault Detection Threshold V TH(FA) 0.250 Socket Fault Detection Delay Time tD(FA) FA/P Pin Clamp Voltage VCL 50 ICLAMP = 100 mA V ms ms 0.325 0.400 V 40 ms 1 V Over-Temperature Detection Threshold V TH(TM) Over-Temperature Detection Delay Time tD(TM) 1 ms Temperature Monitor Current Source ITM 100 mA Temperature Monitor Current On-Time tON(ITM) 12 ms Temperature Monitor Current Duty Ratio DITM 1 % Protection Mode Current Source IP 1.12 100 1.20 150 1.28 200 V mA NOTES: A. Guaranteed by design. Not tested in production. 11 www.power.com Rev. G 06/16 CHY103 SO-8 (D Package) 4 B 0.10 (0.004) C A-B 2X 2 DETAIL A 4.90 (0.193) BSC A 4 8 D 5 2 3.90 (0.154) BSC GAUGE PLANE SEATING PLANE 6.00 (0.236) BSC 0-8 C 1.04 (0.041) REF 2X 0.10 (0.004) C D Pin 1 ID 1 4 0.25 (0.010) BSC 0.40 (0.016) 1.27 (0.050) 0.20 (0.008) C 2X 7X 0.31 - 0.51 (0.012 - 0.020) 0.25 (0.010) M C A-B D 1.27 (0.050) BSC 1.25 - 1.65 (0.049 - 0.065) 1.35 (0.053) 1.75 (0.069) o DETAIL A 0.10 (0.004) 0.25 (0.010) 0.10 (0.004) C H 7X SEATING PLANE C Reference Solder Pad Dimensions + 1.45 (0.057) 4.00 (0.157) 5.45 (0.215) + D08A 0.17 (0.007) 0.25 (0.010) 1.27 (0.050) + + 0.60 (0.024) Notes: 1. JEDEC reference: MS-012. 2. Package outline exclusive of mold flash and metal burr. 3. Package outline inclusive of plating thickness. 4. Datums A and B to be determined at datum plane H. 5. Controlling dimensions are in millimeters. Inch dimensions are shown in parenthesis. Angles in degrees. PI-5615-020515 12 Rev. G 06/16 www.power.com CHY103 PACKAGE MARKING SO-8 Package Marking B A A. B. C. D. 1535 CHY103D 4K857B D C Power Integrations Registered Trademark Assembly Date Code (last two digits of year followed by 2-digit work week) Product Identification (Part #/Package Type) Lot Identification Code PI-7788-111115 13 www.power.com Rev. G 06/16 CHY103 MSL Table Part Number MSL Rating CHY103DG 1 ESD and Latch-Up Table Test Conditions Results Latch-up at 125 °C JESD78D Human Body Model ESD ANSI/ESDA/JEDEC JS-001-2014 > ±2000 V on all pins Machine Model ESD JESD22-A115C > ±200 V on all pins > ±100 mA or > 1.5 V (max) on all pins Part Ordering Information • ChiPhy Product Family • 103 Series Number • Package Identifier D SO-8 • Tape & Reel and Other Options CHY 103 D - TL TL Tape & Reel, 2.5 k pcs 14 Rev. G 06/16 www.power.com CHY103 Notes 15 www.power.com Rev. G 06/16 Revision Notes Date B Code A data sheet. C Schematic error corrections made to Figures 5, 8 and 13. 09/18/15 09/15 D Updated VR values. 9/23/15 E Made correction to Figure 13, and updated ∆IT(UP) and ∆IT(DO) parameter limits. Added MSL, ESD and Latch-up tables, added Package Marking. 11/11/15 F Updated text on page 7 in Remote Shutdown section and page 8 in D+/D- Short to VO Protection Circuit and Primary BYPASS Pin sections. 12/02/15 G Updated D+/D- Pin Voltage in Abs Max Ratings section, VBP(RESET) and RDS(ON)N1 parameters per PCN-16241. 06/16 For the latest updates, visit our website: www.power.com Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. Patent Information The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set forth at http://www.power.com/ip.htm. Life Support Policy POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein: 1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or death to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. The PI logo, TOPSwitch, TinySwitch, SENZero, SCALE-iDriver, Qspeed, PeakSwitch, LYTSwitch, LinkZero, LinkSwitch, InnoSwitch, HiperTFS, HiperPFS, HiperLCS, DPA-Switch, CAPZero, Clampless, EcoSmart, E-Shield, Filterfuse, FluxLink, StakFET, PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©2016, Power Integrations, Inc. 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