ClampZero Family
Active Clamp IC with Integrated High-Voltage Switch
Pairs with InnoSwitch4 Family of Offline Switcher ICs
Product Highlights
ClampZero
Highly Integrated, Compact Footprint
D
S2
HS
BP2
High-Voltage
DC Input
IN
LS
S1
Eliminates switching losses in InnoSwitch4 primary switch
Captures and recycles leakage inductance energy
Dramatically improves power supply efficiency
Interfaces seamlessly with InnoSwitch4
Powered directly from InnoSwitch4 BYPASS pin
Self-biased at start-up
Operates in both DCM and CCM modes
Robust 750 V PowiGaN switch (CPZ1075M / CPZ1076M)
BP1
•
•
•
•
•
•
•
•
Advanced Protection / Safety Features
• Integrated temperature sensing and hysteretic thermal shutdown
InnoSwitch4-CZ
Green Package
PI-90
• Halogen free and RoHS compliant
Applications
• High density flyback designs up to 220 W
Figure 1. Typical Application schematic.
Description
The ClampZero™ IC pairs with the InnoSwitch™4 family of ICs to
eliminate energy wasted due to switching losses in the clamp and
primary switch. This dramatically improves power supply efficiency –
easily exceeding 95% - while maintaining the flexibility and low
component count of the flyback architecture.
The ClampZero IC is an active clamping circuit which recycles
otherwise wasted leakage inductance energy. The ClampZero
incorporates a high-side power switch and level shifted self-biased
controller which receives communication from a low-side transceiver
connected to the InnoSwitch4 primary controller
By ensuring zero voltage switching across all line and load conditions
and in both CCM and DCM operating modes, ClampZero combines with
InnoSwitch4 to implement a highly flexible active clamp flyback
solution. In a typical application paired with the InnoSwitch4 IC, the
low switching losses permit use of a high switching frequency,
minimizing the physical size of the transformer and resulting in an
extremely small PCB footprint.
Zero-voltage switching is achieved by precise timing between the
turn-off of the ClampZero and turn-on of the InnoSwitch4 power
switch, which completely removes turn-on losses. The overall effect of
this synchronized switching, along with the InnoSwitch4 PowiGaN
switch with zero turn-off losses, is a flyback converter with zero
primary clamp losses and zero power switch switching losses enabling
high density, heat sinkless flyback designs up to 220 W.
Figure 2. MinSOP-16A Package with Creepage for High-Side Driver.
ClampZero + InnoSwitch4 Output Power Table
Product 3,4
Adapter1
Open Frame2
CPZ1061M
70 W
75 W
CPZ1062M
90 W
100 W
CPZ1075M
135 W
145 W
CPZ1076M
200 W
220 W
Table 1. Output Power Table.
Notes:
1. Minimum continuous power in a typical non-ventilated enclosed typical size
adapter measured at 40 °C ambient. Max output power is dependent on the
design. With condition that package temperature must be < 125 °C.
2. Minimum peak power capability.
3. Package: MinSOP-16A.
4. CPZ1061M / CPZ1062M ‒ 650 V MOSFET.
CPZ1075M / CPZ1076M ‒ 750 V PowiGaN Switch.
www.power.com
July 2022
This Product is Covered by Patents and/or Pending Patent Applications.
ClampZero
DRAIN
(D)
PRIMARY BYPASS
(BP2)
REGULATOR
BP2/UV
BP2 PIN
UNDERVOLTAGE
+
VBP2
VBP2 – VBP2(H2)
THERMAL
SHUTDOWN
VSHUNT2
Power
Switch
SOURCE
(S2)
BP2
DRIVER
HIGH-SIDE
RECEIVER AND
DRIVER LOGIC
DRIVE LINK
TO
HIGH-SIDE
SOURCE
(S1)
PRIMARY BYPASS
(BP1)
IN
PI-8553-110920
Figure 3. Block Diagram.
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Rev. G 07/22
ClampZero
Pin Functional Description
Not Connected (NC) Pin (Pins 1-2, 4-5)
These pins are not electrically connected. Pin 5 must connect to S1 pin.
LOW-SIDE SOURCE (S1) Pin (Pins 3 and 6)
Source connection of low-side controller.
LOW-SIDE RECEIVER (IN) Pin (Pin 7)
Receiver for Clamp Zero trigger; connects to HSD pin of
InnoSwitch4.
NC
NC
S1
NC
NC
S1
IN
BP1
1
2
3
4
5
6
7
8
LOW-SIDE BYPASS (BP1) Pin (Pin 8)
Supply voltage for low side controller. Needs to be connected to BPP of
InnoSwitch4 primary to draw power from auxiliary winding.
16 D
11-12 S2
10 S2
9 BP2
PI-8987a-011420
HIGH-SIDE BYPASS (BP2) Pin (Pin 9)
Supply voltage for high-side controller.
Figure 4. Pin Configuration.
HIGH-SIDE SOURCE (S2) Pin (Pins 10-12)
Source connection of high-side switch.
InnoSwitch4. Thus the BP2 capacitor value is limited to 150 nF
(min 100 nF/max 220 nF). Higher value BP2 capacitor is undesirable
as this would cause too much delay in start-up and cause possible
overshoot of primary clamp voltage.
DRAIN (D) Pin (Pin 16)
Drain of high-side switch.
ClampZero Functional Description
The ClampZero integrates low-side and high-side controller, plus a
high-side power switch with gate driver.
The ClampZero is the partner IC with InnoSwitch4 to provide zero
voltage switching (ZVS) functionality to the main power switch of
flyback power converter. The ClampZero IC operates as an active
clamping circuit in a flyback power supply that has the ability to
operate in continuous conduction mode (CCM) and discontinuous
conduction mode (DCM). The ClampZero incorporates a high-side
power switch and self-biasing controller with integrated thermal
protection, low-to-high side communication and low-side transceiver
to receive a clamp turn-on signal from the InnoSwitch4 primary
controller.
Figure 3 shows the functional block diagram of the controller,
highlighting the most important features.
LOW-SIDE BYPASS Pin
Low-side controller receives its bias for BP1 from InnoSwitch4 BPP
pin. When BP1 voltage is VBP1(RESET)1 or greater, low-side controller is
functional and able to receive an HSD pulse from InnoSwitch4 and
communicate the drive instruction to the high-side driver stage.
LOW-SIDE RECEIVER Pin
The ClampZero low-side controller receives signal from InnoSwitch4
HSD pin. During the rising edge of the signal, the low-side controller
communicates the drive instruction to turn on the high-side switch
when HSD signal is above VIN(R). During the falling edge of the signal,
the low-side controller communicates the drive instruction to turn off
the high-side switch when HSD signal is below VIN(F).
HIGH-SIDE BYPASS Pin Regulator
High-side BYPASS pin has an internal regulator that charges the BP2
to VBP2 by drawing current from the DRAIN pin whenever the power
switch is off. The amount of charge current available for BP2 is
important in order to have fast start-up from initial switching of
HIGH-SIDE BYPASS Pin Undervoltage Threshold
The BP2 pin undervoltage circuitry disables the power switch when
the BP2 pin voltage drops below ~4.4 V (VBP2 – VBP2(H2)) in steady-state
operation. Once the BP2 pin voltage falls below this threshold, it
must rise to VBP2 to re-enable turn-on of the power switch.
In addition, a shunt regulator clamps BP2 pin voltage to VSHUNT2 when
current is provided to the BP2 through external bias winding or boot
strap circuit. This removes the excessive dissipation from Drain to
BP2 charge current during steady-state operation.
Over-Temperature Protection
The thermal shutdown circuitry senses the die temperature. If the
die temperature rises above the threshold, the power switch is
disabled and remains disabled until the die temperature falls by TSD(H)
at which point switching is re-enabled. A large amount of hysteresis
is provided to prevent over-heating of the PCB due to a continuous
fault condition.
Zero Voltage Switching (ZVS)
InnoSwitch4 will achieve ZVS operation both in CCM and DCM
operation with ClampZero providing extra high side switch. The
operation of the converter is as:
• I nnoSwitch4, after receiving the Flux Link pulse, does not immediately turn on primary switch.
• InnoSwitch4 primary controller first generates a fixed duration pulse
on the HSD pin. This pulse will control the power switch inside
ClampZero, and the switch will be turned on when HSD pulse is
high. ClampZero starts recycling clamp capacitor energy to output
and also building up energy on transformer magnetizing inductance
and leakage inductance which are used later for ZVS.
• After InnoSwitch4 terminates the HSD pulse, it waits for additional
delay and then turns on the primary switch. This delay is programmable by InnoSwitch4. During this delay, the energy built up at
magnetizing inductance and leakage inductance will help discharge
COSS of primary switch in InnoSwitch4 to achieve ZVS.
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Rev. G 07/22
ClampZero
Applications Example
C6
220 pF
250 VAC
C17
100 nF
630 V
R3
2.00 MΩ
1%
1
2
3
3
2
4
1
L2
18 mH
D1
US1K-13-F
BP2
C2
100 µF
400 V
S1
IN
C15
100 nF
50 V
R18
3.09 kΩ
1%
C16
4.7 µF
50 V
3
4
2
1
C9
220 pF
100 V
R10
10 Ω
1%
D2
BAV21WS-7-F
FL3
4
T1
RM8
VOUT
R14
150 kΩ
1%
1/8 W
R16
10 kΩ
C12
6.8 nF
50 V
R15
10 kΩ
1%
1/16 W
C8
330 pF
50 V
C11
330 µF
25 V
C13
1 µF
50 V
RTN
R17
0.009 Ω
1%
Q1
AON6220
C18
D6
1 µF
100 V US1M-13-F
BP1
C1
330 nF
310 VAC
C4
22 µF
35 V
D4
US1M-13-F
S2
HS
FL1
C19
2.2 nF
630 V
D
LS
R1
R2
1.3 MΩ 1.3 MΩ
1%
1%
D7
BAV19WS
3
R4
2.00 MΩ
1%
ClampZero
U2
CPZ1061M
4
VR1
SMBJ200A
200 V
VR2
MMSZ5243BT1G
BR1
3KBP08M
C10
330 µF
25 V
FL2
D3
V12P10-M3/86A
1
C14
1 µF
25 V
R9
47 Ω
R8
2 kΩ
1%
R11
300 Ω
1/10 W
C7
2.2 µF
25 V
R5
30 kΩ
1%
CONTROL
L
AC
IN
N
S HSD
IS
GND
FB
BPS
SR
V
D
F1
3.15 A
FW
L1
200 µH
VOUT
BPP
InnoSwitch4-CZ
U1
INN4073C
C5
4.7 µF
50 V
PI-9247-111621
Figure 5. Schematic 20 V / 3.25 A Notebook Adapter Power Supply.
The circuit shown in Figure 5 is a 20 V, 3.25 A single output power
supply using INN4073C and CPZ1061M. This single output design is
DOE Level 6 and EC CoC v5 compliant.
Input fuse F1 isolates the circuit and provides protection from
component failure, and the common mode choke L1 and L2 with
capacitor C1 attenuation for EMI. Bridge rectifier BR1 rectifies the AC
line voltage and provides a full wave rectified DC across the filter
capacitor C2. Y capacitor C6 connected between the power supply
output and input helps to reduce common mode EMI.
Resistors R1 and R2 along with U2 discharge capacitor C1 when the
power supply is disconnected from AC mains.
One end of the transformer primary is connected to the rectified DC
bus; the other is connected to the drain terminal of the switch inside
the InnoSwitch4 IC (U1). Resistors R3 and R4 provide input voltage
sense protection for undervoltage and overvoltage conditions.
The primary clamp formed by diode D1 and capacitor C17 limits the
peak drain voltage of U1 at the instant of turn-off of the switch inside
U1. The energy stored in the leakage inductance of transformer T1
will be transferred to capacitor C17. Part of the magnetizing energy
will also get transferred to C17 depending on the capacitance value
used. VR1 is used to protect the InnoSwitch4 from excessive drain
voltages if there is any malfunction of the power supply.
When the FluxLinkTM signal is received from the secondary-side, the
InnoSwitch4 generates an HSD signal to turn on the ClampZero
device. When the ClampZero IC (U2) turns on, to achieve soft
switching of the InnoSwitch4 primary switch, clamp capacitor C17
starts to charge the leakage inductance of the transformer in the
case of CCM operation and both the leakage and the magnetizing
inductance of the transformer in the case of DCM operation. Ultrafast
diodes D1 and D4 are used to divert the transformer current from the
body diode of ClampZero’s high-side switch to minimize the reverserecovery energy. Those diodes (D1 and D4) and capacitor C19 are
not required for the CPZ107xM. A small delay is provided from the
instant the high-side switch turns off in order to achieve zero voltage
switching on the primary switch. This delay is programmable by
different resistor values of R5. Capacitor C19 will help reduce the
voltage on the ClampZero IC (U2) to provide soft turn-on.
Capacitor C16 is used to provide local decoupling at the BP1 pin.
Capacitor C15 provides the decoupling for BP2 pin. Diode D6 and
capacitor C18 form a bootstrap circuit to provide the bias for the
high-side BP2 pin. Resistor R18 limits the current flowing into the
BP2 pin.
The InnoSwitch4 IC is self-starting, using an internal high-voltage
current source to charge the PRIMARY BYPASS pin capacitor (C5)
when AC is first applied. During normal operation, the primary-side
block is powered from an auxiliary winding on the transformer T1.
Output of the auxiliary (or bias) winding is rectified using diode D2
and filtered using capacitor C4. Resistor R8 limits the current being
supplied to the PRIMARY BYPASS pin of InnoSwitch4 IC (U1).
Output regulation is achieved using modulation control, where the
frequency and ILIM of switching cycles are adjusted based on the
output load. At high load, most switching cycles are enabled for a
high value of ILIM in the selected ILIM range, and at light load or
no-load, most cycles are disabled, and the ones enabled have a low
value of ILIM in the selected ILIM range. Once a cycle is enabled,
the switch remains on until the primary current ramps to the device
current limit for the specific operating state.
The latch-off/auto-restart primary-side overvoltage protection is
obtained using Zener diode VR2 with current limiting resistor R9. In
a flyback converter, output of the auxiliary winding tracks the output
voltage of the converter. In case of overvoltage at the output of the
converter, the auxiliary winding voltage increases and causes
breakdown of VR2, which then causes a current to flow into the BPP
pin of InnoSwitch4 IC U1. If the current flowing into the BPP pin
increases above the ISD threshold, the U1 controller latches off to
prevent any further increase in output voltage.
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Rev. G 07/22
ClampZero
The secondary-side of the InnoSwitch4 IC provides output voltage,
output current sensing, and drive to a MOSFET providing synchronous
rectification. The secondary of the transformer is rectified by SR FET
Q1/D3 and filtered by capacitors C10 and C11. Capacitor C13 is used
to reduce the high-frequency output voltage ripple. High-frequency
ringing during switching transients that would otherwise create
radiated EMI is reduced via RCD snubber R10, C9, and D7. Diode D7
minimizes the dissipation in resistor R10.
Below the CC threshold, the device operates in constant voltage
mode. During constant voltage mode operation, output voltage
regulation is achieved through sensing the output voltage via divider
resistors R14 and R15. The voltage across R15 is fed into the
FEEDBACK pin with an internal reference voltage threshold of 1.265 V.
The output voltage is regulated so as to achieve a voltage of 1.265 V
on the FEEDBACK pin. Capacitor C8 provides noise filtering of the
signal at the FEEDBACK pin.
The gate of Q1 is turned on by the secondary-side controller of IC U1,
based on the winding voltage sensed via resistor R11 and fed into the
FWD pin of the IC.
During CC operation, when the output voltage falls, the device
directly powers itself from the secondary winding. During the
on-time of the primary-side power switch, the forward voltage that
appears across the secondary winding is used to charge the
decoupling capacitor C7 via resistor R11 and an internal regulator.
This allows output current regulation to be maintained down to
~3.4 V. Output current is sensed by monitoring the voltage drop
across resistor R17 between the IS and SECONDARY GROUND pins.
A threshold of approximately 35 mV reduces losses. C14 provides
filtering on the IS pin from external noise. Once the internal current
sense threshold is exceeded, the device regulates the number of
switch pulses to maintain a fixed output current.
In continuous conduction mode of operation, the SR MOSFET is
turned off just prior to the secondary-side commanding a new
switching cycle from the primary. In discontinuous mode of
operation, the power MOSFET is turned off, when the voltage drop
across the MOSFET falls below a threshold of approximately VSR(TH) mV.
The secondary side of the IC U1 is self-powered from either the
secondary winding forward voltage or the output voltage. Capacitor
C7 connected to the BPS pin of IC U1 provides decoupling for the
internal circuitry.
Layout Example
Y capacitor connection to the plus
bulk rail on the primary-side for
surge protection.
Maximize source cu.
area for good heat sinking.
Figure 6. PCB Layout Top Side.
Keep Innoswitch4 switching
loop area and clampzero
switching loop area short.
Place clamp components close to
Bulk capacitor, Transformer and
Innoswitch4 drain.
6.2 mm Spark Gap for ESD.
Place BPP and BPS
capacitors near the
Innoswitch4 IC.
Keep IS-GND pin sense
resistor close to output
capacitor and output
connector
Keep IS-GND pin
decoupling capacitor
close to the
Innoswitch4 IC.
Keep FEEDBACK pin
decoupling capacitor
close to the
Innoswitch4 IC
Keep output SF FET
and output filter
capacitor loop short
Maximize drain area of
SR FET for good heat
sinking
Place BP1 and BP2
Maximize source cu.
Place Vpin sense resistors
decoupling caps close area for good heat sinking.
close to the Innoswitch4 IC.
to the clampzero IC.
In order to increase ESD
immunity and to meet isolation
requirements, no traces are
routed beneath the IC
Figure 7. PCB Layout Bottom Side.
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ClampZero
Applications Example 2
C5
2.2 nF
250 VAC
VBUS
3
400 V
C16
0.1 µF
250 V
C27
330 µF
25 V
FL1
D6
UF4003
4
R22
1 kΩ
C26
330 µF
25 V
R28
20 Ω
2W
C22
470 pF
200 V
FL2
R21
2.00 MΩ
1%
C31
330 pF
16 V
D7
TSP15H150SS1G
Q1
SIR870DP
R27
10 kΩ
1%
C28
330 µF
25 V
Q2
SIR870DP
1
VR2
EDZVT2R10B
10 V
D9
S1AB-13-F
C21
4.7 µF
10 V
R17
10 Ω
1%
C18
22 µF
35 V
V
D
CONTROL
S HSD
R26
30 kΩ
1%
IS
D4
HS1KFL
800 V
GND
R18
3 kΩ
1%
C20
100 nF
50 V
FB
BP1
S1
C17
1 µF
100 V
BPS
C19
100 nF
25 V
IN
LS
R24
2.2 kΩ
RTN
J2
R32
0.01 Ω
1%
BP2
SR
VCCP
C25
330 pF
25 V
S2
FW
R25
47 Ω
C23
2.2 µF
25 V
D
HS
C32
1 µF
50 V
R30
0.01 Ω
1%
T1
PQ32/30
ClampZero
U2
CPZ1076M
C30
330 µF
25 V
R23
147 kΩ
1%
R31
0.01 Ω
1%
R19
300 Ω
2
D5
BAV21WS-7-F
20 V, 9 A
J1
R20
2.00 MΩ
1%
VR1
SMBJ170A
C29
330 µF
25 V
VOUT
BPP
InnoSwitch4-CZ
U3
INN4177C
C15
0.47 µF
25 V
PI-9465b-122121
Figure 8. Schematic 20 V / 9 A Power Supply.
The circuit shown in Figure 8 is a DC/DC stage 20 V, 9 A single output
power supply using INN4177C and CPZ1076M. This single output
design exceed requirement for DOE Level 6 and EC CoC v5 compliant.
Y capacitor C5 is connected between the power supply output and
input helps to reduce common mode EMI.
One end of the transformer primary is connected to the rectified DC
bus; the other is connected to the drain terminal of the switch inside
the InnoSwitch4 IC (U3). Resistors R20 and R21 provide input
voltage sense protection for undervoltage and overvoltage conditions.
The primary clamp formed by switch of U2 and capacitor C16 limits
the peak drain voltage of U3 at the instant of turn-off of the switch
inside U3. The energy stored in the leakage inductance of transformer
T1 will be transferred to capacitor C16. Part of the magnetizing
energy will also get transferred to C16 depending on the capacitance
value used. VR1 is used to protect the InnoSwitch4 from excessive
drain voltages if there is any malfunction of the power supply.
When the FluxLink signal is received from the secondary side, the
InnoSwitch-4 generates an HSD signal to turn on the ClampZero
device. When the ClampZero IC (U2) turns on, to achieve soft
switching of the InnoSwitch4 primary switch, clamp capacitor C16
starts to charge the leakage inductance of the transformer in the
case of CCM operation and both the leakage and the magnetizing
inductance of the transformer in the case of DCM operation. A small
delay is provided from the instant the high-side switch turns off in
order to achieve zero voltage switching on the primary switch. This
delay is programmable by different resistor values of R26.
Capacitor C20 is used to provide local decoupling at the BP1 pin.
Capacitor C19 provides the decoupling for BP2 pin. Diode D4 and
capacitor C17 form a bootstrap circuit to provide the bias for the
high-side BP2 pin. Resistor R18 limits the current flowing into the
BP2 pin.
The InnoSwitch-4 IC is self-starting, using an internal high-voltage
current source to charge the PRIMARY BYPASS pin capacitor (C15)
when input AC is first applied. During normal operation, the
primary-side block is powered from an auxiliary winding on the
transformer T1. Output of the auxiliary (or bias) winding is rectified
using diode D5 and filtered using capacitor C18. Resistor R24 limits
the current being supplied to the PRIMARY BYPASS pin of
InnoSwitch4 IC (U3).
Output regulation is achieved using modulation control, where the
frequency and ILIM of switching cycles are adjusted based on the
output load. At high load, most switching cycles are enabled for a
high value of ILIM in the selected ILIM range, and at light load or
no-load, most cycles are disabled, and the ones enabled have a low
value of ILIM in the selected ILIM range. Once a cycle is enabled,
the switch remains on until the primary current ramps to the device
current limit for the specific operating state.
The latch-off/auto-restart primary-side overvoltage protection is
obtained using Zener diode VR2 with current limiting resistor R25. In
a flyback converter, output of the auxiliary winding tracks the output
voltage of the converter. In case of overvoltage at the output of the
converter, the auxiliary winding voltage increases and causes
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Rev. G 07/22
ClampZero
breakdown of VR2, which then causes a current to flow into the BPP
pin of InnoSwitch4 IC U3. If the current flowing into the BPP pin
increases above the ISD threshold, the U3 controller latches off to
prevent any further increase in output voltage.
The secondary-side of the InnoSwitch4 IC provides output voltage,
output current sensing, and drive to a MOSFET providing synchronous
rectification. The secondary of the transformer is rectified by SR
FET’s Q1, Q2 and diode D3 and filtered by capacitors C26 – C30.
Capacitor C32 is used to reduce the high-frequency output voltage
ripple. High-frequency ringing during switching transients that would
otherwise create radiated EMI is reduced via RCD snubber R28, C22,
and D6. Diode D6 minimizes the dissipation in resistor R28.
The gate of Q1 and Q2 is turned on by the secondary-side controller
of IC U3, based on the winding voltage sensed via resistor R19 and
fed into the FWD pin of the IC.
In continuous conduction mode of operation, the SR MOSFET is
turned off just prior to the secondary side commanding a new
switching cycle from the primary. In discontinuous mode of
operation, the power MOSFET is turned off, when the voltage drop
across the MOSFET falls below a threshold of approximately VSR(TH) mV.
The secondary-side of the IC U3 is self-powered from either the
secondary winding forward voltage or the output voltage. Capacitor
C23 connected to the BPS pin of IC U3 provides decoupling for the
internal circuitry.
Below the CC threshold, the device operates in constant voltage
mode. During constant voltage mode operation, output voltage
regulation is achieved through sensing the output voltage via divider
resistors R23 and R27. The voltage across R27 is fed into the FB pin
with an internal reference voltage threshold of 1.265 V. The output
voltage is regulated so as to achieve a voltage of 1.265 V on the FB
pin. Capacitor C25 provides noise filtering of the signal at the FB pin.
Resistor R22 together with C31 forms a feed forward circuit and
reduces the output triple.
During CC operation, when the output voltage falls, the device
directly powers itself from the secondary winding. During the
on-time of the primary-side power switch, the forward voltage that
appears across the secondary winding is used to charge the
decoupling capacitor C23 via resistor R19 and an internal regulator.
This allows output current regulation to be maintained down to ~3.4 V
depending on the trim configuration. Output current is sensed by
monitoring the voltage drop across resistor R30 – R32 between the
IS and SECONDARY GROUND pins. A threshold of approximately
35 mV reduces losses. Resistor R17 and capacitor C21 provides
filtering on the IS pin from external noise. Once the internal current
sense threshold is exceeded, the device regulates the number of
switch pulses to maintain a fixed output current.
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ClampZero
Key Application Considerations
No-load Consumption
The ClampZero device draws energy from the BP1 pin decoupling
capacitor, which is supplied by the internal tap of InnoSwitch4. The
InnoSwitch4 IC can start in self-powered mode, drawing energy from
the BYPASS pin capacitor charged through an internal current source.
Use of a bias winding, however, is required to provide supply current
to the PRIMARY BYPASS pin, once the InnoSwitch4 IC has started
switching. An auxiliary (bias) winding provided on the transformer
serves this purpose. The high-side BP2 pin decoupling capacitor of
the ClampZero device draws energy from the internal tap, once the
power supply starts switching. In order to minimize the no-load
consumption, a bootstrap diode D6 is recommended. Resistors R8
and R18 shown in Figure 5 should be adjusted to achieve the lowest
no-load input power. ClampZero typically consumes ~35 µA from the
BP1 pin and ~50 µA from the BP2 pin at no-load, adding only a few
mW to total system losses.
Critical Components Selection
BP2 Pin Decoupling Capacitor
The high-side BYPASS pin has an internal regulator that charges BP2
to VBP2 by drawing current from the DRAIN pin whenever the power
switch is off. The amount of charge current available for BP2 is
important in order to have fast start-up from initial switching of
InnoSwitch4. Thus, the BP2 capacitor value is set to 150 nF. A
higher value BP2 capacitor is undesirable, because too much start-up
delay may cause overshoot of the primary clamp voltage. A 100 nF
to 220 nF capacitor may be used. At least 10 V, 0603 or larger size
rated X5R or X7R dielectric capacitors are recommended to ensure
that minimum capacitance requirements are met. The ceramic
capacitor type designations, such as X7R or X5R from different
manufacturers or different product families, do not have the same
voltage coefficients. It is recommended that capacitor data sheets
be reviewed to ensure that the selected capacitor will not have more
than 20% drop in capacitance at 5 V. Do not use Y5U or Z5U / 0402
rated MLCC, because this type of SMD ceramic capacitor has very
poor voltage and temperature coefficient characteristics.
Bias Winding and External Bias Circuit
The internal regulator connected from the DRAIN pin of the switch to
the PRIMARY BYPASS pin of the InnoSwitch4 primary-side controller
charges the capacitors connected to the InnoSwitch4 BPP pin and
ClampZero BP1 pin to achieve start-up. A bias winding should be
provided on the transformer with a suitable rectifier and filter capacitor
to create a bias supply that can be used to supply current to the BPP
and BP1 pins. The turns ratio for the bias winding should be selected
such that a minimum of ~8 V is developed across the bias winding at
the lowest rated output voltage of the power supply at the lowest
load condition. If the voltage is lower than this, no-load input power
increases.
The bias current from the external circuit should be set to IS1(MAX) to
achieve lowest no-load power consumption when operating the
power supply at 230 VAC input, (VBPP > 5 V). An aluminum capacitor
of at least 22 µF with a voltage rating 1.2 times greater than the
highest voltage developed across the capacitor is recommended.
Highest voltage is typically developed across this capacitor when the
supply is operated at the highest rated output voltage and load with
the lowest input AC supply voltage.
Clamp Capacitor
It is recommended to choose the value of the clamp capacitor such
that ~0.25 times the resonant period of the CCLAMP and LLKG equals the
HSD pulse width. Capacitance in the range of 10 nF to 100 nF may
be used depending on the design. At least 200 V, 1206 or larger size
rated X7R dielectric capacitors are recommended.
HSD Pulse Width `
r
L C
2 LKG CLAMP
Layout Considerations
The following layout considerations are specifically for the ClampZero
components. For placement and layout of InnoSwitch4 specific and
power components, check the InnoSwitch4 data sheet.
1. The ClampZero BP1 pin is supplied and regulated by the
InnoSwitch4 internal BPP regulator. A separate decoupling
capacitor needs to be placed very close to the BP1 pin of the
ClampZero device.
2. The high-side BP2 pin is supplied by the internal drain tap during
startup until the external bias is available from an external
bootstrap circuit. A decoupling capacitor should be placed very
close to the BP2 pin of the ClampZero IC.
3. Even though ClampZero conducts only for a short period and
dissipates a small amount of power, some amount of PCB copper
heat sinking on the source pin of the ClampZero device is required
to minimize the thermals.
4. It is recommended to place the bootstrap components close to the
BP2 and SOURCE pins of the ClampZero device to minimize the
noise coupling into other parts of the circuit.
5. Place the ClampZero IC as close as possible to the clamp capacitor
and transformer to minimize the clamp loop area.
Figure 2 shows the ClampZero layout used for the design in Figure 5
following the recommendations stated above.
Quick Design Checklist
Aside from the verification of the functionality of the InnoSwitch4 IC,
proper operation of the ClampZero IC must also be checked. At the
minimum, the following verification tests must be performed.
1. Maximum Drain Voltage – Verify that VDS of ClampZero does not
exceed 90% of the breakdown voltage at the highest input
voltage and peak (overload) output power in normal operation
and during start-up.
2. Maximum Drain Current – Under all conditions, the maximum
drain current for the ClampZero switch should be below the
specified absolute maximum rating.
3. Thermal Check – Verify that the ClampZero IC does not cause an
OTP fault when operating at maximum load throughout the whole
input range. Sufficient bias current needs to be supplied to the
BP2 pin of the ClampZero device; otherwise, operating with the
internal tap can result in higher dissipation on the ClampZero
device and eventually reach extreme operating conditions.
Triggering OTP of the ClampZero device can cause additional
thermal stress on the InnoSwitch4 device and the TVS device
used across the clamp capacitor because of loss of zero voltage
switching. This can also increase voltage stress on the DRAIN pin
of the InnoSwitch4 and ClampZero devices.
8
www.power.com
Rev. G 07/22
ClampZero
Absolute Maximum Ratings1,2
DRAIN to S2 Pin Voltage: CPZ1061M & CPZ1062M....... -1.8 V8 to 650 V
CPZ1075M & CPZ1076M...... -4.2 V8 to 750 V6
DRAIN Pin Peak Current: CPZ1061M.....................................±3.26 A3
CPZ1062M.....................................±3.87 A3
CPZ1075M...................................... ±3.2 A7
CPZ1076M...................................... ±6.5 A7
BP1 to S1 Pin Voltage.....................................................-0.3 V to 6 V
IN to S1 Pin Voltage .......................................................-0.3 V to 6 V
BP2 to S2 Pin Voltage.....................................................-0.3 V to 6 V
S2 to S1 Pin Voltage................................................... -0.3 V to 650 V
Storage Temperature ...................................................-65 to 150 °C
Operating Junction Temperature4 ................................. -40 to 150 °C
Ambient Temperature ..................................................-40 to 105 °C
Lead Temperature5 ................................................................ 260 °C
Notes:
1. All voltages referenced to low-side or high-side source, TA = 25 °C.
2. Maximum ratings specified may be applied one at a time without
causing permanent damage to the product. Exposure to Absolute
Maximum Ratings conditions for extended periods of time may
affect product reliability.
3. Please refer to Figure 9 about maximum allowable voltage and
current combinations.
4. Normally limited by internal circuitry.
5. 1/16” from case for 5 seconds.
6. Maximum drain voltage (non-repetitive pulse) 750 V, maximum
continuous voltage 650 V.
7. Please refer to Figure 17 about maximum voltage and current
combinations.
8. Minimum drain voltage (non-DC).
Thermal Resistance
Thermal Resistance: CPZ106xM
(qJA)..................................... 82 °C/W2, 76 °C/W3
(qJC).....................................................19 °C/W1
CPZ107xM
(qJA).................................. 126 °C/W2, 115 °C/W3
(qJC).....................................................36 °C/W1
Parameter
Notes:
1. Case termperature measured at top center of package body.
2. Solder to 0.36 sq. in (232 mm2), 2 oz. (610 g/m2) copper clad.
3. Solder to 1 sq. in (645 mm2), 2 oz. (610 g/m2) copper clad.
Symbol
Conditions
SOURCE = 0 V
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Min
Typ
Max
Units
IS1(2)
VBP2 = VBP2 + 0.1 V
(Switch not Switching)
TJ = 25 °C
35
47
55
µA
CPZ1061M
400
580
800
CPZ1062M
600
760
950
1490
1700
Control Functions
BP2 Supply Current
IS2(2)
VBP2 = VBP2 + 0.1 V
(Switch Switching at
fOSC = 180 kHz)
TJ = 25 °C
CPZ107xM
ICH1(2)
VBP2 = 0 V
TJ = 25 °C
4.2
5.2
6.2
ICH2(2)
VBP2 = 4 V
TJ = 25 °C
4.2
5.2
6.2
BP2 Pin Charge Current
µA
mA
BP2 Pin Voltage
VBP2
4.8
5
5.2
V
BP2 Pin Voltage
Hysteresis
VBP2(H2)
0.38
0.6
0.8
V
BP2 Shunt Voltage
VSHUNT2
5.2
5.45
5.7
V
3
3.23
3.45
3.1
3.45
BP2 Power-Up Reset
Threshold voltage
VBP2(RESET)2
IBP2 = 2 mA
TJ = 25 °C
CPZ1061M
CPZ1062M
CPZ1075M
CPZ1076M
V
9
www.power.com
Rev. G 07/22
ClampZero
Parameter
Symbol
Conditions
SOURCE = 0 V
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Min
Typ
Max
Units
VBP1(RESET)2
TJ = 25 °C
3.4
3.8
4.2
V
IS1(1)
Non Switching, VBP1 = 5.1 V
IN: 0 V
TJ = 25 °C
20
30
50
µA
IS2(1)
Switching, IN: 500 ns Pulse at 180 kHz
VBP1 = 5.1 V
TJ = 25 °C
60
80
100
µA
Control Functions (cont.)
BP1 Power-Up Reset
Threshold voltage
BP1 Supply Current
(Load)
IN Pin Voltage Rising
Threshold
VIN(R)
2.75
2.93
3.25
V
IN Pin Voltage Falling
Threshold
VIN(F)
1.6
1.82
2.1
V
30
57
100
54
100
Delay from HSD High to
ClampZero ON
Delay From HSD Low To
ClampZero OFF
DHSD(ON)
DHSD(OFF)
CPZ1061M; CPZ1062M
CPZ1075M; CPZ1076M
CPZ1061M
35
55
80
CPZ1062M
42
62
90
CPZ1075M
67
100
CPZ1076M
72
100
142
150
ns
ns
Circuit Protection
Thermal Shutdown
TSD
Thermal Shutdown
Hysteresis
TSD(H)
135
70
°C
°C
10
www.power.com
Rev. G 07/22
ClampZero
Parameter
Symbol
Conditions
SOURCE = 0 V
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
IDSS1
VBP2 = VBP2 + 0.1 V
VDS = 80% Peak Drain Voltage
TJ = 125 °C
IDSS2
VBP2 = VBP2 + 0.1 V
VDS = 325 V
TJ = 25 °C
Min
Typ
Max
Units
200
µA
Electrical Characteristics
Off-State Drain Leakage
Current
CPZ1061M
CPZ1062M
On-State Resistance
RDS(ON)
CPZ1075M
CPZ1076M
15
µA
ID = 300 mA
TJ = 25 °C
3.20
3.68
ID = 300 mA
TJ = 100 °C
4.96
5.70
ID = 300 mA
TJ = 25 °C
1.95
2.24
ID = 300 mA
TJ = 100 °C
3.02
3.47
ID = 2 A
TJ = 25 °C
0.85
1.20
ID = 2 A
TJ = 100 °C
1.35
1.80
ID = 4 A
TJ = 25 °C
0.52
0.78
ID = 4 A
TJ = 100 °C
0.78
1.17
W
11
www.power.com
Rev. G 07/22
ClampZero
1.0
0.8
0.6
0.4
TCASE = 25 °C
TCASE = 100 °C
0.2
0
100 200 300 400 500
0
600 700
Drain Voltage (V)
Figure 9. Maximum Allowable Drain Current vs. Drain Voltage.
Scaling Factors:
CPZ1061M 1.95
CPZ1062M 3.20
75
Power (mW)
1000
2
4
6
Drain Voltage (V)
8
10
Figure 10. Output Characteristics.
PI-8416d-112321
10000
0
100
PI-8417d-112321
0.0
Drain Capacitance (pF)
Scaling Factors:
CPZ1061M 1.95
CPZ1062M 3.20
1.2
Drain Current (A)
1.0
PI-8418d-112321
1.4
PI-8505-072519
Drain Current (A)
(Normalized to Absolute
Maximum Current Rating)
Typical Performance Curves
Scaling Factors:
CPZ1061M 1.95
CPZ1062M 3.20
50
25
10
Switching Frequency = 100 kHz
1
1
100
200
300
400
Drain Voltage (V)
500
0
600
Figure 11. COSS vs. Drain Voltage.
0
100
200
300
400
Drain Voltage (V)
500
600
Figure 12. Drain Capacitance Power.
Breakdown Voltage
(Normalized to 25 °C)
PI-2213-021518
1.1
1.0
0.9
-50 -25
0
25
50
75 100 125 150
Junction Temperature (°C)
Figure 13. Breakdown vs. Temperature.
12
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Rev. G 07/22
ClampZero
Drain Capacitance (pF)
Scaling Factors:
CPZ1075M 0.32
CPZ1076M 0.65
20
10000
PI-8853bb-112921
Drain Current IDS (A)
25
15
10
5
0
TCASE = 25 °C
TCASE = 100 °C
0
2
4
6
8
Scaling Factors:
CPZ1075M 0.32
CPZ1076M 0.65
1000
100
10
10
0 50
Drain Voltage VDS (V)
Power (mW)
200
150
100
50
0
0
100
200
300
400
Drain Voltage (V)
Figure 16. Drain Capacitance Power.
250
350
450
550
500
100
PI-8851dd-112921
Scaling Factors:
CPZ1075M 0.32
CPZ1076M 0.65
Drian Current (A)
250
150
Drain Voltage (V)
Figure 15. COSS vs. Drain Voltage.
PI-8854z-112921
Figure 14. Optional Characteristics.
PI-8852aa-112921
Typical Performance Curves
10
Scaling Factors:
CPZ1075M 0.32
CPZ1076M 0.65
1
0.1
0.01
0.001
10
100
Drain Voltage (V)
1000
Figure 17. Maximum Allowable Drain Current vs. Drain Voltage.
13
www.power.com
Rev. G 07/22
ClampZero
MinSOP-16A (M Package)
7
3
0.42 Ref.
2.03 Ref.
4
1.35
1.23
4 Lead Tips
2X
16
0.15 C
9
9
16
0.10 C B
0.19
0.46
Ref.
Gauge
Plane
Seating
Plane
2
9.00
H
11.32
0° – 8°
0.22
0.07
Standoff
0.85
0.55
1
B
8
8
0.15 C
1
8 Lead Tips
Pin #1 I.D.
3
4
A
0.30 11X
0.20
0.665
DETAIL A
2
0.25 M C A B
5.67
2X
TOP VIEW
0.10 C A
BOTTOM VIEW
1.94
Body Thickness
1.74
1.16 Ref.
Detail A
3
0.29 12 Leads
0.17
Seating
Plane
C
0.10 C
Coplanarity: 12 Leads
2.16 Max.
Total Mounting Height
SIDE VIEW
END VIEW
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions noted are determined at the outermost extremes
of the plastic body exclusive of mold flash, tie bar burrs, gate
burrs, and inter-lead flash, but including any mismatch between
the top and bottom of the plastic body. Maximum mold protrusion
is 0.18 per side.
3. Dimensions noted are inclusive of plating thickness.
4. Does not include inter-lead flash or protrusions.
5. Controlling dimensions in millimeters.
6. Datums A and B to be determined at Datum H.
7. This dimension is the nominal dimension between leadtips,
not including plating, and not including metal protrusions.
Metal-to-metal distance (Creepage) is 1.85 mm minimum.
POD_MinSOP-16A_E_042922
PI-8833-051622
14
www.power.com
Rev. G 07/22
ClampZero
PACKAGE MARKING
MinSOP-16A
A
C
CPZ1061M
B
YYWW
%%7654321A
A.
B.
C.
D.
D
Power Integrations Registered Trademark
Assembly Date Code (last two digits of year followed by 2-digit work week)
Product Identification (Part #/Package Type)
Lot Identification Code
PI-9220a-111720
Part Ordering Information
• ClampZero Product Family
• Series Number
• Package Identifier
M
MinSOP-16A
• Tape & Reel and Other Options
CPZ 1061 M - TL
TL
Tape & Reel, 2 k pcs per reel.
15
www.power.com
Rev. G 07/22
ClampZero
MSL Table
Part Number
MSL Rating
CPZ1061M
CPZ1062M
CPZ1075M
CPZ1076M
3
3
3
3
Part Ordering Information
• ClampZero Product Family
• Series Number
• Package Identifier
M
MinSOP-16A
• Tape & Reel and Other Options
CPZ 1061 M - TL
TL
Tape & Reel, 2 k pcs per reel.
16
www.power.com
Rev. G 07/22
Revision
Notes
Date
C
Production release.
11/20
D
Introduction of part numbers CPZ1075M, CPZ1076M.
01/22
E
Production release of PowiGaN devices and update the DHSD(ON), DHSD(OFF) and RDS(ON).
03/22
F
Updated MinSOP-16A (M package) drawing.
05/22
G
Updated DRAIN Pin Voltage and Peak Current values in Abs Max Ratings table.
07/22
For the latest updates, visit our website: www.power.com
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations
does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY
HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one
or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of
Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set
forth at www.power.com/ip.htm.
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POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:
1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose
failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or
death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness.
Power Integrations, the Power Integrations logo, CAPZero, ChiPhy, CHY, DPA-Switch, EcoSmart, E-Shield, eSIP, eSOP, HiperLCS, HiperPLC,
HiperPFS, HiperTFS, InnoSwitch, Innovation in Power Conversion, InSOP, LinkSwitch, LinkZero, LYTSwitch, SENZero, TinySwitch, TOPSwitch, PI,
PI Expert, PowiGaN, SCALE, SCALE-1, SCALE-2, SCALE-3 and SCALE-iDriver, are trademarks of Power Integrations, Inc. Other trademarks are
property of their respective companies. ©2022, Power Integrations, Inc.
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