InnoSwitch-CH Family
Off-Line CV/CC Flyback Switcher IC with Integrated 650 V MOSFET,
Synchronous Rectification and Feedback
Product Highlights
Highly Integrated, Compact Footprint
EcoSmart™ – Energy Efficient
• <
10 mW no-load at 230 VAC when supplied by transformer bias
winding
• Easily meets all global energy efficiency regulations
• Low heat dissipation
InnoSwitch-CH
VOUT
Primary FET
and Controller
S
Secondary
Control IC
IS
BPP
Advanced Protection / Safety Features
•
•
•
•
rimary sensed output OVP
P
Secondary sensed output overshoot clamp
Secondary sensed output OCP to zero output voltage
Hysteretic thermal shutdown
FB
GND
BPS
D
SR
SR FET
FWD
• Incorporates flyback controller, 650 V MOSFET, secondary-side
sensing and synchronous rectification driver
• Integrated FluxLink™, HIPOT-isolated, feedback link
• Exceptional CV/CC accuracy, independent of transformer design or
external components
• Instantaneous transient response ±5% CV with 0%-100%-0%
load step
PI-6986-103014
Figure 1. Typical Application/Performance.
Full Safety and Regulatory Compliance
• 1
00% production HIPOT compliance testing equivalent to
6 kV DC/1 sec
• Reinforced insulation
• Isolation voltage >3,500 VAC
• UL1577 and TUV (EN60950 and EN62368) safety approved
• EN61000-4-8 (100 A/m) and EN61000-4-9 (1000 A/m) compliant
Figure 2. High Creepage, Safety-Compliant eSOP Package.
Green Package
• Halogen free and RoHS compliant
Applications
• C
hargers and adapters for smart mobile devices
• High efficiency, low voltage, high current power supplies
Description
Output Power Table
85-265 VAC
Product 3,4
The InnoSwitch™-CH family of ICs dramatically simplifies the development and manufacturing of low-voltage, high current power supplies,
particularly those in compact enclosures or with high efficiency requirements. The InnoSwitch-CH architecture is revolutionary in that the
devices incorporate both primary and secondary controllers, with sense
elements and a safety-rated feedback mechanism into a single IC.
Close component proximity and innovative use of the integrated
communication link permit accurate control of a secondary-side
synchronous rectification MOSFET and optimization of primary-side
switching to maintain high efficiency across the entire load range.
Additionally, the minimal DC bias requirements of the link enables the
system to achieve less than 10 mW no-load in challenging applications
such as smart-mobile device chargers.
Adapter1
Peak or
Open Frame2
INN20x3K
12 W
15 W
INN20x4K
15 W
20 W
INN20x5K
20 W
25 W
Table 1. Output Power Table.
Notes:
1. Minimum continuous power in a typical non-ventilated enclosed typical size
adapter measured at 40 °C ambient. Max output power is dependent on the
design. With condition that package temperature must be < = 125 °C.
2. Minimum peak power capability.
3. Package: eSOP-R16B.
4. x = 0 (No cable compensation), x = 2 (6% cable compensation).
www.power.com
June 2020
This Product is Covered by Patents and/or Pending Patent Applications.
InnoSwitch-CH
PRIMARY BYPASS
(BPP)
DRAIN
(D)
REGULATOR
5.95 V
FAULT
PRESENT
+
AUTORESTART
COUNTER
BYPASS
CAPACITOR
SELECT AND
CURRENT
LIMIT STATE
MACHINE
RESET
5.95 V
5.39 V
BYPASS PIN
UNDERVOLTAGE
-
VI
LIMIT
CURRENT LIMIT
COMPARATOR
+
JITTER
CLOCK
THERMAL
SHUTDOWN
DCMAX
FROM
FEEDBACK
DRIVER
OSCILLATOR
PRI/SEC
RECEIVER
CONTROLLER
PULSE
DCMAXS
S
Q
R
Q
6.4 V
LEADING
EDGE
BLANKING
OVP
LATCH
20 Ω
SOURCE
(S)
PI-7432-110414
Figure 3. Primary-Side Controller Block Diagram.
OUTPUT
VOLTAGE
(VO)
FORWARD
(FWD)
REGULATOR
4.45 V
DETECTOR
SCONDARY
BYPASS
(BPS)
4.45 V
3.80 V
FEEDBACK
(FB)
HAND SHAKE
PULSES
+
CONTROL
-
+
-
CABLE
COMPENSATION
ISENSE
(IS)
TO
RECEIVER
FEEDBACK
DRIVER
+
-
CLOCK
IS THRESHOLD
OSCILLATOR
SYNC RECT
(SR)
ENB
Q
S
Q
R
ENABLE
SR
+
-
SR THESHOLD
SECONDARY
GROUND
(GND)
PI-7433-092717
Figure 4.
Secondary-Side Controller Block Diagram.
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InnoSwitch-CH
Pin Functional Description
InnoSwitch-CH Functional Description
DRAIN (D) Pin (Pin 1)
This pin is the power MOSFET drain connection.
The InnoSwitch-CH combines a high-voltage power MOSFET switch
and both primary-side and secondary-side controllers in one device.
The feedback scheme using a proprietary FluxLink coupling scheme
using the package lead frame and bond wires to provide a reliable
and low-cost means to provide accurate direct sensing of the output
voltage and output current on the secondary to communicate
information to the primary IC. Unlike conventional PWM (pulse width
modulated) controllers, it uses a simple ON/OFF control to regulate
the output voltage and current. The primary controller consists of an
oscillator, a receiver circuit magnetically coupled to the secondary
controller, current limit state machine, 5.95 V regulator on the
PRIMARY BYPASS pin, overvoltage circuit, current limit selection
circuitry, over temperature protection, leading edge blanking and a
650 V power MOSFET. The InnoSwitch-CH secondary controller
consists of a transmitter circuit that is magnetically coupled to the
primary receiver, constant voltage (CV) and constant current (CC)
control circuitry, a 4.45 V regulator on the SECONDARY BYPASS pin,
synchronous rectifier MOSFET driver, frequency jitter oscillator and a
host of integrated protection features. Figures 3 and 4 show the
functional block diagrams of the primary and secondary controllers
with the most important features.
SOURCE (S) Pin (Pin 3-6)
This pin is the power MOSFET source connection. It is also the
ground reference for the PRIMARY BYPASS pin.
PRIMARY BYPASS (BPP) Pin (Pin 7)
It is the connection point for an external bypass capacitor for the
primary IC supply.
NO CONNECTION (NC) Pin (Pin 8)
This pin should be left open or tied to PRIMARY BYPASS pin.
NO CONNECTION (NC) Pin (Pin 9)
This pin should be left open.
FORWARD (FWD) Pin (Pin 10)
The connection point to the switching node of the transformer output
winding for sensing and other functions.
OUTPUT VOLTAGE (VOUT) Pin (Pin 11)
This pin is connected directly to the output voltage of the power
supply to provide bias to the secondary IC.
SYNCHRONOUS RECTIFIER DRIVE (SR) Pin (Pin 12)
Connection to external SR FET gate terminal.
SECONDARY BYPASS (BPS) Pin (Pin 13)
It is the connection point for an external bypass capacitor for the
secondary IC supply.
FEEDBACK (FB) Pin (Pin 14)
This pin connects to an external resistor divider to set the power
supply CV voltage regulation threshold.
SECONDARY GROUND (GND) (Pin 15)
Ground connection for the secondary IC.
ISENSE (IS) Pin (Pin 16)
Connection to the power supply output terminals. Internal current
sense is connected between this pin and the SECONDARY GROUND pin.
D1
S 3-6
BPP 7
NC 8
16 IS
15 GND
14 FB
13 BPS
12 SR
11 VOUT
10 FWD
9 NC
PI-7398-072915
Figure 5. Pin Configuration.
PRIMARY BYPASS Pin Regulator
The PRIMARY BYPASS pin has an internal regulator that charges the
PRIMARY BYPASS pin capacitor to VBPP by drawing current from the
voltage on the DRAIN pin whenever the power MOSFET is off. The
PRIMARY BYPASS pin is the internal supply voltage node. When the
power MOSFET is on, the device operates from the energy stored in
the PRIMARY BYPASS pin capacitor. Extremely low power consumption of the internal circuitry allows the InnoSwitch-CH to operate
continuously from current it takes from the DRAIN pin.
In addition, there is a shunt regulator clamping the PRIMARY BYPASS
pin voltage to VSHUNT when current is provided to the PRIMARY
BYPASS pin through an external resistor. This facilitates powering the
InnoSwitch-CH externally through a bias winding to decrease the
no-load consumption to less than 10 mW (5 V output design).
PRIMARY BYPASS Pin Capacitor Selection
The PRIMARY BYPASS pin can use a ceramic capacitor as small as
0.1 mF for decoupling the internal power supply of the device. A
larger capacitor size can be used to adjust the current limit. A 1 mF
capacitor on the PRIMARY BYPASS pin will select a higher current limit
equal to the standard current of the next larger device. A 10 mF
capacitor on the PRIMARY BYPASS pin selects a lower current limit
equal to the standard current limit of the next smaller device
PRIMARY BYPASS Pin Undervoltage Threshold
The PRIMARY BYPASS pin undervoltage circuitry disables the power
MOSFET when the PRIMARY BYPASS pin voltage drops below VBPP-VBPP(H)
in steady-state operation. Once the PRIMARY BYPASS pin voltage
falls below this threshold, it must rise back above VBPP to enable
switching the power MOSFET.
PRIMARY BYPASS Pin Output Overvoltage Latching Function
The PRIMARY BYPASS pin has an OV protection latching feature.
A Zener diode in parallel to the resistor in series with the PRIMARY
BYPASS pin capacitor is typically used to detect an overvoltage on the
primary bias winding to activate this protection mechanism. In the
event the current into the PRIMARY BYPASS pin exceeds (ISD) the
device will disable the power MOSFET switching. The latching
condition is reset by bringing the primary bypass below the reset
threshold voltage (VBPP(RESET)).
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Rev. K 06/20
InnoSwitch-CH
Over-Temperature Protection
The thermal shutdown circuitry senses the primary die temperature.
This threshold is set to 142 °C with 75 °C hysteresis. When the die
temperature rises above this threshold the power MOSFET is disabled
and remains disabled until the die temperature falls by 75 °C, at which
point it is re-enabled. A large hysteresis of 75 °C is provided to
prevent over-heating of the PC board due to continuous fault condition.
P: Primary Chip
S: Secondary Chip
Start
P: Powered Up, Switching
S: Powering Up
Current Limit Operation
The current limit circuit senses the current in the power MOSFET.
When this current exceeds the internal threshold (ILIMIT), the power
MOSFET is turned off for the remainder of that switch cycle. The
current limit state-machine reduces the current limit threshold by
discrete amounts under medium and light loads.
P: Auto-Restart
S: Powering Up
tAR(OFF)
The leading edge blanking circuit inhibits the current limit comparator
for a short time (tLEB) after the power MOSFET is turned-on. This
leading edge blanking time has been set so that current spikes
caused by capacitance and secondary-side rectifier reverse recovery
time will not cause premature termination of the switching pulse.
Each switching cycle is terminated when the Drain current of the
primary power MOSFET reaches the current limit of the device.
P: Switching
S: Sends Handshaking Pulses
Auto-Restart
In the event of a fault condition such as output overload, output
short-circuit or external component/pin fault, the InnoSwitch-CH
enters into auto-restart (AR) operation. In auto-restart operation the
power MOSFET switching is disabled for t AR(OFF). There are 2 ways to
enter auto-restart after the secondary has taken control:
P: Has Received
Handshaking
Pulses
1. Continuous switching requests from the secondary for time period
exceeding t AR.
2. No requests for switching cycles from the secondary for a time
period exceeding t AR(SK).
S: Has powered
up within tAR
The auto-restart counter is reset once the primary PRIMARY BYPASS
pin falls below the undervoltage threshold VBPP-VBPP(HYS).
Safe-Operating-Area (SOA) Protection
In the event there are two consecutive cycles where the primary
power MOSFET switch current reaches current limit (ILIM) within the
blanking (tLEB) and current limit (tILD) delay time, the controller will
skip approximately 2.5 cycles or ~25 msec. This provides sufficient
time for reset of the transformer without sacrificing start-up time into
large capacitive load. Auto-restart timing is increased when the
device is operating in SOA-mode.
Primary-Secondary Handshake Protocol
At start-up, the primary initially switches without any feedback
information (this is very similar to the operation of a standard
TOPSwitch™, TinySwitch™ or LinkSwitch™ controllers). If no
feedback signals are received during the auto-restart on-time, the
primary goes into auto-restart and repeats. However under normal
conditions, the secondary chip will power-up through the FORWARD
pin or directly from VOUT and then take over control. From then
P: Goes to Auto-Restart Off
S: Bypass Discharging
Yes
tAR
No
P: Continuous Switching
S: Doesn’t Take Control
No
P: Not Switching
S: Doesn’t Take Control
Yes
P: Stops Switching, Hands
Over Control to Secondary
The first condition corresponds to a condition wherein the secondary
controller makes continuous cycle requests without a skipped-cycle
for more than t AR time period. The second method was included to
ensure that if communication is lost, the primary tries to restart again.
Although this should never be the case in normal operation, this can
be useful in the case of system ESD events for example where a loss
of communication due to noise disturbing the secondary controller, is
resolved when the primary restarts after an auto-restart off time.
The auto-restart alternately enables and disables the switching of the
power MOSFET until the fault is removed. The auto-restart counter is
gated by the switch oscillator in SOA mode the auto-restart off timer
may appear to be longer.
No
S: Has Taken
Control?
Yes
End of Handshaking,
Secondary Control Mode
PI-7416-110414
Figure 6.
Primary – Secondary Handshake Flowchart.
onwards the secondary is in control of demanding switching cycles
when required.
The handshake flowchart is shown in Figure 6.
In the event the primary stops switching or does not respond to cycle
requests from the secondary during normal operation when the
secondary has control, the handshake protocol is imitated to ensure
that the secondary is ready to assume control once the primary
begins switching again. This protocol for an additional handshake is
also invoked in the event the secondary detects that the primary is
providing more cycles than were requested.
The most likely event that could require an additional handshake is
when the primary stops switching resulting from a momentary line
drop-out or brown-out event. When the primary resumes operation,
it will default into a start-up condition and attempt to detect handshake pulses from the secondary.
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InnoSwitch-CH
In the event the secondary does not detect that the primary responds
to requests for 3 consecutive cycles, or if the secondary detects that
the primary is switching without cycle requests for 3 or more
consecutive cycles, the secondary controller will initiate a second
handshake sequence.
This protection mode also provides additional protection against
cross-conduction of the SR MOSFET while the primary is switching
with the primary-side in control. This protection mode also prevents
output overvoltage in the event the primary is reset while the
secondary is still in control and light/medium load conditions exist.
Secondary Controller
The feedback driver block is the drive to the FluxLink communication
loop transferring switching pulse requests to the primary IC.
As shown in the block diagram in Figure 4, the secondary controller
is powered through a 4.45 V Regulator block by either VOUT or
FORWARD pin connections to the SECONDARY BYPASS pin. The
SECONDARY BYPASS pin is connected to an external decoupling
capacitor and fed internally from the regulator block.
The FORWARD pin also connects to the negative edge detection
block used for both handshaking and timing to turn on the synchronous rectifier MOSFET (SR FET) connected to the SYNCHRONOUS
RECTIFIER DRIVE pin. The FORWARD pin is also used to sense when
to turn off the SR FET in discontinuous mode operation when the
voltage across the FET on resistance drops below VSR(TH).
In continuous mode operation the SR FET is turned off when the
pulse request is sent to demand the next switching cycle, providing
excellent synchronization free of any overlap for the FET turn-off
while operating in continuous mode.
The mid-point of an external resistor divider network between the
VOUT and SECONDARY GROUND pins is tied to the FEEDBACK pin
to regulate the output voltage. The internal voltage comparator
reference voltage is VREF (1.265V).
The resistor connected between IS and SECONDARY GROUND pins is
the bonding wire sense resistor which is used to regulate the output
current in constant current regulator mode. The ISENSE pin is
connected to the internal bond wire sense resistor and a 33 mV ISV(TH)
threshold comparator used to determine the value at which the power
supply output current is regulated.
Output Overvoltage Protection
In the event the sensed voltage on the FEEDBACK pin is 2% higher
than the regulation threshold, a bleed current of ~10 mA is applied on
the VOUT pin. This bleed current increases to ~140 mA in the event
the FEEDBACK pin voltage is raised to beyond ~20% of the internal
FEEDBACK pin reference voltage. The current sink on the VOUT pin
is intended to discharge the output voltage for momentary overshoot
events. The secondary does not relinquish control to the primary
during this mode of operation.
FEEDBACK Pin Short Detection
In the event the FEEDBACK pin voltage is below the VFB(OFF) threshold
at start-up, the secondary will complete the primary/secondary
handshake and will stop requesting pulses to initiate an auto-restart.
The secondary will stop requesting cycles for t AR(SK), to begin primaryside auto-restart of t AR(OFF). In this condition, the total apparent AR
off-time is t AR(SK) + t AR(OFF). During normal operation, the secondary
will stop requesting pulses from the primary to initiate an auto-restart
cycle when the FEEDBACK pin voltage falls below VFB(OFF) threshold.
The deglitch filter on the VFB(OFF) is less than 10 msec. The secondary
will relinquish control after detecting the FEEDBACK pin is shorted to
ground.
OUTPUT VOLTAGE Pin Auto-Restart Threshold
The OUTPUT VOLTAGE pin includes a comparator to detect when the
output voltage falls below the VOUT(AR) threshold for a duration exceeding tVOUT(AR). The secondary controller will relinquish control when it
detects the OUTPUT VOLTAGE pin has fallen below VOUT(AR) for a time
duration longer than tVOUT(AR). This threshold is meant to limit the
range of constant current (CC) operation.
Cable Drop Compensation (CDC)
The amount of cable drop compensation is a function of the load with
respect to the constant current regulation threshold as illustrated in
Figure 7 below.
φCD × VFB
FEEDBACK Pin
Voltage
The communication is extremely robust. Measures against loss of
communication have been implemented to make the device tolerant
to extreme conditions such as surge, ESD events, or failure of
external component (single point faults).
Cable Drop
Compensation
VFB
No-Load
Load Current
Onset of CC
Regulation
PI-7417-110714
Figure 7. Cable Drop Compensation Characteristic.
The lower feedback pin resistor must be tied to the SECONDARY
GROUND pin (not ISENSE pin) to have output cable drop compensation enabled.
Cable drop compensation only applies for 5 V designs. Cable drop
compensation function is disabled for higher output voltage designs.
Output Constant Current Regulation
The InnoSwitch-CH regulates the output current through internal
sense across bond wires between the ISENSE and SECONDARY
GROUND pins. An external diode may be required across the
ISENSE-SECONDARY GROUND pins to limit the peak voltage across
the bond wire during fault condition. Larger output capacitance
especially at higher output voltages, the output capacitor discharge
into a short-circuited output can exceed the bond wire fusing current.
SR Disable Protection
On a cycle-by-cycle basis the SR is only engaged in the event a cycle
was requested by the secondary controller and the negative edge is
detected on the FORWARD pin. In the event the voltage on the
ISENSE pin exceeds approximately 3 times the ISV(TH) threshold, the
SR MOSFET drive is disabled until the surge current has diminished
to nominal levels.
5
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Rev. K 06/20
InnoSwitch-CH
InnoSwitch-CH Operation
InnoSwitch-CH devices operate in the current limit mode. When
enabled, the oscillator turns the power MOSFET on at the beginning
of each cycle. The MOSFET is turned off when the current ramps up
to the current limit or when the DCMAX limit is reached. Since the
highest current limit level and frequency of a InnoSwitch-CH design
are constant, the power delivered to the load is proportional to the
primary inductance of the transformer and peak primary current
squared. Hence, designing the supply involves calculating the primary
inductance of the transformer for the maximum output power
required. If the InnoSwitch-CH is appropriately chosen for the power
level, the current in the calculated inductance will ramp up to current
limit before the DCMAX limit is reached.
InnoSwitch-CH senses the output voltage on the FEEDBACK pin using
a resistive voltage divider to determine whether or not to proceed
with the next switching cycle. The sequence of cycles is used to
determine the current limit. Once a cycle is started, it always
completes the cycle. This operation results in a power supply in
which the output voltage ripple is determined by the output capacitor,
and the amount of energy per switch cycle.
CLOCK
CLOCK
DMAX
DMAX
IDRAIN
IDRAIN
VDRAIN
VDRAIN
PI-7040-101014
PI-7041-101014
Figure 8. Operation at Near Maximum Loading.
Figure 9. Operation at Moderately Heavy Loading.
CLOCK
CLOCK
DCMAX
DMAX
IDRAIN
IDRAIN
VDRAIN
VDRAIN
PI-7038-101014
Figure 10. Operation at Medium Loading.
PI-7039-101014
Figure 11. Operation at Very Light Load.
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InnoSwitch-CH
ON/OFF Operation with Current Limit State Machine
The internal clock of the InnoSwitch-CH runs all the time. At the
beginning of each clock cycle, the voltage comparator on the
FEEDBACK pin decides whether or not to implement a switch cycle,
and based on the sequence of samples over multiple cycles, it
determines the appropriate current limit. At high loads, the state
machine sets the current limit to its highest value. At lighter loads,
the state machine sets the current limit to reduced values.
supply output (Figure 9). At medium loads, cycles will be skipped and
the current limit will be reduced (Figure 10). At very light loads, the
current limit will be reduced even further (Figure 11). Only a small
percentage of cycles will occur to satisfy the power consumption of
the power supply.
The response time of the ON/OFF control scheme is very fast compared
to PWM control. This provides accurate regulation and excellent
transient response.
PI-7042-053013
200
VDC-INPUT
100
0
10
PI-2395-101014
At near maximum load, InnoSwitch-CH will conduct during nearly
all of its clock cycles (Figure 8). At slightly lower load, it will “skip”
additional cycles in order to maintain voltage regulation at the power
200
100
VDC-INPUT
0
VBPP
5
400
0
300
400
200
200
VDRAIN
100
0
0
1
Time (ms)
Figure 12. Power-Up Timing.
VDRAIN
2
0
2.5
0
5
Time (s)
Figure 13. Normal Power-Down Timing.
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Rev. K 06/20
InnoSwitch-CH
Applications Example
VAC
265
82.6
84.2
85.1
84.8
78.3
78.9
78.6
78.7
(mW)
7
7
8
9
No-Load Input
C8
100 pF
400 VAC
L2
4.7 µH
C1
1 nF
250 V
D5
RS2MA-13-F
D3
RS2MA-13-F
4
R1
200 kΩ
5 V, 2 A
6
D1
R14 DFLR1600-7
30 Ω
600 V
R4
3 kΩ
O
D4
RS2MA-13-F
NC
C5
22 µF
16 V
D6
RS2MA-13-F
t
C4
8.2 µF
400 V
T1
EE1621
InnoSwitch-CH
U1
INN2023K
D
C16
1 µF
50 V
C7
2.2 µF
25 V
R11
100 kΩ
CONTROL
S
L1
100 µH
R10
330 kΩ
D+/D-
R5
47 Ω
FWD
RT1
10 Ω
2
D2
DFLR1200-7
200 V
C2
8.2 µF
400 V
R9
34 kΩ
1%
5
1
F1
3.15 A
85 - 264
VAC
C10
560 µF
6.3 V
C9
R7 1.5 nF
20 Ω 200 V
3
R8
100 kΩ
1%
GND
Full Load
10% Load
BPS
84.2
VO
Efficiency
at PCB (%)
230
84.2
Q1
SI7478DP-T1-E3
Average
115
SR/P
85
BPP
FB
IS
C15
100 pF
100 V
C6
1 µF
25 V
RTN
PI-7424-111014
Figure 14. 5 V, 2 A Universal Input Charger.
The circuit shown in Figure 14 is a low cost, very high efficiency
charger designed to provide 5 V, 2 A CV/CC charging, using an
INN2023K integrated power supply controller.
This single 5 V output charger design features DoE Level 6 and EC
CoC 5 compliance (84% measured vs. 79% requirement) and 45 to only
32. The built-in secondary-side synchronous rectification (SR)
controller of U1, allows expensive high current Schottky barrier diodes
to be replaced with lower cost MOSFETs while increasing efficiency
and removing hot spots. With control on the secondary-side, cross
conduction problems normally associated with SR are eliminated
under all conditions.
The input stage required a small thermistor (RT1) to prevent inrush
currents exceeding the specification of D3-D6 and causing fuse F1
to open.
The total input capacitance of capacitor C2 and C4 is sufficient to
maintain full output power delivery at 85 VAC, the converter being
able to operate at the minimum DC voltage, just before the next AC
cycle refreshes the input. The DC voltage is applied to the primary
winding of T1. The other end of the primary winding is driven by the
MOSFET inside the InnoSwitch-CH IC.
A low-cost RCD clamp formed by diode D1, resistors R1 and R14, and
capacitor C1 limits the peak drain voltage of the InnoSwitch-CH IC at
the instant of turn-off of the MOSFET. The clamp helps dissipate the
energy stored in the leakage reactance of transformer T1 and
effectively limits the turn-off voltage spike at the DRAIN pin of U1 to
a safe value.
The InnoSwitch-CH IC is self-starting, using an internal high-voltage
current source to charge the PRIMARY BYPASS pin capacitor (C6)
when AC is first applied. During normal operation the primary-side
controller is powered from an auxiliary winding on the transformer
T1. Output of the auxiliary (or bias) winding is rectified using diode
D2 and filtered using capacitor C5. Resistor R4 limits the current
being supplied to the PRIMARY BYPASS pin of the InnoSwitch-CH IC
(U1) to be close to the IC supply current so as to minimize no-load
input power.
Output regulation is achieved using ON/OFF control, the number of
enabled switching cycles are adjusted based on the output load. At
high-load, most switching cycles are enabled, and at light-load or
no-load, most cycled are disabled or skipped. Once a cycle is enabled,
the MOSFET will remain on until the primary current ramps to the
device current limit for the specific operating state. There are four
operating states (current limits) arranged such that the frequency
content of the primary current switching pattern remains out of the
audible range until at light-load where the transformer flux density
and therefore audible noise generation is at a very low level.
The secondary-side of the InnoSwitch-CH IC provides output voltage,
output current sensing and drive to a MOSFET providing synchronous
rectification.
The secondary of the transformer is rectified by MOSFET Q1 and
filtered by capacitor C10. Resistor R7 and C9 limit high-frequency
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InnoSwitch-CH
ringing during switching transients that would otherwise create
radiated EMI. The gate of Q1 is turned on by secondary-side
controller inside the InnoSwitch-CH IC based on the winding voltage
sensed via resistor R5 and fed into the FORWARD pin of the IC.
Better load regulation and lower output ripple can be achieved by
matching the time constants of upper and lower feedback divider
network. As shown in Figure 15.
In continuous conduction mode of operation, Q1 is turned off just
prior to the secondary-side commanding a new switching cycle from
the primary. In discontinuous mode of operation, Q1 is turned off
when the voltage drop across the MOSFET falls below a threshold of
approximately -24 mV [VSR(TH)].
Key application Considerations
As both SR and primary MOSFET control resides on the secondaryside, any possibility of cross conduction of the two MOSFETs is
eliminated. In turn the time Q1 is on can be maximized for lowest
loss and allows removal of a parallel Schottky diode and/or the use of
a lower cost higher RDS(ON) device for the same efficiency compared to
standalone SR controllers.
The secondary-side of the InnoSwitch-CH IC is self-powered from
either the secondary winding forward voltage or the output voltage.
Capacitor C7 connected to the SECONDARY BYPASS pin of
InnoSwitch-CH IC (U1) provides decoupling for the internal circuitry.
During CC (constant current) operation, when the output voltage
falls, the device will power itself from the secondary winding directly.
During the on-time of the primary-side power MOSFET, the forward
voltage that appears across the secondary winding is used to charge
the decoupling capacitor C7 via resistor R5 and an internal regulator.
This allows output current regulation to be maintained down to 82%.
3. Minimum data sheet value of I2f.
4. Transformer primary inductance tolerance of ±10%.
5. Reflected output voltage (VOR) of 110 V.
6. Voltage only output of 12 V with a synchronous rectifier.
7. Increased current limit is selected for peak and open frame power
columns and standard current limit for adapter columns.
8. The part is board mounted with SOURCE pins soldered to a
sufficient area of copper and/or a heat sink is used to keep the
SOURCE pin temperature at or below 110 °C.
9. Ambient temperature of 50 °C for open frame designs and 40 °C
for sealed adapters.
*Below a value of 1, KP is the ratio of ripple to peak primary current.
To prevent reduced power delivery, due to premature termination of
switching cycles, a transient KP limit of ≥0.25 is recommended. This
prevents the initial current limit (IINIT) from being exceeded at
MOSFET turn-on.
Overvoltage Protection
The output overvoltage protection provided by the InnoSwitch-CH IC
uses an internal latch that is triggered by a threshold current of
approximately 7.6 mA into the PRIMARY BYPASS pin. In addition to
an internal filter, the PRIMARY BYPASS pin capacitor forms an external
filter providing noise immunity from inadvertent triggering. For the
bypass capacitor to be effective as a high frequency filter, the
capacitor should be located as close as possible to the SOURCE and
PRIMARY BYPASS pins of the device.
The primary sensed OVP function can be realized by connecting
a Zener diode from the rectified and filtered bias winding voltage
supply to the PRIMARY BYPASS pin (parallel to R4 in Figure 14).
Selecting the Zener diode voltage to be approximately 6 V above
the bias winding voltage (28 V for 22 V bias winding) gives good OVP
performance for most designs, but can be adjusted to compensate
for variations in leakage inductance. Adding additional filtering can
be achieved by inserting a low value (10 Ω to 47 Ω) resistor in series
with the bias winding diode and/or the OVP Zener diode. The resistor
in series with the OVP Zener diode also limits the maximum current
into the BYPASS pin.
Reducing No-load Consumption
The InnoSwitch-CH IC can start in self-powered mode from the
BYPASS pin capacitor charged through the internal current source.
Use of a bias winding is however required to provide supply current to
the PRIMARY BYPASS pin once the InnoSwitch-CH IC has become
operational. Auxiliary or bias winding provided on the transformer is
required for this purpose. The addition of a bias winding that provides
bias supply to the PRIMARY BYPASS pin enables design of power
supplies with no-load power consumption down to ±2000 V on all pins
Machine Model ESD
JESD22-A115C
> ±200 V on all pins
> ±100 mA or > 1.5 V (max) on all pins
Part Ordering Information
• InnoSwitch-CH Product Family
• 20x Series Number
• Package Identifier
K
eSOP-R16B
• Tape & Reel and Other Options
INN 2023 K - TL
TL
Tape & Reel, 1000 pcs min/mult.
24
Rev. K 06/20
www.power.com
InnoSwitch-CH
Revision Notes
Date
A
Initial Release.
11/14
B
Added Note 4 to Table 1, updated Auto-Restart section, added VFB(OFF) to Parameter Table, new Figure 23, added Part
Ordering Table and added Notes 6 and 7 to Absolute Maximum Ratings table.
01/15
C
Corrected secondary auto-restart from relative specification on the FEEDBACK pin to absolute threshold on the VOUT
pin, that was incorrectly documented in previous revision. Updated ISR(PD), ISR(PU) and VBPP limits based on high volume
production data.
05/15
D
Added extra information related to Cable Drop Compensation (CDC) function on page 5.
07/15
E
Updated in line with UL Report E358471. Increased Storage, Operating Junction, and Ambient Temperatures and
Secondary-Side Current Rating Parameters. Previous Note 7 in Abs Max Ratings Table is no longer required and
deleted. Updated Figure 5, page 1 and RDS(ON) Condition parameter.
08/15
F
Corrected Bottom (Left side) of PCB layout in Figure 20, SOURCE (S) Pin description on page 3, added ESD table and
eSOP-R16B Package Marking.
11/15
G
Modified page 1 sub-header text.
11/18/15
H
Corrected OUTPUT VOLTAGE Pin Auto-Restart Threshold section. Improved VOUT(AR) limits tolerance, 3.5 V Max.
12/04/15
I
Added Pin 8 and Pin 9 information under Pin Functional Description on page 3.
04/17
J
Corrected error in Figure 4. Updated text and added 4 new waveform schematics in Bias Winding and External Bias
Circuit section. Added 1 new figure in Applications Example section.
10/17
K
Updated safety information on page 1.
06/20
25
www.power.com
Rev. K 06/20
For the latest updates, visit our website: www.power.com
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations
does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY
HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one
or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of
Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set
forth at www.power.com/ip.htm.
Life Support Policy
POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:
1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose
failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or
death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness.
Power Integrations, the Power Integrations logo, CAPZero, ChiPhy, CHY, DPA-Switch, EcoSmart, E-Shield, eSIP, eSOP, HiperPLC, HiperPFS,
HiperTFS, InnoSwitch, Innovation in Power Conversion, InSOP, LinkSwitch, LinkZero, LYTSwitch, SENZero, TinySwitch, TOPSwitch, PI, PI Expert,
PowiGaN, SCALE, SCALE-1, SCALE-2, SCALE-3 and SCALE-iDriver, are trademarks of Power Integrations, Inc. Other trademarks are property of
their respective companies. ©2020, Power Integrations, Inc.
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