INN21x3-21x5
InnoSwitch-CE Family
Off-Line CV/CC Flyback Switcher IC with Integrated 650 V MOSFET,
Sync-Rect and Feedback with High Output Current (>2 A) Capability
Product Highlights
Highly Integrated, Compact Footprint
• Incorporates flyback controller, 650 V MOSFET, secondary-side
sensing and synchronous rectification driver
SR FET
• FluxLink™ integrated, HIPOT-isolated, feedback link
• Exceptional CV accuracy, tolerant of transformer and board
• 3,500 VAC
UL1577 and TUV (EN60950) safety approved
EN61000-4-8 (100 A/m) and EN61000-4-9 (1000 A/m) compliant
Green Package
Figure 2. High Creepage, Safety-Compliant eSOP Package.
• Halogen free and RoHS compliant
Applications
• High current charger and adapters for mobile devices
• Consumer electronics − set top boxes, networking, gaming, LED
Description
Output Power Table
85-265 VAC
The InnoSwitch™-CE family of ICs dramatically simplify the development
and manufacturing of low-voltage, high current power supplies,
particularly those in compact enclosures or with high efficiency requirements. The InnoSwitch-CE architecture is revolutionary in that the
devices incorporate both primary and secondary controllers, with sense
elements and a safety-rated feedback mechanism into a single IC.
Close component proximity and innovative use of the integrated
communication link permit accurate control of both a secondary-side
synchronous rectification MOSFET and optimization of primary-side
MOSFET switching. This improves system reliability, maximizes
efficiency across the power range from full load to low-power standby.
Product 4
Adapter1
Peak or
Open Frame1,2
INN21x3K
3
12 W
15 W
INN21x4K
3
15 W
20 W
INN21x5K
3
20 W
25 W
Table 1. Output Power Table.
Notes:
1. Minimum continuous power in a typical non-ventilated enclosed typical size
adapter measured at 40 °C ambient. Max output power is dependent on the
design. With condition that package temperature must be < = 125 °C.
2. Minimum peak power capability.
3. x = 0 (no cable compensation), x = 2 (300 mV cable compensation).
4. Package: K: eSOP-R16B.
www.power.com
February 2016
This Product is Covered by Patents and/or Pending Patent Applications.
INN21x3-21x5
PRIMARY BYPASS
(BPP)
DRAIN
(D)
REGULATOR
5.95 V
FAULT
PRESENT
INPUT VOLTAGE
MONITOR (V)
LINE-SENSE
AUTORESTART
COUNTER
UV
OV
BYPASS PIN
UNDERVOLTAGE
+
BYPASS
CAPACITOR
SELECT AND 5.95 V
5.39
V
CURRENT
LIMIT STATE
MACHINE
RESET
VI
LIMIT
CURRENT LIMIT
COMPARATOR
+
JITTER
CLOCK
THERMAL
SHUTDOWN
DCMAX
FROM
FEEDBACK
DRIVER
OSCILLATOR
PRI/SEC
RECEIVER
CONTROLLER
PULSE
DCMAXS
S
Q
R
Q
6.4 V
LEADING
EDGE
BLANKING
OVP
LATCH
20 Ω
PI-7453-121114
SOURCE
(S)
Figure 3. Primary-Side Controller Block Diagram.
OUTPUT
VOLTAGE
(VO)
FORWARD
(FWD)
REGULATOR
4.45 V
DETECTOR
SCONDARY
BYPASS
(BPS)
HAND SHAKE
PULSES
+
4.45 V
3.80 V
FEEDBACK
(FB)
CONTROL
-
+
-
CABLE
COMPENSATION
ISENSE
(IS)
FEEDBACK
DRIVER
+
IS THRESHOLD
-
CLOCK
OSCILLATOR
SYNC RECT
(SR)
TO
RECEIVER
ENB
Q
S
Q
R
ENABLE
SR
+
-
SR
THESHOLD
SECONDARY
GROUND
(GND)
PI-7813-120215
Figure 4.
Secondary-Side Controller Block Diagram.
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INN21x3-21x5
Pin Functional Description
InnoSwitch-CE Functional Description
DRAIN (D) Pin (Pin 1)
This pin is the power MOSFET drain connection.
The InnoSwitch-CE combines a high-voltage power MOSFET switch,
along with both primary-side and secondary-side controllers in one
device. It has a novel inductive coupling feedback scheme using the
package leadframe and bond wires to provide a reliable and low-cost
means to provide accurate direct sensing of the output voltage and
output current on the secondary to communicate information to the
primary IC. Unlike conventional PWM (pulse width modulated)
controllers, it uses a simple ON/OFF control to regulate the output
voltage and current. The primary controller consists of an oscillator, a
receiver circuit magnetically coupled to the secondary controller, current
limit state machine, 5.95 V regulator on the PRIMARY BYPASS pin,
overvoltage circuit, current limit selection circuitry, over temperature
protection, leading edge blanking and a 650 V power MOSFET. The
InnoSwitch-CE secondary controller consists of a transmitter circuit that
is magnetically coupled to the primary receiver, constant voltage (CV)
and constant current (CC) control circuitry, a 4.4 V regulator on the
SECONDARY BYPASS pin, synchronous rectifier MOSFET driver,
frequency jitter oscillator and a host of integrated protection features.
Figures 3 and 4 show the functional block diagrams of the primary and
secondary controllers with the most important features.
SOURCE (S) Pin (Pin 3-6)
This pin is the power MOSFET source connection. It is also the
ground reference for the PRIMARY BYPASS pin.
PRIMARY BYPASS (BPP) Pin (Pin 7)
It is the connection point for an external bypass capacitor for the
primary-side controller IC supply.
INPUT VOLTAGE MONITOR (V) Pin (Pin 8)
A 8 MW resistor is tied between the pin and the input bulk capacitor
to provide input under and overvoltage protection.
FORWARD (FWD) Pin (Pin 10)
The connection point to the switching node of the transformer output
winding for sensing and other functions.
OUTPUT VOLTAGE (VOUT) Pin (Pin 11)
This pin is connected directly to the output voltage of the power
supply to provide bias to the secondary IC.
SYNCHRONOUS RECTIFIER DRIVE (SR) Pin (Pin 12)
Connection to external SR FET gate terminal.
SECONDARY BYPASS (BPS) Pin (Pin 13)
It is the connection point for an external bypass capacitor for the
secondary-side controller supply.
FEEDBACK (FB) Pin (Pin 14)
This pin connects to an external resistor divider to set the power
supply CV voltage regulation threshold.
SECONDARY GROUND (GND) (Pin 15)
Ground connection for the secondary IC.
ISENSE (IS) Pin (Pin 16)
Connection to the power supply output terminals. An external
current sense resistor is connected between this pin and the SECONDARY GROUND pin.
If secondary current sense is not required, the ISENSE pin should be
connected to the SECONDARY GROUND pin.
D1
S 3-6
BPP 7
V8
16 IS
15 GND
14 FB
13 BPS
12 SR
11 VOUT
10 FWD
9 NC
PI-7454-082715
PRIMARY BYPASS Pin Regulator
The PRIMARY BYPASS pin has an internal regulator that charges the
PRIMARY BYPASS pin capacitor to VBPP by drawing current from the
voltage on the DRAIN pin whenever the power MOSFET is off. The
PRIMARY BYPASS pin is the internal supply voltage node. When the
power MOSFET is on, the device operates from the energy stored in
the PRIMARY BYPASS pin capacitor. Extremely low power consumption of the internal circuitry allows the InnoSwitch-CE to operate
continuously from current it takes from the DRAIN pin.
In addition, there is a shunt regulator clamping the PRIMARY BYPASS
pin voltage to VSHUNT when current is provided to the PRIMARY BYPASS
pin through an external resistor. This facilitates powering the
InnoSwitch-CE externally through a bias winding to decrease the
no-load consumption to less than 10 mW (5V output design).
PRIMARY BYPASS Pin Capacitor Selection
The PRIMARY BYPASS pin can use a ceramic capacitor as small as
0.1 mF for decoupling the internal power supply of the device.
A larger capacitor size can be used to adjust the current limit. A 1 mF
capacitor on the PRIMARY BYPASS pin will select a higher current limit
equal to the standard current of the next larger device. A 10 mF
capacitor on the PRIMARY BYPASS pin selects a lower current limit
equal to the standard current limit of the next smaller device.
PRIMARY BYPASS Pin Undervoltage Threshold
The PRIMARY BYPASS pin undervoltage circuitry disables the power
MOSFET when the PRIMARY BYPASS pin voltage drops below
VBPP-VBPP(H) in steady-state operation. Once the PRIMARY BYPASS pin
voltage falls below this threshold, it must rise back to VBPP to enable
(turn-on) the power MOSFET.
PRIMARY BYPASS Pin Output Overvoltage Latching Function
The PRIMARY BYPASS pin has an OV protection latching feature.
A Zener diode in parallel to the resistor in series with the PRIMARY
BYPASS pin capacitor is typically used to detect an overvoltage on the
primary bias winding to activate this protection mechanism. In the
event the current into the PRIMARY BYPASS pin exceeds (ISD) the
device will disable the power MOSFET switching. The latching
condition is reset by bringing the primary bypass below the reset
threshold voltage (VBPP(RESET)).
Figure 5. Pin Configuration.
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INN21x3-21x5
Over-Temperature Protection
The thermal shutdown circuitry senses the primary die temperature.
This threshold is typically set to 142 °C with 75 °C hysteresis. When
the die temperature rises above this threshold the power MOSFET is
disabled and remains disabled until the die temperature falls by 75 °C,
at which point it is re-enabled. A large hysteresis of 75 °C is provided
to prevent over-heating of the PC board due to continuous fault
condition.
Current Limit Operation
The current limit circuit senses the current in the power MOSFET.
When this current exceeds the internal threshold (ILIMIT), the power
MOSFET is turned off for the remainder of that switch cycle. The
current limit state-machine reduces the current limit threshold by
discrete amounts under medium and light loads.
The leading edge blanking circuit inhibits the current limit comparator
for a short time (tLEB) after the power MOSFET is turned-on. This
leading edge blanking time has been set so that current spikes
caused by capacitance and secondary-side rectifier reverse recovery
time will not cause premature termination of the switching pulse.
Each switching cycle is terminated when the Drain current of the
primary power MOSFET reaches the current limit of the device.
the primary goes into auto-restart and repeats. However under
normal conditions, the secondary chip will power-up through the
FORWARD pin or directly from VOUT and then take over control.
From then onwards the secondary is in control of demanding
switching cycles when required.
The handshake flowchart is shown in Figure 6 below.
In the event the primary stops switching or does not respond to cycle
requests from the secondary during normal operation when the
secondary has control, the handshake protocol is initiated to ensure
that the secondary is ready to assume control once the primary
begins switching again. This protocol for an additional handshake is
also invoked in the event the secondary detects that the primary is
providing more cycles than were requested.
P: Primary Chip
S: Secondary Chip
Start
P: Powered Up, Switching
S: Powering Up
Auto-Restart
In the event of a fault condition such as output overload, output
short-circuit or external component/pin fault, the InnoSwitch-CE
enters into auto-restart (AR) operation. In auto-restart operation the
power MOSFET switching is disabled for t AR(OFF). There are 2 ways to
enter auto-restart:
P: Auto-Restart
S: Powering Up
2s
1. Continuous switching requests from the secondary for time period
exceeding t AR.
S: Has powered
up within 64 ms?
2. No requests for switching cycles from the secondary for a time
period exceeding t AR(SK).
The first condition corresponds to a condition wherein the secondary
controller makes continuous cycle requests without a skipped-cycle
for more than t AR time period. The second method was included to
ensure that if communication is lost, the primary tries to restart
again. Although this should never be the case in normal operation,
this can be useful in the case of system ESD events for example
where a loss of communication due to noise disturbing the secondary
controller, is resolved when the primary restarts after an auto-restart
off time.
The auto-restart alternately enables and disables the switching of the
power MOSFET until the fault is removed. The auto-restart counter is
gated by the switch oscillator in SOA mode the auto-restart off timer
may appear to be longer.
The auto-restart counter is reset once the primary PRIMARY BYPASS
pin falls below the undervoltage threshold VBPP-VBPP(HYS).
Safe-Operating-Area (SOA) Protection
In the event there are two consecutive cycles where the primary
power MOSFET switch current reaches current limit (ILIM) within the
blanking (tLEB) and current limit (tILD) delay time, the controller will
skip approximately 2.5 cycles or ~25 msec. This provides sufficient
time for reset of the transformer without sacrificing start-up time into
large capacitive load. Auto-restart timing is increased when the
device is operating in SOA-mode.
Primary-Secondary Handshake Protocol
At start-up, the primary initially switches without any feedback
information (this is very similar to the operation of a standard
TOPSwitch™, TinySwitch™ or LinkSwitch™ controllers). If no
feedback signals are received during the auto-restart on-time,
No
P: Goes to Auto-Restart Off
S: Bypass Discharging
Yes
64 ms
P: Switching
S: Sends Handshaking Pulses
P: Has Received
Handshaking
Pulses
No
P: Continuous Switching
S: Doesn’t Take Control
No
P: Not Switching
S: Doesn’t Take Control
Yes
P: Stops Switching, Hands
Over Control to Secondary
S: Has Taken
Control?
Yes
End of Handshaking,
Secondary Control Mode
PI-7416-102814
Figure 6.
Primary –Secondary Handshake Flowchart.
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INN21x3-21x5
In the event the secondary does not detect that the primary responds
to requests for 6 consecutive cycles, or if the secondary detects that
the primary is switching without cycle requests for 6 or more
consecutive cycles, the secondary controller will initiate a second
handshake sequence.
This protection mode also provides additional protection against
cross-conduction of the SR MOSFET while the primary is switching.
This protection mode also prevents output overvoltage in the event
the primary is reset while the secondary is still in control and light/
medium load conditions exist.
Line Voltage Monitor
The VOLTAGE MONITOR pin is used for input under and overvoltage
sensing and protection function.
A 8 MW resistor is tied between the high voltage bulk DC capacitor
after the bridge or connected through a set of diodes from the AC
side of bridge and small high-voltage capacitor and bleed resistor
(for fast AC reset) and VOLTAGE MONITOR pin to enable this function.
To disable this function the VOLTAGE MONITOR pin should be tied to
the PRIMARY BYPASS pin.
At power-up after the BPP is charged and the ILIM is latched, prior to
switching the state of VOLTAGE MONITOR pin current is checked to
determine that it is above brown-in (IUV+) And below the overvoltage
shutdown threshold (IOV+) To proceed with start-up.
If during normal operation the VOLTAGE MONITOR pin current falls
below the brown-out (IUV-) threshold and remains below brown-in
(IUV+) for longer than tUV- the controller enters into auto-restart with
a short auto-restart off-time (~200 ms). Switching will only resume
once the VOLTAGE MONITOR pin current is above the brown-in
threshold (IUV+) for a time period exceeding ~150 ms.
In the event during normal operation the VOLTAGE MONITOR pin
current is above the overvoltage threshold (IOV+) for longer than tOV,
the controller will enter auto-restart with a short auto-restart off-time
(~200 ms). Switching will only resume once the VOLTAGE MONITOR
pin current fall below (IOV-) for a time period exceeding ~150 ms.
Secondary Controller
Once the device enters the short auto-restart OFF-time, the PRIMARY
BYPASS pin will activate an internal bleed to discharge the input bulk
capacitor. The feedback driver block is the drive to the FluxLink
communication loop transferring switching pulse requests to the
primary IC.
As shown in the block diagram in Figure 4, the secondary controller
is powered through a 4.45 V Regulator block by either VOUT or
FORWARD pin connections to the SECONDARY BYPASS pin. The
SECONDARY BYPASS pin is connected to an external decoupling
capacitor and fed internally from the regulator block.
The FORWARD pin also connects to the negative edge detection
block used for both handshaking and timing to turn on the synchronous rectifier MOSFET (SR FET) connected to the SYNCHRONOUS
RECTIFIER DRIVE pin. The FORWARD pin is also used to sense when
to turn off the SR FET in discontinuous mode operation when the
voltage across the FET on resistance drops below VSR(TH).
In continuous mode operation the SR FET is turned off when the
pulse request is sent to demand the next switching cycle, providing
excellent synchronization free of any overlap for the FET turn-off
while operating in continuous mode.
The mid-point of an external resistor divider network between the
VOUT and SECONDARY GROUND pins is tied to the FEEDBACK pin
to regulate the output voltage. The internal voltage comparator
reference voltage is VREF (1.265 V).
The external current sense resistor connected between IS and
SECONDARY GROUND pins is used to regulate the output current in
constant current regulator mode. The internal current sense
comparator threshold is ISVTH used to determine the value at which
the power supply output current is regulated.
Secondary Controller Oscillator
The typical oscillator frequency is internally set to an average
frequency of 100 kHz.
The oscillator incorporates circuitry that introduces a small amount of
frequency jitter, typically 6 kHz peak-to-peak, to minimize EMI
emission. The modulation rate of the frequency jitter is set to 1 kHz
to optimize EMI reduction for both average and quasi-peak emissions.
Output Overvoltage Protection
In the event the sensed voltage on the FEEDBACK pin is 2% higher
than the regulation threshold, a bleed current of ~10 mA is applied on
the VOUT pin. This bleed current increases to ~140 mA in the event
the FEEDBACK pin voltage is raised to beyond ~20% of the internal
FEEDBACK pin reference voltage. The current sink on the VOUT pin
is intended to discharge the output voltage for momentary overshoot
events. The secondary does not relinquish control to the primary
during this mode of operation.
FEEDBACK Pin Short Detection
In the event the FEEDBACK pin voltage is below the VFB(OFF) threshold
at start-up, the secondary will complete the primary/secondary handshake and will stop requesting pulses to initiate an auto-restart. The
secondary will stop requesting cycles for t AR(SK), to begin primary-side
auto-restart of t AR(OFF)SH. In this condition, the total apparent AR
off-time is t AR(SK) + t AR(OFF)SH. During normal operation, the secondary
will stop requesting pulses from the primary to initiate an auto-restart
cycle when the FEEDBACK pin voltage falls below VFB(OFF) threshold.
The deglitch filter on the VFB(OFF) is less than 10 msec. The secondary
will relinquish control after detecting the FEEDBACK pin is shorted to
ground.
Cable Drop Compensation (CDC)
The amount of cable drop compensation is a function of the load with
respect to the constant current regulation threshold as illustrated in
Figure 7.
VOUT + φCD
Output Voltage
End of PCB
The most likely event that could require an additional handshake is
when the primary stops switching resulting from a momentary line
drop-out or brown-out event. When the primary resumes operation,
it will default into a start-up condition and attempt to detect handshake pulses from the secondary.
Cable Drop
Compensation
VOUT
No-Load
Load Current
Onset of CC
Regulation
PI-7863-010516
Figure 7.
Cable Drop Compensation Characteristics.
The lower feedback pin resistor must be tied to the SECONDARY
GROUND pin (not ISENSE pin) to have output cable drop compensation enabled.
5
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Rev. A 02/16
INN21x3-21x5
OUTPUT VOLTAGE Pin Auto-Restart Threshold
The VOUT pin also includes a comparator to detect when the output
voltage falls below the VOUT(AR) threshold for a duration exceeding
tVOUT(AR). The secondary controller will relinquish control when it
detects the FEEDBACK pin has fallen below VOUT(AR) for a time duration
longer than tVOUT(AR). This threshold is meant to limit the range of
constant current (CC) operation.
SR Disable Protection
On a cycle by cycle basis the SR is only engaged in the event a cycle
was requested by the secondary controller and the negative edge is
detected on the FORWARD pin. In the event the voltage on the
ISENSE pin exceeds approximately 3 times the ISVTH threshold, the SR
MOSFET drive is disabled until the surge current has diminished to
nominal levels.
Output Constant-Current Regulation
The InnoSwitch-CE regulates the output current through a resistor
between the ISENSE and SECONDARY GROUND pins. If constant
current regulation is not required, this pin must be tied to the
GROUND pin.
InnoSwitch-CE Operation
InnoSwitch-CE devices operate in the current limit mode. When
enabled, the oscillator turns the power MOSFET on at the beginning
of each cycle. The MOSFET is turned off when the current ramps up
CLOCK
CLOCK
DMAX
DMAX
IDRAIN
IDRAIN
VDRAIN
VDRAIN
PI-7040-101014
PI-7041-101014
Figure 9. Operation at Moderately Heavy Loading.
Figure 8. Operation at Near Maximum Loading.
CLOCK
CLOCK
DCMAX
DMAX
IDRAIN
IDRAIN
VDRAIN
VDRAIN
PI-7038-101014
Figure 10. Operation at Medium Loading.
PI-7039-101014
Figure 11. Operation at Very Light Load.
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Rev. A 02/16
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INN21x3-21x5
InnoSwitch-CE senses the output voltage on the FEEDBACK pin using
a resistive voltage divider to determine whether or not to proceed
with the next switching cycle. The sequence of cycles is used to
determine the current limit. Once a cycle is started, it always
completes the cycle. This operation results in a power supply in
which the output voltage ripple is determined by the output capacitor,
and the amount of energy per switch cycle.
PI-7042-053013
200
VDC-INPUT
100
0
ON/OFF Operation with Current Limit State Machine
The internal clock of the InnoSwitch-CE runs all the time. At the
beginning of each clock cycle, the voltage comparator on the
FEEDBACK pin decides whether or not to implement a switch cycle,
and based on the sequence of samples over multiple cycles, it
determines the appropriate current limit. At high loads, the state
machine sets the current limit to its highest value. At lighter loads,
the state machine sets the current limit to reduced values.
At near maximum load, InnoSwitch-CE will conduct during nearly
all of its clock cycles (Figure 8). At slightly lower load, it will “skip”
additional cycles in order to maintain voltage regulation at the power
supply output (Figure 9). At medium loads, cycles will be skipped and
the current limit will be reduced (Figure 10). At very light loads, the
current limit will be reduced even further (Figure 11). Only a small
percentage of cycles will occur to satisfy the power consumption of
the power supply.
The response time of the ON/OFF control scheme is very fast
compared to PWM control. This provides accurate regulation and
excellent transient response.
PI-2395-101014
to the current limit or when the DCMAX limit is reached. Since the
highest current limit level and frequency of a InnoSwitch-CE design
are constant, the power delivered to the load is proportional to the
primary inductance of the transformer and peak primary current
squared. Hence, designing the supply involves calculating the
primary inductance of the transformer for the maximum output power
required. If the InnoSwitch-CE is appropriately chosen for the power
level, the current in the calculated inductance will ramp up to current
limit before the DCMAX limit is reached.
200
10
100
VBPP
5
VDC-INPUT
0
0
400
400
300
200
VDRAIN
VDRAIN
200
0
0
1
Time (ms)
Figure 12. Power-Up.
2
100
0
2.5
0
5
Time (s)
Figure 13. Normal Power-Down Timing.
7
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Rev. A 02/16
INN21x3-21x5
Applications Example
C10
100 pF
250 VAC
L2
Ferrite Bead
5 V, 3 A
5
4
C12
470 µF
6.3 V
BR1
DF206ST-G
600 V
R6
200 kΩ
1%
C9
2.2 nF
200 V
3
R13
200 kΩ
1%
C13
470 µF
6.3 V
6
R10
C11
10 Ω 1.5 nF
1/8 W 200 V
R7
15 Ω
C1
33 nF
630 V
O
FL1
R3
22.1 Ω
1%
C2
15 µF
400 V
T1
EE1621
F1
1A
N
R4
2.32 kΩ
1%
C5
22 µF
25 V
D2
DFLR1200-7
200 V
R1
4.70 MΩ
1%
C3
15 µF
400 V
VR1
DZ2S15000L
15 V
L
85 - 265
VAC
R5
10 Ω
R8
47 Ω
1/10 W
C6
100 pF
50 V
D
V
C14
1000 pF
100 V
C7
1.5 µF
25 V
R2
3.30 MΩ
1%
CONTROL
S
L3
100 µH
C15
1 µF
25 V
BPS
1
BPP
C4
100 nF
25 V
R11
1 kΩ
1%
GND
2
4
VO
t
3
SR/P
RT1
5Ω
Q1
SI7460DP-T1-GE3
1
FWD
L1
150 µH
D1
RS1J
R12
105 kΩ
1%
FB
InnoSwitch-CE
U1
INN2124K
IS
R9
0.009 Ω
1%
C8
330 pF
50 V
R13
34.8kΩ
1%
0V
PI-7855-010616
Figure 14. 5 V, 3 A Charger/Adapter.
The circuit shown in Figure 14 is a low cost 5 V, 3 A power supply
using INN2124K. This single output design features DOE Level 6 and
EC CoC 5 compliance. The integration offered by InnoSwitch-CE
reduces component count from >50 to only 41.
Bridge rectifier BR1 rectifies the AC input supply. Capacitors C2 and
C3 provide filtering of the rectified AC input and together with
inductor L3 form a pi-filter to attenuate differential mode EMI.
Capacitor C15 connected at the power supply output with input
common mode choke help to reduce common mode EMI.
Thermistor RT1 limits the inrush current when the power supply is
connected to the input AC supply.
Input fuse F1 provides protection against excess input current
resulting from catastrophic failure of any of the components in the
power supply. One end of the transformer primary is connected to
the rectified DC bus; the other is connected to the drain terminal of
the MOSFET inside the InnoSwitch-CE IC (U1).
A low-cost RCD clamp formed by diode D1, resistors R6, R7 and R13
and capacitor C9 limits the peak drain voltage of U1 at the instant of
turn-off of the MOSFET inside U1. The clamp helps to dissipate the
energy stored in the leakage reactance of transformer T1.
The InnoSwitch-CE IC is self-starting, using an internal high-voltage
current source to charge the BPP pin capacitor (C4) when AC is first
applied. During normal operation the primary-side block is powered
from an auxiliary winding on the transformer T1. Output of the
auxiliary (or bias) winding is rectified using diode D2 and filtered using
capacitor C5. Resistor R4 limits the current being supplied to the BPP
pin of InnoSwitch-CE IC (U1).
Output regulation is achieved using On/Off control, the number of
enabled switching cycles are adjusted based on the output load.
At high load, most switching cycles are enabled, and at light load or
no-load, most cycled are disabled or skipped. Once a cycle is
enabled, the MOSFET will remain on until the primary current ramps
to the device current limit for the specific operating state. There are
four operating states (current limits) arranged such that the frequency
content of the primary current switching pattern remains out of the
audible range until at light load where the transformer flux density
and therefore audible noise generation is at a very low level.
The secondary-side of the InnoSwitch-CE IC provides output voltage,
output current sensing and drive to a MOSFET providing synchronous
rectification. The secondary of the transformer is rectified by SR FET
Q1 and filtered by capacitors C12 and C13. High frequency ringing
during switching transients that would otherwise create radiated EMI
is reduced via a snubber (resistor R10 and capacitor C11).
Synchronous rectification (SR) is provided by MOSFET Q1. The gate
of Q1 is turned on by secondary-side controller inside IC U1, based on
the winding voltage sensed via resistor R8 and fed into the FWD pin
of the IC.
In continuous conduction mode of operation, the MOSFET is turned
off just prior to the secondary-side commanding a new switching
cycle from the primary. In discontinuous mode of operation, the
power MOSFET is turned off when the voltage drop across the
MOSFET falls below a threshold of approximately -24 mV. Secondaryside control of the primary-side power MOSFET avoids any possibility
of cross conduction of the two MOSFETs and provides extremely
reliable synchronous rectification.
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INN21x3-21x5
The secondary-side of the IC is self-powered from either the
secondary winding forward voltage or the output voltage. Capacitor
C7 connected to the BPS pin of InnoSwitch-CE IC U1, provides
decoupling for the internal circuitry.
During CC operation, when the output voltage falls, the device will
power itself from the secondary winding directly. During the on-time
of the primary-side power MOSFET, the forward voltage that appears
across the secondary winding is used to charge the decoupling
capacitor C7 via resistor R8 and an internal regulator. This allows
output current regulation to be maintained down to ~3 V. Below this
level the unit enters auto-restart until the output load is reduced.
Output current is sensed between the IS and GND pins with a
threshold of approximately 35 mV to reduce losses. Once the current
sense threshold is exceeded the device adjusts the number of switch
pulses to maintain a fixed output current. During a fault condition
such as short-circuit of output, a large current will flow through the
current sense resistor R9 due to discharge of the output capacitors
C12 and C13 through the short-circuit.
The output voltage is sensed via resistor divider R12 and R13.
Output voltage is regulated so as to achieve a voltage of 1.265 V on
the FEEDBACK pin. Resistor R11 and capacitor C14 form a phase lead
network that ensure stable operation and minimize output voltage
overshoot and undershoot during transient load conditions. Capacitor
C8 provides noise filtering of the signal at the FEEDBACK pin.
Resistor R1 and R2 provide line voltage sensing and provide a current
to U1, which is proportional to the DC voltage across capacitor C3. At
approximately 100 V DC, the current through these resistors exceeds
the line undervoltage threshold, which results in enabling of U1.
At approximately 435 VDC, the current through these resistors
exceeds the line overvoltage threshold, which results in disabling of U1.
Key application Considerations
Output Power Table
The data sheet output power table (Table 1) represents the minimum
practical continuous output power level that can be obtained under
the following assumed conditions:
1. The minimum DC input voltage is 90 V or higher for 85 VAC input,
2.
3.
4.
5.
6.
7.
or 220 V or higher for 230 VAC input or 115 VAC with a voltage
doubler. The value of the input capacitance should be sized to
meet these criteria for AC input designs.
Efficiency of >82%.
Minimum data sheet value of I2f.
Transformer primary inductance tolerance of ±10%.
Reflected output voltage (VOR) of 110 V.
Voltage only output of 12 V with a synchronous rectifier.
Increased current limit is selected for peak and open frame power
columns and standard current limit for adapter columns.
The part is board mounted with SOURCE pins soldered to a
sufficient area of copper and/or a heat sink is used to keep the
SOURCE pin temperature at or below 110 °C.
Ambient temperature of 50 °C for open frame designs and 40 °C
for sealed adapters.
an internal filter, the PRIMARY BYPASS pin capacitor forms an external
filter providing noise immunity from inadvertent triggering. For the
bypass capacitor to be effective as a high frequency filter, the
capacitor should be located as close as possible to the SOURCE and
PRIMARY BYPASS pins of the device.
The primary sensed OVP function can be realized by connecting
a Zener diode from the rectified and filtered bias winding voltage
supply to the PRIMARY BYPASS pin (parallel to R4 in Figure 14).
Selecting the Zener diode voltage to be approximately 6 V above
the bias winding voltage (28 V for 22 V bias winding) gives good OVP
performance for most designs, but can be adjusted to compensate
for variations in leakage inductance. Adding additional filtering can
be achieved by inserting a low value (10 Ω to 47 Ω) resistor in series
with the bias winding diode and/or the OVP Zener diode. The resistor
in series with the OVP Zener diode also limits the maximum current
into the BYPASS pin.
Reducing No-load Consumption
The InnoSwitch-CE IC can start in self-powered mode from the
BYPASS pin capacitor charged through the internal current source.
Use of a bias winding is however required to provide supply current to
the PRIMARY BYPASS pin once the InnoSwitch-CE IC has become
operational. Auxiliary or bias winding provided on the transformer is
required for this purpose. The addition of a bias winding that provides
bias supply to the PRIMARY BYPASS pin enables design of power
supplies with no-load power consumption down to 8 mm) between the
primary-side and secondary-side circuits to enable easy compliance
with any ESD / hi-pot requirements.
The spark gap is best placed between output positive rail and one
of the AC inputs directly. In this configuration a 5.5 mm spark gap is
often sufficient to meet the creepage and clearance requirements of
many applicable safety standards. This is less than the primary to
secondary spacing because the voltage across spark gap does not
exceed the peak of the AC input.
Drain Node
The drain switching node is the dominant noise generator. As such
the components connected the drain node should be placed close to
the IC and away from sensitive feedback circuits. The clamp circuit
components should be located physically away from the PRIMARY
BYPASS pin and associated circuit and trace lengths in this circuit
should be minimized.
The loop area of the loop comprising of the input rectifier filter
capacitor, the primary winding and the InnoSwitch-CE IC primary-side
MOSFET should be kept as small as possible.
Figure 14 shows a design example for an InnoSwitch-CE IC based
power supply design. Considerations provided in this design are
marked in the figure and are listed below:
Recommendations for EMI Reduction
1. Appropriate component placement and small loop areas of the
primary and secondary power circuits help minimize radiated and
conducted EMI. Care should be taken to achieve a compact loop
area for these loops.
2. A small capacitor in parallel to the clamp diode on the primary
side can help reduced radiated EMI.
3. A resistor in series with the bias winding helps reduce radiated EMI.
4. Common mode chokes are typically required at the input of the
power supply to sufficiently attenuate common mode noise. The
same can be achieved by using shield windings on the transformer.
Shield windings can also be used in conjunction with common
mode filter inductors at input to achieve improved conducted and
radiated EMI margins.
5. Values of components of the RC snubber connected across the
output SR MOSFET can help reduce high frequency radiated and
conducted EMI.
6. A π filter comprising of differential inductors and capacitors can
be used in the input rectifier circuit to reduce low frequency
differential EMI.
7. A 1 µF ceramic capacitor when connected at the output of the
power supply helps to reduce radiated EMI.
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INN21x3-21x5
Place VOLTAGE pin sense
resistor close to the
VOLTAGE pin
Place BPP and BPS
capacitors near the IC
Maximize drain
area of SR FET for
good heat sinking
Keep output SR FET
and filter capacitor
traces short
Keep drain and
clamp loop short
Place forward and
feedback sense
resistors near the IC
Maximize source area for good heat
sinking via to the pass heat to copper layout
on the other side of the board
PCB – Bottom Side
5.5 mm gap [6.4 mm
for 5000 m altitude
compliant design]
Place slots between
primary and secondary
components for ESD
immunization – no arcing
to InnoSwitch-EP pins
PCB – Top Side
Optional Y capacitor
connection to the plus Bulk
rail on the primary-side for
surge protection
PI-7688-111815
Figure 17. PCB Layout Guidelines. Bottom (Left Side), Top (Right Side).
Recommendations for Audible Noise Suppression
The state machine used in the InnoSwitch-CE IC automatically
adjusts the current limit so as to adjust the operating frequency at
light load. This helps to eliminate audible noise that typically results
from intermittent switching of the power supply at very light loads.
In case of audible noise from a power supply, following should be
considered as guidelines for audible noise reduction:
1. Ensure that the flyback transformers are dip varnished.
2. Often the source of audible noise are ceramic capacitors. Check
both the bias winding and primary-side clamp capacitors. To find
the source substitute the clamp capacitor with a metalized film
type and the bias with an electrolytic type. By far the most
common source is the bias capacitor.
3. If the noise is generated by the bias winding filter capacitor,
generally, use of a capacitor of higher voltage rating will typically
resolve the issue. If the circuit board layout and any physical
13
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INN21x3-21x5
enclosure size constraints, allow, an electrolytic capacitor should
be used instead.
4. Reducing the AC flux density (∆B) of the transformer will also lead
to reduction in audible noise from the core.
5. If the secondary-winding is terminated with flying leads verify if
the wires as vibrating against the bobbin or each other.
6. If the circuit board shows any signs of pulse bunching (multiple
switching cycles followed by no switching activity), this could be
a cause of audible noise. Pulse bunching can be caused by
incorrect circuit board layout in which the feedback node is being
affected by switching noise. Guidelines provided for FEEDBACK
pin decoupling and the phase lead RC network described in this
note can be evaluated. Verify the board layout recommendations
associated with feedback divider network have been followed.
It is recommended that cores with low loss should only be used as
power supply designs are often thermally challenged due to the small
enclosure requirement.
Recommendations for Transformer Design
For designs using triple insulated wire it may still be necessary to use
a small margin in order to meet the required safety creepage
distances. Typically many bobbins exist for each core size and each
will have different mechanical spacing. Refer to the bobbin data
sheet or seek guidance from your safety expert or transformer
vendor to determine what specific margin is required.
Transformer design must ensure that the power supply is able to
deliver the rated power at the lowest operating voltage. The lowest
voltage on the rectified DC bus of the power supply depends on the
capacitance of the filter capacitor used. At least 2 mF / W is recommended to keep the DC bus voltage always above 70 V though 3 mF/W
provides sufficient margin. The ripple on the DC bus should be
measured and care should be taken to verify this voltage to confirm
the design calculations for transformer primary-winding inductance
selection.
Reflected Output Voltage, VOR (V)
This parameter is the secondary-winding voltage during the diode/SR
conduction time reflected back to the primary through the turns ratio
of the transformer. A VOR of 60 V is ideal for most 5 V only designs.
For design optimization purposes, the following should be kept in mind:
1. Higher VOR allows increased power delivery at VMIN, which
minimizes the value of the input capacitor and maximizes power
delivery from a given InnoSwitch-CE device.
2. Higher VOR reduces the voltage stress on the output diodes and
SR MOSFTs.
3. Higher VOR increases leakage inductance that reduces efficiency
of the power supply.
4. Higher VOR increases peak and RMS current on the secondary-side
which may increase secondary-side copper and diode losses.
Safety Margin, M (mm)
For designs that require safety isolation between primary and
secondary but are not using triple insulated wire the width of the
safety margin to be used on each side of the bobbin should be
entered here. Typically for universal input designs a total margin of
6.2 mm would be required, and a value of 3.1 mm would be used on
either side of the winding. For vertical bobbins the margin may not
be symmetrical, however if a total margin of 6.2 mm were required
then the physical margin will be placed only on one side of the
bobbin.
As the margin reduces the available area for the windings, margin
construction may not be suitable for small core sizes. It is recommended that for compact power supply designs using an InnoSwitch-CE
IC, triple insulated wire should be used for secondary which then
eliminates need for margins.
Primary Layers, L
Primary layers should be in the range of 1 < L < 3 and in general it
should be the lowest number that meets the primary current density
limit (CMA). Values of ≥200 Cmils/Amp can be used as a starting
value for most designs though higher values may be required based
on thermal design constraints. Values above 3 layers are possible but
the increased leakage inductance and physical fit of the windings
should be considered. A split primary construction may be helpful for
designs where leakage inductance clamp dissipation is too high.
In split primary construction, half of the primary winding is placed on
either side of the secondary (and bias) winding in a sandwich
arrangement. This arrangement is often disadvantageous for low
power designs as this typically requires additional common mode
filtering which increases cost.
Ripple to Peak Current Ratio, KP
Below a value of 1, indicating continuous conduction mode, KP is the
ratio of ripple to peak primary current (Figure 18).
KP ≡ KRP =
I
K P / K RP = I R
P
Following a value of 1, indicating discontinuous conduction mode, KP
is the ratio of primary MOSFET off time to the secondary diode
conduction time.
K P / K DP =
^1 - D h # T
t
VOR # ^1 - D MAX h
=
^ V MIN - V DS h # D MAX
It is recommended that a K P close to 0.9 at the minimum DC bus
voltage of 70 V should be used for most InnoSwitch-CE designs.
A KP value of 1
T = 1/fS
Primary
D×T
(1-D) × T = t
Secondary
(b) Borderline Discontinuous/Continuous, KP = 1
Figure 19. Discontinuous Mode Current Waveform, KP
PI-2578-103114
≥1.
Maximum Operating Flux Density, BM (Gauss)
A maximum value of 3000 Gauss during normal operation is recommended to limit the maximum flux density under start-up and output
short-circuit. Under these conditions the output voltage is low and
little reset of the transformer occurs during the MOSFET off-time.
This allows the transformer flux density to staircase above the normal
operating level. A value of 3000 Gauss at the peak current limit of
the selected device together with the built-in protection features of
InnoSwitch-CE IC provides sufficient margin to prevent core saturation under start-up or output short-circuit conditions.
Transformer Primary Inductance, (LP)
Once the lowest operating voltage and the required VOR are determined, transformer primary inductance can be calculated. Care
should be taken to ensure that the selected inductance value does
not violate the maximum duty cycle specification in the data sheet of
the InnoSwitch-CE IC. The PIXls design spreadsheet which is part of
the free PI Expert suite can be used to assist in designing the
transformer.
Quick Design Checklist
As with any power supply design, all InnoSwitch-CE designs should
be verified on the bench to make sure that component specifications
are not exceeded under worst-case conditions.
The following minimum set of tests is strongly recommended:
1. Maximum drain voltage – Verify that VDS does not exceed 600 V
at highest input voltage and peak (overload) output power. The
50 V margin to the 650 V BVDSS specification gives margin for
design variation.
2. Maximum drain current – At maximum ambient temperature,
maximum input voltage and peak output (overload) power, verify
drain current waveforms for any signs of transformer saturation
and excessive leading edge current spikes at start-up. Repeat
under steady-state conditions and verify that the leading edge
current spike event is below ILIMIT(MIN) at the end of the tLEB(MIN).
Under all conditions, the maximum drain current should be below
the specified absolute maximum ratings.
3. Thermal Check – At specified maximum output power, minimum
input voltage and maximum ambient temperature, verify that the
temperature specifications are not exceeded for InnoSwitch-CE
IC, transformer, output SR MOSFET, and output capacitors.
Enough thermal margin should be allowed for part-to-part variation
of the RDS(ON) of InnoSwitch-CE IC as specified in the data sheet.
Under low-line, maximum power, a maximum InnoSwitch-CE SOURCE
pin temperature of 110 °C is recommended to allow for these variations.
15
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INN21x3-21x5
Absolute Maximum Ratings1,2
DRAIN Pin Voltage..................................................... -0.3 V to 650 V
DRAIN Pin Peak Current3 INN21x3.............................1200 (2250) mA
INN21x4.............................1360 (2550) mA
INN21x5............................. 1680 (3150) mA
PRIMARY BYPASS/SECONDARY BYPASS Pin Voltage.........-0.3 V to 9 V
PRIMARY BYPASS/SECONDARY BYPASS Pin Current................ 100 mA
FORWARD Pin Voltage.............................................. -1.5 V to 1507 V
FEEDBACK/CURRENT SENSE Pin Voltage............................-0.3 to 9 V
SR/P Pin Voltage..............................................................-0.3 to 9 V6
OUTPUT VOLTAGE Pin Voltage........................................-0.3 to 158 V
Storage Temperature....................................................-65 to 150 °C
Operating Junction Temperature4................................. -40 to 150 °C
Ambient Temperature...................................................-40 to 105 °C
Lead Temperature5.................................................................260 °C
Notes:
1. All voltages referenced to Source and Secondary Ground,
TA = 25 °C.
2. Maximum ratings specified may be applied one at a time without
causing permanent damage to the product. Exposure to Absolute
Maximum Ratings conditions for extended periods of time may
affect product reliability.
3. Higher peak Drain current is allowed while the Drain voltage is
simultaneously less than 400 V.
4. Normally limited by internal circuitry.
5. 1/16” from case for 5 seconds.
6. -1.8 V for a duration of ≤500 nsec. See Figure 23.
7. The maximum current out of the FORWARD pin when the
FORWARD pin is below Ground is -40 mA.
8. Maximum current into VOUT pin at 15 V should not exceed 10 mA.
Thermal Resistance
Thermal Resistance: K Package:
(qJA)...........................................65 °C/W2, 69 °C/W1
(qJC)........................................................ 12 °C/W3
Parameter
Notes:
1. Solder to 0.36 sq. in (232 mm2), 2 oz. (610 g/m2) copper clad.
2. Solder to 1 sq. in (645 mm2), 2 oz. (610 g/m2) copper clad.
3. The case temperature is measured at the plastic surface at the top
of the package.
Conditions
Rating
Units
Current from pin (3-6) to pin 1
1.5
A
TAMB = 25 °C
(Device mounted in socket resulting in TCASE = 120 °C)
1.35
W
TAMB = 25 °C
(Device mounted in socket)
0.125
W
Ratings for UL1577 (Adapter power rating is derated power capability)
Primary-Side
Current Rating
Primary-Side
Power Rating
Secondary-Side
Power Rating
Parameter
Symbol
Conditions
SOURCE = 0 V
TJI = -40 °C to +125 °C
(Note C) (Unless Otherwise Specified)
Min
Typ
Max
93
100
107
Units
Control Functions
Output Frequency
Applies to Both Primary
and Secondary
Controllers
Maximum Duty Cycle
Average
fOSC
TJ = 25 °C
kHz
Peak-to-Peak Jitter
DCMAX
TJ = 0 °C to 125 °C
6
60
%
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INN21x3-21x5
Parameter
Symbol
Conditions
SOURCE = 0 V
TJI = -40 °C to +125 °C
(Unless Otherwise Specified)
Min
Typ
Max
IS1
TJ = 25 °C, VBPP + 0.1 V
(MOSFET not Switching)
See Note B
235
260
290
INN21x3
645
750
INN21x4
790
900
INN21x5
970
1100
Units
Control Functions (cont.)
PRIMARY BYPASS Pin
Supply Current
IS2
ICH1
TJ = 25 °C, VBPP + 0.1 V
(MOSFET Switching at fOSC)
See Note A, C
TJ = 25 °C, VBP = 0 V
See Notes D, E
PRIMARY BYPASS Pin
Charge Current
ICH2
TJ = 25 °C, VBP = 4 V
See Notes D, E
INN21x3
-5.2
-4.6
-4.1
mA
INN21x4
-7.1
-6.3
-5.6
INN21x5
-7.1
-6.3
-5.6
INN21x3
-3.9
-2.9
-2.0
INN21x4
-5.0
-4.2
-3.4
INN21x5
-5.0
-4.2
-3.4
5.70
5.95
6.15
V
0.40
0.56
0.70
V
mA
PRIMARY BYPASS Pin
Voltage
VBPP
PRIMARY BYPASS Pin
Voltage Hysteresis
VBPP(H)
PRIMARY BYPASS
Shunt Voltage
VSHUNT
IBPP = 2 mA
6.15
6.45
6.75
V
UV/OV Pin Brown-In
Threshold
IUV+
TJ = 25 °C
10.7
11.9
13.1
mA
UV/OV Pin Brown-Out
Threshold
IUV-
TJ = 25 °C
See Note A
Brown-Out Delay Time
tUV-
UV/OV Pin Line Overvoltage Threshold
IOV+
TJ = 25 °C
UV/OV Pin Line Ovevoltage Recovery Threshold
IOV-
TJ = 25 °C
0.94 ×
IOV+
UV/OV Pin Overvoltage
Deglitch Filter
tOV+
See Note A
5
VOLTAGE MONITOR Pin
Threshold Voltage
VV
IV = 30 mA
See Note D
Line Fault Protection
0.87 ×
IUV+
30
34
38
ms
53.2
55.8
58.3
mA
ms
3.1
3.7
4.3
V
Circuit Protection
Standard Current Limit
(BPP) Capacitor = 0.1 mF
ILIMIT
See Note E
di/dt = 168 mA/ms
TJ = 25 °C
INN21x3
705
750
795
di/dt = 186 mA/ms
TJ = 25 °C
INN21x4
799
850
901
di/dt = 213 mA/ms
TJ = 25 °C
INN21x5
893
950
1007
mA
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Parameter
Symbol
Conditions
SOURCE = 0 V
TJI = -40 °C to +125 °C
(Unless Otherwise Specified)
Min
Typ
Max
Units
Circuit Protection (cont.)
Reduced Current Limit
(BPP) Capacitor = 10 mF
Increased Current Limit
(BPP) Capacitor = 1 mF
Power Coefficient
ILIMIT-1
See Note E
ILIMIT+1
See Note E
I2 f
di/dt = 168 mA/ms
TJ = 25 °C
INN21x3
591
650
709
di/dt = 186 mA/ms
TJ = 25 °C
INN21x4
682
750
818
di/dt = 213 mA/ms
TJ = 25 °C
INN21x5
773
850
927
di/dt = 168 mA/ms
TJ = 25 °C
INN21x3
773
850
927
di/dt = 186 mA/ms
TJ = 25 °C
INN21x4
864
950
1036
di/dt = 213 mA/ms
TJ = 25 °C
INN21x5
955
1050
1145
Standard Current Limit,
I2f = ILIMIT(TYP)2 × fOSC(TYP)
See Note A
INN21x3-21x5
0.87 ×
I2 f
I2 f
1.15 ×
I2 f
Reduced Current Limit,
I2f = ILIMITred(TYP)2 × fOSC(TYP)
See Note A
INN21x3-21x5
0.84 ×
I2 f
I2 f
1.18 ×
I2 f
Increased Current Limit,
I2f = ILIMITinc(TYP)2 × fOSC(TYP)
See Note A
INN21x3-21x5
0.84 ×
I2 f
I2 f
1.18 ×
I2 f
Initial Current Limit
IINIT
TJ = 25 °C
See Note A
0.75 ×
ILIMIT(TYP)
Leading Edge
Blanking Time
tLEB
TJ = 25 °C
See Note A
170
Current Limit Delay
tILD
TJ = 25 °C
See Note A, F
Thermal Shutdown
TSD
See Note A
Thermal Shutdown
Hysteresis
TSD(H)
See Note A
PRIMARY BYPASS Pin
Shutdown Threshold
Current
Primary Bypass
Power-Up Reset
Threshold Voltage
Auto-Restart On-Time
at fOSC
Auto-Restart
Trigger‑Skip Time
ISD
135
mA
mA
A2Hz
mA
250
ns
170
ns
142
150
75
°C
°C
5.6
7.6
9.6
mA
VBPP(RESET)
TJ = 25 °C
2.8
3.0
3.3
V
t AR
TJ = 25 °C
See Note G
64
77
90
ms
t AR(SK)
TJ = 25 °C
See Note A, G
1
s
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INN21x3-21x5
Parameter
Symbol
Conditions
SOURCE = 0 V
TJI = -40 °C to +125 °C
(Unless Otherwise Specified)
t AR(OFF)
TJ = 25 °C
See Note G
t AR(OFF)SH
TJ = 25 °C
See Note A, G
Min
Typ
Max
Units
2
s
Circuit Protection (cont.)
Auto-Restart Off-Time
at fOSC
Short Auto-Restart
Off-Time at fOSC
0.5
s
Output
INN21x3
ID = 850 mA
ON-State Resistance
RDS(ON)
INN21x4
ID = 950 mA
INN21x5
ID = 1050 mA
TJ = 25 °C
3.50
4.10
TJ = 100 °C
See Note A
5.50
6.30
TJ = 25 °C
2.30
2.70
TJ = 100 °C
See Note A
3.60
4.20
TJ = 25 °C
1.70
2.00
TJ = 100 °C
See Note A
2.70
3.10
OFF-State Drain
Leakage Current
IDSS1
VBPP = 6.2 V, VDS = 560 V, TJ = 125 °C
See Note H
OFF-State Drain
Leakage Current
IDSS2
VBPP = 6.2 V, VDS = 325 V, TJ = 25 °C
See Note A, H
Breakdown Voltage
BVDSS
VBPP = 6.2 V, TJ = 25 °C
See Note I
Drain Supply Voltage
200
15
W
mA
mA
650
V
50
V
Secondary
FEEDBACK Pin Voltage
VFB
TJ = 25 °C
1.250
1.265
1.280
V
OUTPUT VOLTAGE Pin
Auto-Restart Threshold
VOUT(AR)
See Note K
3.00
3.25
3.50
V
SECONDARY BYPASS
Pin Current at No-Load
ISNL
TJ = 25 °C
265
300
335
mA
Cable Drop
Compensation Factor
φCD
250
300
350
SECONDARY BYPASS
Pin Voltage
VBPS
4.25
4.45
4.65
V
SECONDARY BYPASS
Pin Undervoltage
Threshold
VBPS(UVLO)
3.45
3.8
4.15
V
SECONDARY BYPASS
Pin Undervoltage
Hysteresis
VBPS(HYS)
0.10
0.65
1.2
V
34.1
35
35.9
mV
Output (IS Pin) Current
Limit Voltage Threshold
ISVTH
INN212x
TJ = 25 °C
INN210x
TJ = 25 °C
0
VOUT Pin
Auto-Restart Timer
tVOUT(AR)
50
FEEDBACK Pin
Short-Circuit
VFB(OFF)
80
mV
ms
100
120
mV
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Symbol
Conditions
SOURCE = 0 V
TJI = -40 °C to +125 °C
(Unless Otherwise Specified)
Min
Typ
Max
Units
SYNCHRONOUS
RECTIFIER Pin
Threshold
VSRTH
TJ = 25 °C
-19
-24
-29
mV
SYNCHRONOUS
RECTIFIER Pin
Pull-Up Current
ISRPU
TJ = 25 °C
CLOAD = 2 nF, fS = 100 kHz
135
162
185
mA
SYNCHRONOUS
RECTIFIER Pin
Pull-Down Current
ISRPD
TJ = 25 °C
CLOAD = 2 nF, fS = 100 kHz
210
250
330
mA
SYNCHRONOUS
RECTIFIER Pin
Drive Voltage
VSR
See Note A
4.2
4.4
4.6
V
Rise Time
tR
TJ = 25 °C
CLOAD = 2 nF
See Note A
Fall Time
tF
TJ = 25 °C
CLOAD = 2 nF
See Note A
Parameter
Synchronous Rectifier1
0-100%
71
10-90%
40
0-100%
32
10-90%
15
ns
ns
Output Pull-Up
Resistance
RPU
TJ = 25 °C, VSPS = 4.4 V
ISR = 10 mA, See Note A
11.5
W
Output Pull-Down
Resistance
RPD
TJ = 25 °C, VSPS = 4.4 V
ISR = 10 mA, See Note A
3.5
W
NOTES:
A. This parameter is derived from characterization.
B. IS1 is an estimate of device current consumption at no-load, since the operating frequency is so low under these conditions. Total device
consumption at no-load is sum of IS1 and IDSS2 (this does not include secondary losses)
C. Since the output MOSFET is switching, it is difficult to isolate the switching current from the supply current at the Drain. An alternative is to
measure the PRIMARY BYPASS pin current at 6.2 V.
D. The PRIMARY BYPASS pin is not intended for sourcing supply current to external circuitry.
E. To ensure correct current limit it is recommended that nominal 0.1 mF/1 mF/10 mF capacitors are used. In addition, the BPP capacitor value
tolerance should be equal or better than indicated below across the ambient temperature range of the target application. The minimum and
maximum capacitor values are guaranteed by characterization.
Nominal PRIMARY
BYPASS Pin Capacitor
Value
Tolerance Relative to Nominal
Capacitor Value
Minimum
Maximum
0.1 mF
-60%
+100%
1 mF
-50%
+100%
10 mF
-50%
N/A
F. This parameter is derived from the change in current limit measured at 1X and 4X of the di/dt shown in the ILIMIT specification.
G. Auto-restart on-time has same temperature characteristics as the oscillator (inversely proportional to frequency).
H. IDSS1 is the worst-case OFF-state leakage specification at 80% of BVDSS and the maximum operating junction temperature. IDSS2 is a typical
specification under worst-case application conditions (rectified 230 VAC) for no-load consumption calculations.
I. Breakdown voltage may be checked against minimum BVDSS specification by ramping Drain voltage up to but not exceeding minimum BVDSS.
J. For reference only. This is the total range of current limit threshold which corrects for variations in the current sense bond wire. Both of
which are trimmed to set the normalized output constant current.
K. Measured at the VOUT pin of the device. At the end of the cable under load, the apparent auto-restart threshold will be lower.
20
Rev. A 02/16
www.power.com
INN21x3-21x5
Typical Performance Characteristics
1.0
1.2
1.0
0.8
25
50
Scaling Factors:
INN21x3 1.22
INN21x4 1.12
INN21x5 1.10
0.4
0.2
75 100 125 150
1
2
200
150
100
TCASE=25 °C
TCASE=100 °C
0
1000
Drain Capacitance (pF)
PI-7725-091415
Drain Current (mA)
Scaling Factors:
INN21x3
7.9
INN21x4 11.2
INN21x5 16.0
50
Scaling Factors:
INN21x3
7.9
INN21x4 11.2
INN21x5 16.0
100
10
1
0
2
4
6
8
1
10
100
20
10
0
100
200
300
400
Drain Voltage (V)
Figure 24. Drain Capacitance Power.
500
600
400
500
600
VSR(t)
PI-7474-011215
SYNCHRONOUS RECTIFIER DRIVE
Pin Voltage Limits (V)
Power (mW)
PI-7724-091415
Scaling Factors:
INN21x3
7.9
INN21x4 11.2
INN21x5 16.0
30
300
Figure 23. COSS vs. Drain Voltage.
Figure 22. Output Characteristic.
40
200
Drain Voltage (V)
DRAIN Voltage (V)
0
4
Figure 21. Standard Current Limit Vs. di/dt.
Figure 20. Breakdown vs. Temperature.
250
3
Normalized di/dt
Junction Temperature (°C)
300
Note: For the
normalized current
limit value, use the
typical current limit
specified for the
appropriate BP/M
capacitor.
PI-7723-091415
0
Normalized
di/dt = 1
0.6
0
0.9
-50 -25
PI-7726-091415
1.4
Normalized Current Limit
PI-2213-012315
Breakdown Voltage
(Normalized to 25 °C)
1.1
-0.0
-0.3
-1.8
500 ns
Time (ns)
Figure 25. SYNCHRONOUS RECTIFIER DRIVE Pin Negative Voltage.
21
www.power.com
Rev. A 02/16
Rev. A 02/16
4
TOP VIEW
C
Detail A
9
5
4
3
END VIEW
0.092 [2.34]
0.086 [2.18]
0.306 [7.77] Ref.
BOTTOM VIEW
6
7. Exposed metal at the plastic package body outline/surface between leads 6 and 7, connected
internally to wide lead 3/4/5/6.
6. Datums A and B to be determined in Datum H.
5. Controlling dimensions in inches [mm].
4. Does not include inter-lead flash or protrusions.
3. Dimensions noted are inclusive of plating thickness.
0.020 [0.51]
Ref.
1.78
[.070]
0.71
[.028]
Reference
Solder Pad
Dimensions
0.016 [0.41]
0.011 [0.28]
12X
3
0° - 8°
0.010 [0.25]
Sealing Plane
C
Gauge Plane
H
4.11
[.162]
PI-6995-111214
POD-eSOP-R16B Rev B
mm [INCH]
11.68
[.460]
1.27
[.050]
0.010 [0.25] Ref.
0.032 [0.81]
0.029 [0.74]
0.022 [0.56] Ref.
0.019 [0.48]
Ref.
DETAIL A
0.040 [1.02]
0.028 [0.71]
4.19
[.165]
7.62
[.300]
8.89
[.350]
0.057 [1.45] Ref.
0.028 [0.71]
Ref.
0.059 [1.50]
Ref. Typ.
0.059 [1.50]
Ref. Typ.
0.010 [0.24]
Ref.
1
10 11 12 13 14 15 16
0.400 [10.16]
2
0.004 [0.10] C A
2. Dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold
flash, tie bar burrs, gate burrs, and inter-lead flash, but including any mismatch between the top
and bottom of the plastic body. Maximum mold protrusion is 0.007 [0.18] per side.
Seating
Plane
0.049 [1.23]
0.046 [1.16]
0.004 [0.10] C
12 Leads
SIDE VIEW
7
0.464 [11.79]
8 Lead Tips
0.006 [0.15] C
A
2X
8
7
0.006 [0.15] C
4 Lead Tips
3
4
0.158 [4.01]
0.045 [1.14] Ref.
0.152 [3.86]
8
9
0.080 [2.03] Ref.
0.356 [9.04]Ref.
1
16
0.050 [1.27]
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
Seating Plane to
Molded Bumps
Standoff
0.012 [0.30]
0.004 [0.10]
0.105 [2.67]
0.093 [2.36]
Pin #1 I.D.
(Laser Marked)
B
0.350 [8.89]
2
2X
0.004 [0.10] C B
3
0.023 [0.58] 13X
0.018 [0.46]
0.010 [0.25] M C A B
eSOP-R16B
INN21x3-21x5
22
www.power.com
INN21x3-21x5
PACKAGE MARKING
eSOP-R16B
A
A.
B.
C.
D.
INN2105K
1530
M4N343-1
C
B
D
Power Integrations Registered Trademark
Assembly Date Code (last two digits of year followed by 2-digit work week)
Product Identification (Part #/Package Type)
Lot Identification Code
PI-7814-120215
23
www.power.com
Rev. A 02/16
INN21x3-21x5
MSL Table
Part Number
MSL Rating
INN21x3
3
INN21x4
3
INN21x5
3
ESD and Latch-Up Table
Test
Conditions
Results
Latch-up at 125 °C
JESD78D
Human Body Model ESD
ANSI/ESDA/JEDEC JS-001-2014
> ±2000 V on all pins
Machine Model ESD
JESD22-A115C
> ±200 V on all pins
> ±100 mA or > 1.5 V (max) on all pins
Part Ordering Information
• InnoSwitch-CE Product Family
• 21x Series Number
• Package Identifier
K
eSOP-R16B
• Tape & Reel and Other Options
INN 21x3 K - TL
TL
Tape & Reel, 1000 pcs min/mult.
24
Rev. A 02/16
www.power.com
INN21x3-21x5
Notes
25
www.power.com
Rev. A 02/16
Revision Notes
A
Date
Code A.
02/16
For the latest updates, visit our website: www.power.com
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations
does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY
HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
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The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one
or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of
Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set
forth at http://www.power.com/ip.htm.
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POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:
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failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or
death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness.
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Integrations, Inc. Other trademarks are property of their respective companies. ©2016, Power Integrations, Inc.
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