INN3165C-H102-TL

InnoSwitch3-CE Family Off-Line CV/CC QR Flyback Switcher IC with Integrated Primary Switch, Synchronous Rectification and FluxLink Feedback. For Applications up to 65 W Product Highlights Highly Integrated, Compact Footprint • Up to 94% efficiency across full load range • Incorporates a multi-mode Quasi-Resonant (QR) / CCM flyback controller, 650 V Switch, secondary-side sensing and synchronous rectification driver • Integrated FluxLink™, HIPOT-isolated, feedback link • Exceptional CV/CC accuracy, independent of external components • Adjustable accurate output current sense using external sense resistor • Less than 30 mW no-load including line sense • Easily meets all global energy efficiency regulations • Low heat dissipation InnoSwitch3-CE FB BPS GND SR V VOUT Primary Switch and Controller S Advanced Protection / Safety Features • Secondary Switch or diode short-circuit protection • Open SR FET-gate detection • Fast input line UV/OV protection D FWD EcoSmart™ – Energy Efficient SR FET IS BPP Secondary Control IC Figure 1. Typical Application schematic. PI-8179-092019 Optional Features • • • • • Cable-drop compensation with multiple settings Variable output voltage, constant current profiles Auto-restart or latching fault response for output OVP/UVP Multiple output UV fault thresholds Latching or hysteretic primary over-temperature protection Full Safety and Regulatory Compliance • • • • Reinforced isolation Isolation voltage >4000 VAC 100% production HIPOT testing UL1577, TUV (EN62368-1), CQC (GB4943.1) and VDE 0884-17 (EN60747-17) safety approved • Excellent noise immunity enables designs that achieve class “A” performance criteria for EN61000-4 suite; EN61000-4-2, 4-3 (30 V/m), 4-4, 4-5, 4-6, 4-8 (100 A/m) and 4-9 (1000 A/m) Green Package • Halogen free and RoHS compliant Applications Figure 2. High Creepage, Safety-Compliant InSOP-24D Package. Output Power Table 230 VAC ± 15% Product 3 85-265 VAC Adapter1 Open Frame2 INN3162C 10 W 12 W 10 W 10 W INN3163C 12 W 15 W 12 W 12 W Adapter1 Open Frame2 INN3164C 20 W 25 W 15 W 20 W INN3165C 25 W 30 W 22 W 25 W INN3166C 35 W 40 W 27 W 36 W Description INN3167C 45 W 50 W 40 W 45 W The InnoSwitch™3-CE family of ICs dramatically simplifies the design and manufacture of flyback power converters, particularly those requiring high efficiency and/or compact size. The InnoSwitch3-CE family incorporates primary and secondary controllers and safety-rated feedback into a single IC. INN3168C 55 W 65 W 50 W 55 W • High efficiency flyback designs up to 65 W • High current charger and adaptors for mobile devices • Consumer electronics − set-top boxes, networking, gaming, LED InnoSwitch3-CE family devices incorporate multiple protection features including line over and undervoltage protection, output over-voltage and over-current limiting, and over-temperature shutdown. Devices are available that support the common combinations of latching and auto-restart behaviors required by applications such as chargers, adapters, consumer electronics and industrial systems. The devices are available with and without cable-drop compensation. www.power.com Table 1. Output Power Table. Notes: 1. Minimum continuous power in a typical non-ventilated enclosed typical size adapter measured at 40 °C ambient. Max output power is dependent on the design, with condition that package temperature must be tAR(SK). The second is included to ensure that if communication is lost, the primary tries to restart. Although this should never be the case in normal operation, it can be useful when system ESD events (for example) causes a loss of communication due to noise disturbing the secondary controller. The issue is resolved when the primary restarts after an auto-restart off-time. 4 www.power.com Rev. I 09/21 InnoSwitch3-CE The auto-restart is reset as soon as an AC reset occurs. SOA Protection In the event that there are two consecutive cycles where the ILIM is reached within ~500 ns (the blanking time + current limit delay time), (including leading edge current spike) the controller will skip 2.5 cycles or ~25 ms (based on full frequency of 100 kHz). This provides sufficient time for the transformer to reset with large capacitive loads without extending the start-up time. Secondary Rectifier/SR Switch Short Protection (SRS) In the event that the output diode or SR FET is short-circuited before or during the primary conduction cycle, the drain current (prior to the end of the leading edge blanking time) can be much higher than the maximum current limit threshold. If the controller turns the highvoltage power switch off, the resulting peak drain voltage could exceed the rated BVDSS of the device, resulting in catastrophic failure even with minimum on-time. To address this issue, the controller features a circuit that reacts when the drain current exceeds the maximum current limit threshold prior to the end of leading-edge blanking time. If the leading-edge current exceeds current limit within a cycle (200 ns), the primary controller will trigger a 30 ms off-time event. SOA mode is triggered if there are two consecutive cycles above current limit within tLES (~500 ns). SRS mode also triggers t AR(OFF)SH off-time, if the current limit is reached within 200 ns after a 30 ms off-time. Input Line Voltage Monitoring The UNDER/OVER INPUT VOLTAGE pin is used for input undervoltage and overvoltage sensing and protection. A sense resistor is tied between the high-voltage DC bulk capacitor after the bridge (or to the AC side of the bridge rectifier for fast AC reset) and the UNDER/OVER INPUT VOLTAGE pin to enable this functionality. This function can be disabled by shorting the UNDER/ OVER INPUT VOLTAGE pin to SOURCE pin. At power-up, after the primary bypass capacitor is charged and the ILIM state is latched, and prior to switching, the state of the UNDER/ OVER INPUT VOLTAGE pin is checked to confirm that it is above the brown-in and below the overvoltage shutdown thresholds. In normal operation, if the UNDER/OVER INPUT VOLTAGE pin current falls below the brown-out threshold and remains below brown-in for longer than tUV-, the controller enters auto-restart. Switching will only resume once the UNDER/OVER INPUT VOLTAGE pin current is above the brown-in threshold. In the event that the UNDER/OVER INPUT VOLTAGE pin current is above the overvoltage threshold, the controller will also enter auto-restart. Again, switching will only resume once the UNDER/ OVER INPUT VOLTAGE pin current has returned to within its normal operating range. The input line UV/OV function makes use of an internal high-voltage switch on the UNDER/OVER INPUT VOLTAGE pin to reduce power consumption. If the cycle off-time tOFF is greater than 50 ms, the internal high-voltage switch will disconnect the external 4 MW resistor from the internal IC to eliminate current drawn through the sense resistor. The line sensing function will activate again at the beginning of the next switching cycle. P: Primary Chip S: Secondary Chip Start P: Powered Up, Switching S: Powering Up P: Auto-Restart S: Powering Up tAR(OFF) S: Has powered up within tAR No P: Goes to Auto-Restart Off S: Bypass Discharging Yes tAR P: Switching S: Sends Handshaking Pulses P: Has Received Handshaking Pulses No P: Continuous Switching S: Doesn’t Take Control No P: Not Switching S: Doesn’t Take Control Yes P: Stops Switching, Hands Over Control to Secondary S: Has Taken Control? Yes End of Handshaking, Secondary Control Mode PI-7416a-102116 Figure 7. Primary-Secondary Handshake Flowchart. Primary-Secondary Handshake At start-up, the primary-side initially switches without any feedback information (this is very similar to the operation of a standard TOPSwitch™, TinySwitch™ or LinkSwitch™ controllers). If no feedback signals are received during the auto-restart on-time (t AR), the primary goes into auto-restart mode. Under normal conditions, the secondary controller will power-up via the FORWARD pin or from the OUTPUT VOLTAGE pin and take over control. From this point onwards the secondary controls switching. If the primary controller stops switching or does not respond to cycle requests from the secondary during normal operation (when the secondary has control), the handshake protocol is initiated to ensure that the secondary is ready to assume control once the primary begins to switch again. An additional handshake is also triggered if the secondary detects that the primary is providing more cycles than were requested. 5 www.power.com Rev. I 09/21 InnoSwitch3-CE The most likely event that could require an additional handshake is when the primary stops switching as the result of a momentary line brown-out event. When the primary resumes operation, it will default to a start-up condition and attempt to detect handshake pulses from the secondary. If the secondary does not detect that the primary responds to switching requests for 8 consecutive cycles, or if the secondary detects that the primary is switching without cycle requests for 4 or more consecutive cycles, the secondary controller will initiate a second handshake sequence. This provides additional protection against cross-conduction of the SR FET while the primary is switching. This protection mode also prevents an output overvoltage condition in the event that the primary is reset while the secondary is still in control. Wait and Listen When the primary resumes switching after initial power-up recovery from an input line voltage fault (UV or OV) or an auto-restart event, it will assume control and require a successful handshake to relinquish control to the secondary controller. As an additional safety measure the primary will pause for an auto-restart on-time period, t AR (~82 ms), before switching. During this “wait” time, the primary will “listen” for secondary requests. If it sees two consecutive secondary requests, separated by ~30 ms, the primary will infer secondary control and begin switching in slave mode. If no pulses occurs during the t AR “wait” period, the primary will begin switching under primary control until handshake pulses are received. Audible Noise Reduction Engine The InnoSwitch3-CE features an active audible noise reduction mode whereby the controller (via a “frequency skipping” mode of operation) avoids the resonant band (where the mechanical structure of the power supply is most likely to resonate − increasing noise amplitude) between 5 kHz and 12 kHz - 200 ms and 83 ms period respectively. If a secondary controller switch request occurs within this time window from the last conduction cycle, the gate drive to the power switch is inhibited. Secondary Controller As shown in the block diagram in Figure 4, the IC is powered by a 4.4 V (VBPS) regulator which is supplied by either VOUT or FWD. The SECONDARY BYPASS pin is connected to an external decoupling capacitor and fed internally from the regulator block. The FORWARD pin also connects to the negative edge detection block used for both handshaking and timing to turn on the SR FET connected to the SYNCHRONOUS RECTIFIER DRIVE pin. The FORWARD pin voltage is used to determine when to turn off the SR FET in discontinuous conduction mode operation. This is when the voltage across the RDS(ON) of the SR FET drops below zero volts. In continuous conduction mode (CCM) the SR FET is turned off when the feedback pulse is sent to the primary to demand the next switching cycle, providing excellent synchronous operation, free of any overlap for the FET turn-off. The mid-point of an external resistor divider network between the OUTPUT VOLTAGE and SECONDARY GROUND pins is tied to the FEEDBACK pin to regulate the output voltage. The internal voltage comparator reference voltage is VFB (1.265 V). The external current sense resistor connected between ISENSE and SECONDARY GROUND pins is used to regulate the output current in constant current regulation mode. Minimum Off-Time The secondary controller initiates a cycle request using the inductiveconnection to the primary. The maximum frequency of secondarycycle requests is limited by a minimum cycle off-time of tOFF(MIN). This is in order to ensure that there is sufficient reset time after primary conduction to deliver energy to the load. Maximum Switching Frequency The maximum switch-request frequency of the secondary controller is fSREQ. Frequency Soft-Start At start-up the primary controller is limited to a maximum switching frequency of fSW and 75% of the maximum programmed current limit at the switch-request frequency of 100 kHz. The secondary controller temporarily inhibits the FEEDBACK short protection threshold (VFB(OFF)) until the end of the soft-start (tSS(RAMP)) time. After hand-shake is completed the secondary controller linearly ramps up the switching frequency from fSW to fSREQ over the tSS(RAMP) time period. In the event of a short-circuit or overload at start-up, the device will move directly into CC (constant-current) mode. The device will go into auto-restart (AR), if the output voltage does not rise above the VFB(AR) threshold before the expiration of the soft-start timer (tSS(RAMP)) after handshake has occurred. The secondary controller enables the FEEDBACK pin-short protection mode (VFB(OFF)) at the end of the tSS(RAMP) time period. If the output short maintains the FEEDBACK pin below the short-circuit threshold, the secondary will stop requesting pulses triggering an auto-restart cycle. If the output voltage reaches regulation within the tSS(RAMP) time period, the frequency ramp is immediately aborted and the secondary controller is permitted to go full frequency. This will allow the controller to maintain regulation in the event of a sudden transient loading soon after regulation is achieved. The frequency ramp will only be aborted if quasi-resonant-detection programming has already occurred. Maximum Secondary Inhibit Period Secondary requests to initiate primary switching are inhibited to maintain operation below maximum frequency and ensure minimum off-time. Besides these constraints, secondary-cycle requests are also inhibited during the “ON” time cycle of the primary switch (time between the cycle request and detection of FORWARD pin falling edge). The maximum time-out in the event that a FORWARD pin falling edge is not detected after a cycle requested is ~30 ms. Output Voltage Protection In the event that the sensed voltage on the FEEDBACK pin is 2% higher than the regulation threshold, a bleed current of ~2.5 mA (3 mA max) is applied on the OUTPUT VOLTAGE pin (weak bleed). This bleed current increases to ~200 mA (strong bleed) in the event that the FEEDBACK pin voltage is raised beyond ~10% of the internal FEEDBACK pin reference voltage. The current sink on the OUTPUT VOLTAGE pin is intended to discharge the output voltage after momentary overshoot events. The secondary does not relinquish control to the primary during this mode of operation. If the voltage on the FEEDBACK pin is sensed to be 20% higher than the regulation threshold, a command is sent to the primary to either latch-off or begin an auto-restart sequence (see Secondary Fault Response in Feature Code Addendum). This integrated VOUT OVP can be used independently from the primary sensed OVP or in conjunction. 6 www.power.com Rev. I 09/21 InnoSwitch3-CE protection mode is on for less than ~10 ms. By this mechanism, the secondary will relinquish control after detecting that the FEEDBACK pin is shorted to ground. Cable Drop Compensation VFB No-Load Load Current Onset of CC Regulation PI-8035-072516 Figure 8. Cable Drop Compensation Characteristics. FEEDBACK Pin Short Detection If the sensed FEEDBACK pin voltage is below VFB(OFF) at start-up, the secondary controller will complete the handshake to take control of the primary complete tSS(RAMP) and will stop requesting cycles to initiate auto-restart (no cycle requests made to primary for longer than t AR(SK) second triggers auto-restart). FORWARD Pin Voltage During normal operation, the secondary will stop requesting pulses from the primary to initiate an auto-restart cycle when the FEEDBACK pin voltage falls below the VFB(OFF) threshold. The deglitch filter on the Cable Drop Compensation (CDC) The amount of cable drop compensation is a function of the load with respect to the constant current regulation threshold as illustrated in Figure 8. Auto-Restart Thresholds The FEEDBACK pin or OUTPUT VOLTAGE pin includes a comparator to detect when the feedback voltage or output voltage falls below VFB(AR), for a duration exceeding tFB(AR) or tVO(AR) respectively. The secondary controller will relinquish control when this fault condition is sensed. This threshold is meant to limit the range of constant current (CC) operation. SECONDARY BYPASS Pin Overvoltage Protection The InnoSwitch3-CE secondary controller features a SECONDARY BYPASS pin OV feature similar to the PRIMARY BYPASS pin OV feature. When the secondary is in control: in the event the SECONDARY BYPASS pin current exceeds IBPS(SD) (~7 mA) the secondary will send a command to the primary to initiate an auto-restart off-time (t AR(OFF)) or latch-off event (see Secondary Fault Response in Feature Code Addendum). Output Constant Current The InnoSwitch3-CE regulates the output current through an external current sense resistor between the ISENSE and SECONDARY GROUND pins where the voltage generated across the resistor is PI-8147-102816 FEEDBACK Pin Voltage X × VFB Request Window Output Voltage Primary VDS Time Time Figure 9. Intelligent Quasi-Resonant Mode Switching. 7 www.power.com Rev. I 09/21 InnoSwitch3-CE compared to an internal reference of ISV(TH) (~35 mV). If constant current regulation is not required, the ISENSE pin must be tied to SECONDARY GROUND pin. SR Disable Protection In each cycle SR is only engaged if a set cycle was requested by the secondary controller and the negative edge is detected on the FORWARD pin. In the event that the voltage on the ISENSE pin exceeds approximately 3 times the CC threshold, the SR FET drive is disabled until the surge current has diminished to nominal levels. SR Static Pull-Down To ensure that the SR gate is held low when the secondary is not in control, the SYNCHRONOUS RECTIFIER DRIVE pin has a nominally “ON” device to pull the pin low and reduce any voltage on the SR gate due to capacitive coupling from the FORWARD pin. Open SR Protection In order to protect against an open SYNCHRONOUS RECTIFIER DRIVE pin system fault the secondary controller has a protection mode to ensure the SYNCHRONOUS RECTIFIER DRIVE pin is connected to an external FET. If the external capacitance on the SYNCHRONOUS RECTIFIER DRIVE pin is below 100 pF, the device will assume the SYNCHRONOUS RECTIFIER DRIVE pin is “open” and there is no FET to drive. If the pin capacitance detected is above 100 pF, the controller will assume an SR FET is connected. Peak Power Delivery Output overload response depends on whether the IS pin is shorted to ground or the design includes a current sense resistor to set the overload threshold. If there is an external current sense resistor on the IS pin, the InnoSwitch has options to set the overload response in two different ways. If the device is configured to have the FEEDBACK pin auto-restart enabled, once the load current reaches the current limit threshold set by the IS pin resistor, the output voltage will fold back and autorestart will occur once the output voltage falls below the AR threshold for a time period exceeding the AR timer. If the device is configured for overload response, once the load current exceeds the current sense threshold the output voltage does not fold back. The auto-restart timer will begin and auto-restart occurs if the load current remains higher than the current sense threshold for a time period exceeding the AR timer. The two cases where a current sense resistor is included in the design are shown in the Figure 10 below. In the event the SYNCHRONOUS RECTIFIER DRIVE pin is detected to be open, the secondary controller will stop requesting pulses from the primary to initiate auto-restart. Intelligent Quasi-Resonant Mode Switching In order to improve conversion efficiency and reduce switching losses, the InnoSwitch3-CE features a means to force switching when the voltage across the primary switch is near its minimum voltage when the converter operates in discontinuous conduction mode (DCM). This mode of operation is automatically engaged in DCM and disabled once the converter moves to continuous-conduction mode (CCM). Rather than detecting the magnetizing ring valley on the primaryside, the peak voltage of the FORWARD pin voltage as it rises above the output voltage level is used to gate secondary requests to initiate the switch “ON” cycle in the primary controller. The secondary controller detects when the controller enters in discontinuous-mode and opens secondary cycle request windows corresponding to minimum switching voltage across the primary power switch. Quasi-Resonant (QR) mode is enabled for 20 ms after DCM is detected or when ring amplitude (pk-pk) >2 V. Afterwards, QR switching is disabled, at which point switching may occur at any time a secondary request is initiated. Output Voltage If the SYNCHRONOUS RECTIFIER DRIVE pin is tied to ground at start-up, the SR drive function is disabled and the open SYNCHRONOUS RECTIFIER DRIVE pin protection mode is also disabled. No CC with Overload Response AR when Load > ISVTH for t > tIS(AR) Constant Current when VFB(AR) is enabled AR when VFB < VFB(AR) for t(FBAR) Load Current ISVTH Threshold PI-8962-040819 Figure 10. Current Sense Resistor in a Design. If the IS pin is shorted to the GND pin, the overload response heavily depends on the operating conditions. If the device is configured to have feedback auto-restart enabled (VFB(AR)), auto-restart will occur if the output voltage droops below the auto-restart threshold for longer than the auto-restart timer (tFB(AR)). Otherwise, the auto-restart occurs if the primary switches above the overload frequency limit (fOVL) for longer than the auto-restart on-time (t AR). The secondary controller includes blanking of ~1 ms to prevent false detection of primary “ON” cycle when the FORWARD pin rings below ground. See Figure 9. 8 www.power.com Rev. I 09/21 InnoSwitch3-CE Applications Example C4 2.2 nF 250 VAC 1 12 V, 3 A FL1 TP1 C7 470 pF R6 2.00 MΩ 1% R1 100 kΩ F1 2A 90 - 264 VAC RT1 2.5 Ω 4 L1 20 mH 2 C2 33 µF 400 V 3 C8 1 nF C6 470 µF 16 V D1 DL4007 Q1 SI4190ADY 4 D2 1N4003 R4 100 kΩ 1% R2 390 Ω VR1 BZX79-C8V2 8.2 V R8 11.8 kΩ 1% C9 330 pF 50 V 2 C3 33 µF 400 V T1 EQ2506 C12 2.2 µF 25 V R9 47 Ω C10 1 µF 50 V V CONTROL S L2 10 µH BPS D GND C11 22 µF 50 V VO R10 5.6 kΩ SR O FWD t C1 100 nF 275 VAC 1 R7 1.80 MΩ 1% C5 470 µF 16 V FL2 R5 20 Ω R3 32 Ω BR1 GBL06 600 V 3 D3 DFLR1200-7 200 V C13 4.7 µF 50 V BPP FB InnoSwitch3-CE U1 INN3166C-H102 IS R11 0.007 Ω 1% RTN PI-8391-100417 TP2 Figure 11. 12 V, 3 A Charger/Adapter. The circuit shown in Figure 11 is a low cost 12 V, 3 A power supply using INN3166C. This single output design features DOE Level 6 and EC CoC 5 compliance. Bridge rectifier BR1 rectifies the AC input supply. Capacitors C2 and C3 provide filtering of the rectified AC input and together with inductor L2 form a pi-filter to attenuate differential mode EMI. Capacitor C4 connected at the power supply output with input common mode choke help to reduce common mode EMI. Thermistor RT1 limits the inrush current when the power supply is connected to the input AC supply. Input fuse F1 provides protection against excess input current resulting from catastrophic failure of any of the components in the power supply. One end of the transformer primary is connected to the rectified DC bus; the other is connected to the drain terminal of the switch inside the InnoSwitch3-CE IC (U1). A low-cost RCD clamp formed by diode D1, resistors R3, R1, and capacitor C7 limits the peak drain voltage of U1 at the instant of turn-off of the switch inside U1. The clamp helps to dissipate the energy stored in the leakage reactance of transformer T1. The InnoSwitch3-CE IC is self-starting, using an internal high-voltage current source to charge the BPP pin capacitor (C13) when AC is first applied. During normal operation the primary-side block is powered from an auxiliary winding on the transformer T1. Output of the auxiliary (or bias) winding is rectified using diode D2 and filtered using capacitor C11. Resistor R10 limits the current being supplied to the BPP pin of InnoSwitch3-CE IC (U1). The secondary-side controller of the InnoSwitch3-CE IC provides output voltage sensing, output current sensing and drive to a switch providing synchronous rectification. The secondary of the transformer is rectified by SR FET Q1 and filtered by capacitors C5 and C6. High frequency ringing during switching transients that would otherwise create radiated EMI is reduced via a snubber (resistor R5 and capacitor C8). Synchronous rectification (SR) is provided by switch Q1. The gate of Q1 is turned on by secondary-side controller inside IC U1, based on the winding voltage sensed via resistor R9 and fed into the FWD pin of the IC. In continuous conduction mode of operation, the switch is turned off just prior to the secondary-side’s commanding a new switching cycle from the primary. In discontinuous conduction mode of operation, the power switch is turned off when the voltage drop across the switch falls below a threshold of 0 V. Secondary-side control of the primary-side power switch avoids any possibility of cross conduction of the two switchs and provides extremely reliable synchronous rectification. The secondary-side of the IC is self-powered from either the secondary winding forward voltage or the output voltage. Capacitor C12 connected to the BPS pin of InnoSwitch3-CE IC U1, provides decoupling for the internal circuitry. During CC operation, when the output voltage falls, the device will directly power itself from the secondary winding. During the on-time of the primary-side power switch, the forward voltage that appears across the secondary winding is used to charge the decoupling capacitor C12 via resistor R9 and an internal regulator. This allows output current regulation to be maintained down to ~3 V. Below this level the unit enters auto-restart until the output load is reduced. Output current is sensed between the IS and GND pins with a threshold of approximately 35 mV to reduce losses. Once the current sense threshold is exceeded the device adjusts the number of switch pulses to maintain a fixed output current. The output voltage is sensed via resistor divider R4 and R8. Output voltage is regulated so as to achieve a voltage of 1.265 V on the FEEDBACK pin. Capacitor C9 provides noise filtering of the signal at the FEEDBACK pin. 9 www.power.com Rev. I 09/21 InnoSwitch3-CE Resistors R6 and R7 provide line voltage sensing and provide a current to U1, which is proportional to the DC voltage across capacitor C3. At approximately 95 V DC, the current through these resistors exceeds the line undervoltage threshold, which results in enabling of U1. At approximately 435 VDC, the current through these resistors exceeds the line overvoltage threshold, which results in disabling of U1. Key Application Considerations Output Power Table The data sheet output power table (Table 1) represents the maximum practical continuous output power level that can be obtained under the following conditions: 1. The minimum DC input voltage is 90 V or higher for 85 VAC input, 220 V or higher for 230 VAC input or 115 VAC with a voltagedoubler. Input capacitor voltage should be sized to meet these criteria for AC input designs. 2. Efficiency assumptions depend on power level. Smallest device power level assumes efficiency >84% increasing to >89% for the largest device. 3. Transformer primary inductance tolerance of ±10%. 4. Reflected output voltage (VOR) is set to maintain KP = 0.8 at minimum input voltage for universal line and KP = 1 for high input line designs. 5. Maximum conduction losses for adapters is limited to 0.6 W, 0.8 W for open frame designs. 6. Increased current limit is selected for peak and open frame power columns and standard current limit for adapter columns. 7. The part is board mounted with SOURCE pins soldered to a sufficient area of copper and/or a heat sink to keep the SOURCE pin temperature at or below 110 °C. 8. Ambient temperature of 50 °C for open frame designs and 40 °C for sealed adapters. 9. Below a value of 1, KP is the ratio of ripple to peak primary current. To prevent reduced power delivery, due to premature termination of switching cycles, a transient KP limit of ≥0.25 is recommended. This prevents the initial current limit (IINT) from being exceeded at switch turn-on. Primary-Side Overvoltage Protection (Latch-Off/Auto-Restart Mode) Primary-side output overvoltage protection provided by the InnoSwitch3-CE IC uses an internal protection depending on H code that is triggered by a threshold current of ISD into the PRIMARY BYPASS pin. In addition to an internal filter, the PRIMARY BYPASS pin capacitor forms an external filter helping noise immunity. For the bypass capacitor to be effective as a high frequency filter, the capacitor should be located as close as possible to the SOURCE and PRIMARY BYPASS pins of the device. The primary sensed OVP function can be realized by connecting a series combination of a Zener diode, a resistor and a blocking diode from the rectified and filtered bias winding voltage supply to the PRIMARY BYPASS pin. The rectified and filtered bias winding output voltage may be higher than expected (up to 1.5X or 2X the desired value) due to poor coupling of the bias winding with the output winding and the resulting ringing on the bias winding voltage waveform. It is therefore recommended that the rectified bias winding voltage be measured. This measurement should be ideally done at the lowest input voltage and with highest load on the output. This measured voltage should be used to select the components required to achieve primary sensed OVP. It is recommended that a Zener diode with a clamping voltage approximately 6 V lower than the bias winding rectified voltage at which OVP is expected to be triggered be selected. A forward voltage drop of 1 V can be assumed for the blocking diode. A small signal standard recovery diode is recommended. The blocking diode prevents any reverse current discharging the bias capacitor during start-up. Finally, the value of the series resistor required can be calculated such that a current higher than ISD will flow into the PRIMARY BYPASS pin during an output overvoltage. Reducing No-load Consumption The InnoSwitch3-CE IC can start in self-powered mode, drawing energy from the BYPASS pin capacitor charged through an internal current source. Use of a bias winding is however required to provide supply current to the PRIMARY BYPASS pin once the InnoSwitch3-CE IC has started switching. An auxiliary (bias) winding provided on the transformer serves this purpose. A bias winding driver supply to the PRIMARY BYPASS pin enables design of power supplies with no-load power consumption less than 15 mW. Resistor R10 shown in Figure 11 should be adjusted to achieve the lowest no-load input power. Secondary-Side Overvoltage Protection (Auto-Restart Mode) The secondary-side output overvoltage protection provided by the InnoSwitch3-CE IC uses an internal auto restart circuit that is triggered by an input current exceeding a threshold of IBPS(SD) into the SECONDARY BYPASS pin. The direct output sensed OVP function can be realized by connecting a Zener diode from the output to the SECONDARY BYPASS pin. The Zener diode voltage needs to be the difference between 1.25 × VOUT and 4.4 V − the SECONDARY BYPASS pin voltage. It is necessary to add a low value resistor in series with the OVP Zener diode to limit the maximum current into the SECONDARY BYPASS pin. Selection of Components Components for InnoSwitch3-CE Primary-Side Circuit BPP Capacitor A capacitor connected from the PRIMARY BYPASS pin of the InnoSwitch3-CE IC to GND provides decoupling for the primary-side controller and also selects current limit. A 0.47 mF or 4.7 mF capacitor may be used. Though electrolytic capacitors can be used, often surface mount multi-layer ceramic capacitors are preferred for use on double sided boards as they enable placement of capacitors close to the IC. Their small size also makes it ideal for compact power supplies. At least 10 V, 0805 or larger size rated X5R or X7R dielectric capacitors are recommended to ensure that minimum capacitance requirements are met. The ceramic capacitor type designations, such as X7R, X5R from different manufacturers or different product families do not have the same voltage coefficients. It is recommended that capacitor datasheets be reviewed to ensure that the selected capacitor will not have more than 20% drop in capacitance at 5 V. Do not use Y5U or Z5U / 0603 rated MLCC due to this type of SMD ceramic capacitor has very poor voltage and temperature coefficient characteristics. Bias Winding and External Bias Circuit The internal regulator connected from the DRAIN pin of the switch to the PRIMARY BYPASS pin of the InnoSwitch3-CE primary-side controller charges the capacitor connected to the PRIMARY BYPASS pin to achieve start-up. A bias winding should be provided on the transformer with a suitable rectifier and filter capacitor to create a bias supply that can be used to supply at least 1 mA of current to the PRIMARY BYPASS pin. The turns ratio for the bias winding should be selected such that 7 V is developed across the bias winding at the lowest rated output voltage of the power supply at the lowest load condition. If the voltage is lower than this, no-load input power will increase. The bias current from the external circuit should be set to approximately ISI(MAX) to achieve lowest no-load power consumption when operating 10 www.power.com Rev. I 09/21 InnoSwitch3-CE the power supply at 230 VAC input, (VBPP > 5 V). A glass passivated standard recovery rectifier diode with low junction capacitance is recommended to avoid the snappy recovery typically seen with fast or ultrafast diodes that can lead to higher radiated EMI. An aluminum capacitor of at least 22 mF with a voltage rating 1.2 times greater than the highest voltage developed across the capacitor is recommended. Highest voltage is typically developed across this capacitor when the supply is operated at the highest rated output voltage and load with the lowest input AC supply voltage. Line UV and OV Protection Resistors connected from the UNDER/OVER INPUT VOLTAGE pin to the DC bus enable sensing of input voltage to provide line undervoltage and overvoltage protection. For a typical universal input application, a resistor value of 3.8 MW is recommended. Figure 16 shows circuit configurations that enable either the line UV or the line OV feature only to be enabled. InnoSwitch3-CE features a primary sensed OV protection feature that can be used to latch-off the power supply. Once the power supply is latched off, it can be reset if the UNDER/OVER INPUT VOLTAGE pin current is reduced to zero. Once the power supply is latched off, even after the input supply is turned off, it can take considerable amount of time to reset the InnoSwitch3-CE controller as the energy stored in the DC bus will continue to provide current to the controller. A fast AC reset can be achieved using the modified circuit configuration shown in Figure 17. The voltage across capacitor CS reduces rapidly after input supply is disconnected reducing current into the INPUT VOLTAGE MONITOR pin of the InnoSwitch3-CE IC and resetting the InnoSwitch3-CE controller. Primary Sensed OVP (Overvoltage Protection) The voltage developed across the output of the bias winding tracks the power supply output voltage. Though not precise, a reasonably accurate detection of the amplitude of the output voltage can be achieved by the primary-side controller using the bias winding voltage. A Zener diode connected from the bias winding output to the PRIMARY BYPASS pin can reliably detect a secondary overvoltage fault and cause the primary-side controller to latch-off/auto-restart depending on H code. It is recommended that the highest voltage at the output of the bias winding should be measured for normal steadystate conditions (at full load and lowest input voltage) and also under transient load conditions. A Zener diode rated for 1.25 times this measured voltage will typically ensure that OVP protection will only operate in case of a fault. Primary-Side Snubber Clamp A snubber circuit should be used on the primary-side as shown in Figure 11. This prevents excess voltage spikes at the drain of the switch at the instant of turn-off of the switch during each switching cycle though conventional RCD clamps can be used. RCDZ clamps offer the highest efficiency. The circuit example shown in Figure 11 uses an RCD clamp with a resistor in series with the clamp diode. This resistor dampens the ringing at the drain and also limits the reverse current through the clamp diode during reverse recovery. Standard recovery glass passivated diodes with low junction capacitance are recommended as these enable partial energy recovery from the clamp thereby improving efficiency. Components for InnoSwitch3-CE Secondary-Side Circuit SECONDARY BYPASS Pin – Decoupling Capacitor A 2.2 mF, 10 V / X7R or X5R / 0805 or larger size multi-layer ceramic capacitor should be used for decoupling the SECONDARY BYPASS pin of the InnoSwitch3-CE IC. Since the SECONDARY BYPASS Pin voltage needs to be 4.4 V before the output voltage reaches the regulation voltage level, a significantly higher BPS capacitor value could lead to output voltage overshoot during start-up. Values lower than 1.5 mF may not enough capacitance, which can cause unpredictable operation. The capacitor must be located adjacent to the IC pins. At least 10 V is recommended voltage rating to give enough margin from BPS voltage, and 0805 size is necessary to guarantee the actual value in operation since the capacitance of ceramic capacitors drops significantly with applied DC voltage especially with small package SMD such as 0603. 6.3 V / 0603 / X5U or Z5U type of MLCC is not recommended for this reason. The ceramic capacitor type designations, such as X7R, X5R from different manufacturers or different product families do not have the same voltage coefficients. It is recommended that capacitor data sheets be reviewed to ensure that the selected capacitor will not have more than 20% drop in capacitance at 4.4 V. Capacitors with X5R or X7R dielectrics should be used for best results. FORWARD Pin Resistor A 47 W, 5% resistor is recommended to ensure sufficient IC supply current. A higher or lower resistor value should not be used as it can affect device operation such as the timing of the synchronous rectifier drive. Figures 12, 13, 14 and 15 below show examples of unacceptable and acceptable FORWARD pin voltage waveforms. VD is forward voltage drop across the SR. 0V VSR(TH) VD PI-8392-051818 Figure 12. Unacceptable FORWARD Pin Waveform After Handshake with SR Switch Conduction During Flyback Cycle. 0V VSR(TH) VD PI-8393-051818 Figure 13. Acceptable FORWARD Pin Waveform After Handshake with SR Switch Conduction During Flyback Cycle. 11 www.power.com Rev. I 09/21 InnoSwitch3-CE voltage of 1.5 V to 2.5 V are ideal although switchs with a threshold voltage (absolute maximum) as high as 4 V may be used provided their data sheets specify RDS(ON) across temperature for a gate voltage of 4.5 V. 0V VSR(TH) VD t1 t2 PI-8394-051818 Figure 14. Unacceptable FORWARD Pin Waveform before Handshake with Body Diode Conduction During Flyback Cycle. Note: If t1 + t2 = 1.5 ms ± 50 ns, the controller may fail the handshake and trigger a primary bias winding OVP latch-off/auto-restart. There is a slight delay between the commencement of the flyback cycle and the turn-on of the SR FET. During this time, the body diode of the SR FET conducts. If an external parallel Schottky diode is used, this current mostly flows through the Schottky diode. Once the InnoSwitch3-CE IC detects end of the flyback cycle, voltage across SR FET RDS(ON) reaches 0 V, any remaining portion of the flyback cycle is completed with the current commutating to the body diode of the SR FET or the external parallel Schottky diode. Use of the Schottky diode parallel to the SR FET may provide higher efficiency and typically a 1 A surface mount Schottky diode is adequate. However, the gains are modest. For a 5 V, 2 A design the external diode adds ~0.1% to full load efficiency at 85 VAC and ~0.2% at 230 VAC. The voltage rating of the Schottky diode and the SR FET should be at least 1.4 times the expected peak inverse voltage (PIV) based on the turns ratio used for the transformer. 60 V rated FETs and diodes are suitable for most 5 V designs that use a VOR < 60 V, and 100 V rated FETs and diodes are suitable for 12 V designs. The interaction between the leakage reactance of the output windings and the SR FET capacitance (COSS) leads to ringing on the voltage waveform at the instance of voltage reversal at the winding due to primary switch turn-on. This ringing can be suppressed using an RC snubber connected across the SR FET. A snubber resistor in the range of 10 W to 47 W may be used (higher resistance values lead to noticeable drop in efficiency). A capacitance value of 1 nF to 2.2 nF is adequate for most designs. Output Capacitor Low ESR aluminum electrolytic capacitors are suitable for use with most high frequency flyback switching power supplies, though the use of aluminum-polymer solid capacitors have gained considerable popularity due to their compact size, stable temperature characteristics, extremely low ESR and high RMS ripple current rating. These capacitors enable the design of ultra-compact chargers and adapters. 0V VSR(TH) VD PI-8393-051818 Figure 15. Acceptable FORWARD Pin Waveform before Handshake with Body Diode Conduction During Flyback Cycle. SR Switch Operation and Selection Although a simple diode rectifier and filter works for the output, use of an SR FET enables the significant improvement in operating efficiency often necessary to meet the European CoC and the U.S. DoE energy efficiency requirements. The secondary-side controller turns on the SR FET once the flyback cycle begins. The SR FET gate should be tied directly to the SYNCHRONOUS RECTIFIER DRIVE pin of the InnoSwitch3-CE IC (no additional resistors should be connected in the gate circuit of the SR FET). The SR FET is turned off once the VDS of the SR FET reaches 0 V. A FET with 18 mW RDS(ON) is appropriate for a 5 V, 2 A output, and a FET with 8 mW RDS(ON) is suitable for designs rated with a 12 V, 3 A output. The SR FET driver uses the SECONDARY BYPASS pin for its supply rail, and this voltage is typically 4.4 V. A FET with a high threshold voltage is therefore not suitable; FETs with a threshold Typically, 200 mF to 300 mF of aluminum-polymer capacitance per ampere of output current is adequate. The other factor that influences choice of the capacitance is the output ripple. Ensure that capacitors with a voltage rating higher than the highest output voltage plus sufficient margin be used. Output Voltage Feedback Circuit The output voltage FEEDBACK pin voltage is 1.265 V [VFB]. A voltage divider network should be connected at the output of the power supply to divide the output voltage such that the voltage at the FEEDBACK pin will be 1.265 V when the output is at its desired voltage. The lower feedback divider resistor should be tied to the SECONDARY GROUND pin. A 300 pF (or smaller) decoupling capacitor should be connected at the FEEDBACK pin to the SECONDARY GROUND pin of the InnoSwitch3-CE IC. This capacitor should be placed close to the InnoSwitch3-CE IC. 12 www.power.com Rev. I 09/21 InnoSwitch3-CE Recommendations for Circuit Board Layout R1 See Figure 18 for a recommended circuit board layout for an InnoSwitch3-CE based power supply. R2 Single-Point Grounding Use a single-point ground connection from the input filter capacitor to the area of copper connected to the SOURCE pins. Bypass Capacitors The PRIMARY BYPASS and SECONDARY BYPASS pin capacitor must be located directly adjacent to the PRIMARY BYPASS-SOURCE and SECONDARY BYPASS-SECONDARY GROUND pins respectively and connections to these capacitors should be routed with short traces. FB GND V BPS D SR 1N4148 FWD + VOUT S Primary Loop Area The area of the primary loop that connects the input filter capacitor, transformer primary and IC should be kept as small as possible. IS BPP InnoSwitch3-CE PI-8403-081617 + R1 Thermal Considerations The SOURCE pin is internally connected to the IC lead frame and provides the main path to remove heat from the device. Therefore the SOURCE pin should be connected to a copper area underneath the IC to act not only as a single point ground, but also as a heat sink. As this area is connected to the quiet source node, it can be maximized for good heat sinking without compromising EMI performance. Similarly for the output SR switch, maximize the PCB area connected to the pins on the package through which heat is dissipated from the SR switch. FB GND BPS V SR D FWD R2 6.2 V VOUT S IS BPP Primary Clamp Circuit A clamp is used to limit peak voltage on the DRAIN pin at turn-off. This can be achieved by using an RCD clamp or a Zener diode (~200 V) and diode clamp across the primary winding. To reduce EMI, minimize the loop from the clamp components to the transformer and IC. InnoSwitch3-CE PI-8404-051818 Figure 16. (Top) Line OV Only; (Bottom) Line UV Only. InnoSwitch3-CE CS 100 nF FB GND BPS V SR D FWD SR FET VOUT Primary FET and Controller S BPP IS Secondary Control IC PI-8407-081617 Figure 17. Fast AC Reset Configuration. 13 www.power.com Rev. I 09/21 InnoSwitch3-CE Sufficient copper area should be provided on the board to keep the IC temperature safely below the absolute maximum limits. It is recommended that the copper area provided for the copper plane on which the SOURCE pin of the IC is soldered is sufficiently large to keep the IC temperature below 110 °C when operating the power supply at full rated load and at the lowest rated input AC supply voltage. Y Capacitor The Y capacitor should be placed directly between the primary input filter capacitor positive terminal and the output positive or return terminal of the transformer secondary. This routes high amplitude common mode surge currents away from the IC. Note – if an input pi-filter (C, L, C) EMI filter is used then the inductor in the filter should be placed between the negative terminals of the input filter capacitors. Output SR Switch For best performance, the area of the loop connecting the secondary winding, the output SR switch and the output filter capacitor, should be minimized. ESD Sufficient clearance should be maintained (>8 mm) between the primary-side and secondary-side circuits to enable easy compliance with any ESD / hi-pot requirements. The spark gap is best placed directly between output positive rail and one of the AC inputs. In this configuration a 6.4 mm spark gap is often sufficient to meet the creepage and clearance requirements of many applicable safety standards. This is less than the primary to secondary spacing because the voltage across spark gap does not exceed the peak of the AC input. Drain Node The drain switching node is the dominant noise generator. As such, the components connected the drain node should be placed close to the IC and away from sensitive feedback circuits. The clamp circuit components should be located physically away from the PRIMARY BYPASS pin and trace lengths minimized. The loop area of the loop comprising of the input rectifier filter capacitor, the primary winding and the IC primary-side switch should be kept as small as possible. 14 www.power.com Rev. I 09/21 InnoSwitch3-CE Layout Example Optional Y capacitor connection to the plus bulk rail on the primaryside for surge protection Maximize source area for good heat sinking PCB - Top Side Keep BPP and BPS capacitors near the IC 6.4 mm spark gap Keep drain and clamp loop short; Keep drain components away from BPP and VOLTAGE pin circuitry Keep FEEDBACK pin decoupling capacitor close to the Feedback pin Place forward and feedback sense resistors near the IC Maximize drain area of SF FET for good heat sinking Maximize source area for good heat sinking Keep output SF FET and output filter capacitor loop short Place VOLTAGE pin sense resistor close to the VOLTAGE pin Keep IS-GND sense resistor close to IC In order to increase ESD immunity and to meet isolation requirement, no traces are routed beneath the IC PCB - Bottom Side PI-8396-091919 Figure 18. PCB. 15 www.power.com Rev. I 09/21 InnoSwitch3-CE Recommendations for EMI Reduction 1. Appropriate component placement and small loop areas of the primary and secondary power circuits help minimize radiated and conducted EMI. Care should be taken to achieve a compact loop area. 2. A small capacitor in parallel to the clamp diode on the primaryside can help reduce radiated EMI. 3. A resistor in series with the bias winding helps reduce radiated EMI. 4. Common mode chokes are typically required at the input of the power supply to sufficiently attenuate common mode noise. However the same performance can be achieved by using shield windings on the transformer. Shield windings can also be used in conjunction with common mode filter inductors at input to improve conducted and radiated EMI margins. 5. Adjusting SR switch RC snubber component values can help reduce high frequency radiated and conducted EMI. 6. A pi-filter comprising differential inductors and capacitors can be used in the input rectifier circuit to reduce low frequency differential EMI. 7. A 1 mF ceramic capacitor connected at the output of the power supply helps to reduce radiated EMI. Recommendations for Transformer Design Transformer design must ensure that the power supply delivers the rated power at the lowest input voltage. The lowest voltage on the rectified DC bus depends on the capacitance of the filter capacitor used. At least 2 mF/W is recommended to always keep the DC bus voltage above 70 V, though 3 mF/W provides sufficient margin. The ripple on the DC bus should be measured to confirm the design calculations for transformer primary-winding inductance selection. Switching Frequency (fSW) It is a unique feature in InnoSwitch3-CE that for full load, the designer can set the switching frequency to between 25 kHz to 95 kHz. For lowest temperature, the switching frequency should be set to around 60 kHz. For a smaller transformer, the full load switching frequency needs to be set to 95 kHz. When setting the full load switching frequency it is important to consider primary inductance and peak current tolerances to ensure that average switching frequency does not exceed 110 kHz which may trigger auto-restart due to overload protection. The following table provides a guide to frequency selection based on device size. This represents the best compromise between overall device losses (conduction losses and switching losses) based on the size of the integrated high-voltage switch. INN3162C and INN3163C 85-90 kHz INN3164C and INN3165C 80 kHz INN3166C 75 kHz INN3167C 70 kHz INN3168C 65 kHz Reflected Output Voltage, VOR (V) This parameter describes the effect on the primary switch drain voltage of the secondary-winding voltage during diode/SR conduction which is reflected back to the primary through the turns ratio of the transformer. To make full use of QR capability and ensure flattest efficiency over line/load, set reflected output voltage (VOR) to maintain KP = 0.8 at minimum input voltage for universal input and KP = 1 for high-line-only conditions. Consider the following for design optimization: 1. Higher VOR allows increased power delivery at VMIN, which minimizes the value of the input capacitor and maximizes power delivery from a given InnoSwitch3-CE device. 2. Higher VOR reduces the voltage stress on the output diodes and SR switchs. 3. Higher VOR increases leakage inductance which reduces power supply efficiency. 4. Higher VOR increases peak and RMS current on the secondary-side which may increase secondary-side copper and diode losses. There are some exceptions to this. For very high output currents the VOR should be reduced to get highest efficiency. For output voltages above 15 V, VOR should be higher to maintain an acceptable PIV across the output synchronous rectifier. Ripple to Peak Current Ratio, KP A KP below 1 indicates continuous conduction mode, where KP is the ratio of ripple-current to peak-primary-current (Figure 19). KP ≡ KRP = IR / IP A value of KP higher than 1, indicates discontinuous conduction mode. In this case KP is the ratio of primary switch off-time to the secondary diode conduction-time. KP ≡ KDP = (1 – D) x T/ t = VOR × (1 – DMAX) / ((VMIN – VDS) × DMAX) It is recommended that a KP close to 0.9 at the minimum expected DC bus voltage should be used for most InnoSwitch3-CE designs. A KP value of 1 T = 1/fS Primary D×T (1-D) × T = t Secondary (b) Borderline Discontinuous/Continuous, KP = 1 PI-2578-103114 Figure 20. Discontinuous Conduction Mode Current Waveform, KP > 1. Quick Design Checklist As with any power supply, the operation of all InnoSwitch3-CE designs should be verified on the bench to make sure that component limits are not exceeded under worst-case conditions. As a minimum, the following tests are strongly recommended: 1. Maximum Drain Voltage – Verify that VDS of InnoSwitch3-CE and SR FET do not exceed 90% of breakdown voltages at the highest input voltage and peak (overload) output power in normal operation and during start-up. 2. Maximum Drain Current – At maximum ambient temperature, maximum input voltage and peak output (overload) power. Review drain current waveforms for any signs of transformer saturation or excessive leading-edge current spikes at start-up. Repeat tests under steady-state conditions and verify that the leading edge current spike is below ILIMIT(MIN) at the end of tLEB(MIN). Under all conditions, the maximum drain current for the primary switch should be below the specified absolute maximum ratings. 3. Thermal Check – At specified maximum output power, minimum input voltage and maximum ambient temperature, verify that temperature specification limits for InnoSwitch3-CE IC, transformer, output SR FET, and output capacitors are not exceeded. Enough thermal margin should be allowed for part-to-part variation of the RDS(ON) of the InnoSwitch3-CE IC. Under low-line, maximum power, a maximum InnoSwitch3-CE SOURCE pin temperature of 110 °C is recommended to allow for these variations. 18 www.power.com Rev. I 09/21 InnoSwitch3-CE Absolute Maximum Ratings1,2 DRAIN Pin Voltage .................................................... -0.3 V to 650 V DRAIN Pin Peak Current: INN3162C........................................1.60 A3 INN3163C........................................2.24 A3 INN3164C........................................3.26 A3 INN3165C........................................3.87 A3 INN3166C........................................4.88 A3 INN3167C........................................5.57 A3 INN3168C........................................6.24 A3 BPP/BPS Pin Voltage ........................................................-0.3 to 6 V BPP/BPS Current .................................................................. 100 mA FWD Pin Voltage ....................................................... -1.5 V to 150 V FB Pin Voltage ..............................................................-0.3 V to 6 V SR Pin Voltage ..............................................................-0.3 V to 6 V VOUT Pin Voltage ....................................................... -0.3 V to 27 V V Pin Voltage ............................................................ -0.3 V to 650 V IS Pin Voltage6 ...........................................................-0.3 V to 0.3 V Storage Temperature ...................................................-65 to 150 °C Operating Junction Temperature4 ................................. -40 to 150 °C Ambient Temperature ..................................................-40 to 105 °C Lead Temperature5 ................................................................ 260 °C Notes: 1. All voltages referenced to SOURCE and Secondary GROUND, TA = 25 °C. 2. Maximum ratings specified may be applied one at a time without causing permanent damage to the product. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect product reliability. 3. Please refer to Figure 21 about maximum allowable voltage and current combinations. 4. Normally limited by internal circuitry. 5. 1/16” from case for 5 seconds. 6. Absolutely maximum voltage for less than 500 msec is 3 V. Thermal Resistance Thermal Resistance: (qJA)............................. 76 °C/W1, 65 °C/W2 (qJC)..............................................8 °C/W3 Notes: 1. Soldered to 0.36 sq. inch (232 mm2) 2 oz. (610 g/m2) copper clad. 2. Soldered to 1 sq. inch (645 mm2), 2 oz. (610 g/m2) copper clad. 3. The case temperature is measured on the top of the package. 19 www.power.com Rev. I 09/21 InnoSwitch3-CE Symbol Conditions SOURCE = 0 V TJ = -40 °C to 125 °C (Unless Otherwise Specified) Min Typ Max Units Startup Switching Frequency fSW TJ = 25 °C 23 25 27 kHz Jitter Modulation Frequency fM TJ = 25 °C fSW = 100 kHz 0.80 1.25 1.70 kHz Maximum On-Time tON(MAX) TJ = 25 °C 12.4 14.6 16.9 µs Minimum Primary Feedback Block-Out Timer tBLOCK tOFF(MIN) µs µA Parameter Control Functions IS1 BPP Supply Current IS2 BPP Pin Charge Current VBPP = VBPP + 0.1 V (Switch not Switching) TJ = 25 °C VBPP = VBPP + 0.1 V (Switch Switching at 132 kHz) TJ = 25 °C 145 200 300 INN3162C 0.29 0.39 0.58 INN3163C 0.32 0.43 0.61 INN3164C 0.38 0.50 0.69 INN3165C 0.49 0.65 1.03 INN3166C 0.64 0.86 1.21 INN3167C 0.77 1.03 1.38 INN3168C 0.90 1.20 1.75 ICH1 VBP = 0 V, TJ = 25 °C -1.75 -1.35 -0.88 ICH2 VBP = 4 V, TJ = 25 °C -5.98 -4.65 -3.32 4.65 4.9 5.15 mA mA BPP Pin Voltage VBPP BPP Pin Voltage Hysteresis VBPP(H) TJ = 25 °C BPP Shunt Voltage VSHUNT IBPP = 2 mA 5.15 5.36 5.65 V BPP Power-Up Reset Threshold Voltage VBPP(RESET) TJ = 25 °C 2.8 3.15 3.5 V UV/OV Pin Brown-In Threshold IUV+ TJ = 25 °C 23.9 26.1 28.2 µA UV/OV Pin Brown-Out Threshold IUV- TJ = 25 °C 21.0 23.7 25.5 µA Brown-Out Delay Time tUV- TJ = 25 °C UV/OV Pin Line Overvoltage Threshold IOV+ TJ = 25 °C UV/OV Pin Line Overvoltage Hysteresis IOV(H) TJ = 25 °C IOV- TJ = 25 °C UV/OV Pin Line Overvoltage Recovery Threshold 0.39 V 35 106 115 7 100 V ms 118 µA µA µA 20 www.power.com Rev. I 09/21 InnoSwitch3-CE Symbol Conditions SOURCE = 0 V TJ = -40 °C to 125 °C (Unless Otherwise Specified) VOLTAGE Pin Line Overvoltage Deglitch Filter tOV+ TJ = 25 °C See Note B VOLTAGE Pin Voltage Rating VV TJ = 25 °C See Note B Parameter Min Typ Max Units Line Fault Protection 3 µs 650 V Circuit Protection Standard Current Limit (BPP) Capacitor = 0.47 mF ILIMIT See Note C Increased Current Limit (BPP) Capacitor = 4.7 mF ILIMIT+1 See Note C Overload Detection Frequency fOVL di/dt = 138 mA/ms TJ = 25 °C INN3162C 418 450 482 di/dt = 163 mA/ms TJ = 25 °C INN3163C 511 550 589 di/dt = 188 mA/ms TJ = 25 °C INN3164C 697 750 803 di/dt = 213 mA/ms TJ = 25 °C INN3165C 883 950 1017 di/dt = 238 mA/ms TJ = 25 °C INN3166C 1162 1250 1338 di/dt = 300 mA/ms TJ = 25 °C INN3167C 1348 1450 1552 di/dt = 375 mA/ms TJ = 25 °C INN3168C 1534 1650 1766 di/dt = 138 mA/ms TJ = 25 °C INN3162C 500 550 600 di/dt = 163 mA/ms TJ = 25 °C INN3163C 591 650 709 di/dt = 188 mA/ms TJ = 25 °C INN3164C 864 950 1036 di/dt = 213 mA/ms TJ = 25 °C INN3165C 1046 1150 1254 di/dt = 238 mA/ms TJ = 25 °C INN3166C 1319 1450 1581 di/dt = 300 mA/ms TJ = 25 °C INN3167C 1501 1650 1799 di/dt = 375 mA/ms TJ = 25 °C INN3168C 1683 1850 2017 102 110 118 TJ = 25 °C mA mA kHz 21 www.power.com Rev. I 09/21 InnoSwitch3-CE Symbol Conditions SOURCE = 0 V TJ = -40 °C to 125 °C (Unless Otherwise Specified) Min Typ Max Units BYPASS Pin Latching/ Auto-Restart Shutdown Threshold Current ISD TJ = 25 °C 6.0 7.5 11.3 mA Auto-Restart On-Time t AR TJ = 25 °C 75 82 89 ms Auto-Restart Trigger Skip Time t AR(SK) TJ = 25 °C Auto-Restart Off-Time t AR(OFF) TJ = 25 °C 1.70 t AR(OFF)SH TJ = 25 °C 0.17 Parameter Circuit Protection (cont.) Short Auto-Restart Off-Time 1.3 sec 2.11 sec 0.20 0.23 sec TJ = 25 °C 6.50 7.48 TJ = 100 °C 10.08 11.60 TJ = 25 °C 4.90 5.64 TJ = 100 °C 7.60 8.74 TJ = 25 °C 3.20 3.68 TJ = 100 °C 4.96 5.70 TJ = 25 °C 1.95 2.24 TJ = 100 °C 3.02 3.47 TJ = 25 °C 1.30 1.50 TJ = 100 °C 2.02 2.53 TJ = 25 °C 1.02 1.17 TJ = 100 °C 1.58 1.82 TJ = 25 °C 0.86 0.99 TJ = 100 °C 1.34 1.54 Output INN3162C ID = ILIMIT+1 INN3163C ID = ILIMIT+1 INN3164C ID = ILIMIT+1 ON-State Resistance RDS(ON) INN3165C ID = ILIMIT+1 INN3166C ID = ILIMIT+1 INN3167C ID = ILIMIT+1 INN3168C ID = ILIMIT+1 OFF-State Drain Leakage Current IDSS1 VBPP = VBPP + 0.1 V VDS = 80% BVDSS TJ = 125 °C IDSS2 VBPP = VBPP + 0.1 V VDS = 325 V TJ = 25 °C Drain Supply Voltage 200 15 TSD See Note A Thermal Shutdown Hysteresis TSD(H) See Note A 135 mA mA 50 Thermal Shutdown W V 142 70 150 °C °C 22 www.power.com Rev. I 09/21 InnoSwitch3-CE Symbol Conditions SOURCE = 0 V TJ = -40 °C to 125 °C (Unless Otherwise Specified) Min Typ Max Units FEEDBACK Pin Voltage VFB TJ = 25 °C 1.250 1.265 1.280 V Maximum Switching Frequency fSREQ TJ = 25 °C 118 132 145 kHz FEEDBACK Pin/OUTPUT VOLTAGE Pin AutoRestart Threshold VFB(AR) V VO(AR) See Feature Code Addendum FEEDBACK Pin/OUTPUT VOLTAGE Pin AutoRestart Timer tFB(AR) tVO(AR) tIS(AR) TJ = 25 °C 49.5 BPS Pin Current at No-Load ISNL TJ = 25 °C 325 485 mA BPS Pin Voltage VBPS 4.20 4.40 4.60 V BPS Pin Undervoltage Threshold VBPS(UVLO)(TH) 3.60 3.80 4.00 V BPS Pin Undervoltage Hysteresis VBPS(UVLO)(H) Parameter Secondary ms 0.65 V Current Limit Voltage Threshold ISV(TH) FWD Pin Voltage VFWD 150 Minimum Off-Time tOFF(MIN) 2.48 3.38 4.37 ms Soft-Start Frequency Ramp Time tSS(RAMP) TJ = 25 °C 7.5 11.75 19 ms φCD See Feature Code Addendum Cable Drop Compensation BPS Pin Latch/ Auto-Restart Command Shutdown Threshold Current IBPS(SD) FEEDBACK Pin Short-Circuit VFB(OFF) Set by External Resistor TJ = 25 °C 35.17 36.62 mV V mV 5.2 TJ = 25 °C 35.90 8.9 12 mA 112 135 mV 23 www.power.com Rev. I 09/21 InnoSwitch3-CE Parameter Symbol Conditions SOURCE = 0 V TJ = -40 °C to 125 °C (Unless Otherwise Specified) Min Typ Max Units 4.2 4.4 4.6 V -2.5 0 mV Synchronous Rectifier @ TJ = 25 °C SR Pin Drive Voltage VSR SR Pin Voltage Threshold VSR(TH) SR Pin Pull-Up Current ISR(PU) TJ = 25 °C CLOAD = 2 nF, fSW = 100 kHz 125 165 195 mA SR Pin Pull-Down Current ISR(PD) TJ = 25 °C CLOAD = 2 nF, fSW = 100 kHz 87 97 115 mA Rise Time tR TJ = 25 °C CLOAD = 2 nF See Note B 10-90% 50 ns Fall Time tF TJ = 25 °C CLOAD = 2 nF See Note B 90-10% 80 ns Output Pull-Up Resistance RPU TJ = 25 °C VBPS = 4.4 V ISR = 10 mA 7.2 8.3 12 W Output Pull-Down Resistance RPD TJ = 25 °C VBPS = 4.4 V ISR = 10 mA 10.0 12.1 13.4 W NOTES: A. This parameter is derived from characterization. B. This parameter is guaranteed by design. C. To ensure correct current limit it is recommended that nominal 0.47 mF / 4.7 mF capacitors are used. In addition, the BPP capacitor value tolerance should be equal or better than indicated below across the ambient temperature range of the target application. The minimum and maximum capacitor values are guaranteed by characterization. Nominal BPP Pin Capacitor Value BPP Capacitor Value Tolerance Minimum Maximum 0.47 mF -60% +100% 4.7 mF -50% N/A Recommended to use at least 10 V / 0805 / X7R SMD MLCC. 24 www.power.com Rev. I 09/21 InnoSwitch3-CE PI-8418-082417 1.0 1.4 Scaling Factors: INN3162 1.00 INN3163 1.40 INN3164 1.95 INN3165 3.20 INN3166 4.80 INN3167 6.10 INN3168 7.65 1.2 Drain Current (mA) PI-8505-072519 Drain Current (A) (Normalized to Absolute MaximumCurrent Rating) Typical Performance Curves 1.0 0.8 0.6 0.4 TCASE = 25 °C TCASE = 100 °C 0.2 0 100 200 300 400 500 0 600 700 Drain Voltage (V) 75 Power (mW) 100 4 6 8 10 Figure 22. Output Characteristics. PI-8416-082417 Drain Capacitance (pF) Scaling Factors: INN3162 1.00 INN3163 1.40 INN3164 1.95 INN3165 3.20 INN3166 4.80 INN3167 6.10 INN3168 7.65 1000 2 DRAIN Voltage (V) Figure 21. Maximum Allowable Drain Current vs. Drain Voltage. 10000 0 PI-8417-082917 0.0 Scaling Factors: INN3162 1.00 INN3163 1.40 INN3164 1.95 INN3165 3.20 INN3166 4.80 INN3167 6.10 INN3168 7.65 50 25 10 Switching Frequency = 100 kHz 1 100 200 300 400 500 600 Drain Voltage (V) 50 75 100 125 150 Junction Temperature (°C) Figure 25. Breakdown vs. Temperature. SYNCHRONOUS RECTIFIER DRIVE Pin Voltage Limits (V) PI-2213-012301 Breakdown Voltage (Normalized to 25 °C) 1.0 25 200 300 400 500 600 Figure 24. Drain Capacitance Power. 1.1 0 100 Drain Voltage (V) Figure 23. COSS vs. Drain Voltage. 0.9 -50 -25 0 VSR(t) PI-7474-011215 1 0 -0.0 -0.3 -1.8 500 ns Time (ns) Figure 26. SYNCHRONOUS RECTIFIER DRIVE Pin Negative Voltage. 25 www.power.com Rev. I 09/21 InnoSwitch3-CE Typical Performance Curves (cont.) PI-8432-090717 Normalized Current Limit 1.4 1.2 1.0 0.8 0.6 Normalized di/dt = 1 0.4 0.2 0 1 2 Note: For the normalized current limit value, use the typical current limit specified for the appropriate BP/M capacitor. 3 4 Normalized di/dt Figure 27. Standard Current Limit vs. di/dt. 26 www.power.com Rev. I 09/21 www.power.com 0.057 0.049 Body Thickness 1.45 1.25 2 1 0.75 [0.030] C B 24 Coplanarity: 17 Leads C Seating Plane C A B 16X 3 A 4 2X C A 2 3 Detail A 0.30 0.18 0.41 [0.016] 8.25 [0.325] 0.75 [0.030] 0.032 0.020 1.58 [0.062] Standoff 0.010 0.004 6. Datums A & B to be determined at Datum H. 5. Controlling dimensions in millimeters [inches]. 4. Does not include inter-lead flash or protrusions. 3. Dimensions noted are inclusive of plating thickness. PI-8106-052620 POD-InSOP-24D Rev B 2.81 [0.111] 8.25 [0.325] 7.50 [0.295] 6.75 [0.266] 4.80 [0.189] 0.45 [0.018] Ref. PCB PAD LAYOUT 1.58 [0.062] C 0.25 0.10 12.72 [0.501] DETAIL A Seating Plane H 2. Dimensions noted are determined at the outermost extremes of the plastic body exculsive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. Maximum mold protrusion is 0.18 [0.007] per side. 17X 0.012 0.007 0.25 [0.010] 0° – 8° 0.81 0.51 Gauge Plane 0.20 [0.008] Ref. BOTTOM VIEW 0.10 [0.004] 9.40 [0.370] END VIEW 0.107 0.102 1.32 [0.052] Ref. C C 2.71 2.59 Notes: 1. Dimensioning and Tolerancing per ASME Y14.5M – 1994. SIDE VIEW 0.012 0.008 4 12 Lead Tips 0.15 [0.006] 13.43 [0.529] 0.15 [0.006] 5 Lead Tips 0.25 [0.010] M 3 0.30 0.20 12 13 0.10 [0.004] C TOP VIEW 0.50 [0.020] Ref. 1.60 [0.063] Max. Total Mounting Height Pin #1 I.D. 10.80 [0.425] 0.10 [0.004] 2X 3.35 [0.132] Ref. InSOP-24D InnoSwitch3-CE Rev. I 09/21 27 InnoSwitch3-CE PACKAGE MARKING InSOP-24D INN3162C M5J156N A A. B. C. D. E. 1740 1 Hxxx C D B E Power Integrations Registered Trademark Assembly Date Code (last two digits of year followed by 2-digit work week) Product Identification (Part #/Package Type) Lot Identification Code Test Sublot and Feature Code PI-8725-050418 28 www.power.com Rev. I 09/21 InnoSwitch3-CE Parameter Conditions Rating Units Current from pin (16-19) to pin 24 1.5 A TAMB = 25 °C (device mounted in socket resulting in TCASE = 120 °C) 1.35 W TAMB = 25 °C (device mounted in socket) 0.125 W Ratings for UL1577 Primary-Side Current Rating Primary-Side Power Rating Secondary-Side Power Rating 29 www.power.com Rev. I 09/21 InnoSwitch3-CE Parameter Symbol Conditions Rating Units Package Characteristics Clearance CLR 11.4 mm (min) Creepage CPG 11.4 mm (min) Distance Through Insulation DTI 0.4 mm Comparative Tracking Index CTI >600 V Isolation Resistance, Input to Output R IO Isolation Capacitance, Input to Output CIO VIO = 500 V, TJ = 25 °C (See Note 1) 1012 VIO = 500 V, 100 °C ≤ TJ ≤ 125 °C (See Note 1) 1011 (See Note 1) 1 pF W (min) Package Insulation Characteristics (See Note 2) Maximum RMS Working Isolation Voltage VIORM(RMS) 460 VRMS (max) Maximum Repetitive Peak Isolation Voltage VIORM(PK) 650 VPK (max) Maximum Transient Peak Isolation Voltage VIOTM Test Voltage = VIOTM, t = 60 s (qualification), t = 1 s (100% production) 8 kVPK (max) Maximum Surge Isolation Voltage VIOSM Surge Test 1.2/50 usec Table 2 IEC 60747-17 10.4 kVPK (max) Method A, After Environmental Tests Subgroup 1, VPD = 1.6 × VIORM, t = 10 s (qualification) Partial Discharge < 5 pC 1040 Method A, After Input / Output Safety Test Subgroup 2/3, VPD = 1.2 × VIORM, t = 10 s, (qualification) Partial Discharge < 5 pC 780 Method B1, 100% Production Test, VPD = 1.875 × VIORM, t = 1 s Partial Discharge < 5 pC 1220 RS VIO = 500 V at TJ = 150 ºC >109 W VISO Test Voltage = VISO, t = 60 s (qualification), Test Voltage = 1.2 x VISO, t = 1 s (100% production) 5000 VRMS (min) Input to Output Test Peak Voltage Insulation Resistance RMS Withstanding Isolation Voltage VPD Climatic Category Parameter VPEAK (min) 40/125/21 Conditions Specifications Material Group I Rated Mains RMS voltage ≤ 150 V I - IV Rated Mains RMS voltage ≤ 300 V I - IV Rated Mains RMS voltage ≤ 600V I - IV Rated Mains RMS voltage ≤ 1000 V I - III IEC 60664-1 Rating Table Basic Isolation Group Insulation Classification Note 1: All pins on each side of the barrier tied together creating a two-terminal device Note 2: VDE 0884-17 (IEC/EN 60747-17) Only applies to devices with following H-codes: -H117, -H118, -H119, -H120, -H121 30 www.power.com Rev. I 09/21 InnoSwitch3-CE Feature Code Table1,2 Feature Code CDC AR Threshold OTP Response AR and OVL Response Output Profile VOUT OVP Secondary Fault Response H101 0 mV 63% Hysteretic AR Fixed CC 120% AR H102 300 mV 63% Hysteretic AR Fixed CC 120% AR H103 250 mV 63% Hysteretic AR Fixed CC 120% AR H104 270 mV 63% Hysteretic AR Fixed CC 120% AR H105 240 mV 63% Hysteretic AR Fixed CC 120% AR H107 380 mV OL Latch Off Latch Off Fixed CC 120% Latch Off H109 0 mV 3.45 V Hysteretic AR Fixed CC 120% AR H110 380 mV OL Latch Off AR Fixed CC 120% Latch Off Common Feature Code H101 H102 INN3162C-H1XX Part   INN3163C-H1XX   INN3164C-H1XX   INN3165C-H1XX    H103 H104 H105    H107 H109 H110   INN3166C-H1XX  INN3167C-H1XX     INN3168C-H1XX         For the latest updates, please visit www.power.com InnoSwitch Family page to Build Your Own InnoSwitch. To download the feature code data sheet addendum, please visit www.power.com. 1 2 MSL Table Part Number MSL Rating INN3162C - INN3168C 3 ESD and Latch-Up Table Test Conditions Results Latch-up at 125 °C JESD78D > ±100 mA or > 1.5 × VMAX on all pins Human Body Model ESD ANSI/ESDA/JEDEC JS-001-2014 > ±2000 V on all pins Charge Device Model ESD ANSI/ESDA/JEDEC JS-002-2014 > ±500 V on all pins Part Ordering Information • InnoSwitch3 Product Family • CE Series Number • Package Identifier C InSOP-24D • Features Code • Tape & Reel and Other Options INN 3162 C - H101 - TL TL Tape & Reel, 2 k pcs per reel. 31 www.power.com Rev. I 09/21 Revision Notes Date A Preliminary. 02/17 B Code B and Code S combined release. 05/17 C Code A release. 09/17 D Updated Figure 10, added InSOP-24D package marking and made minor text edits. 06/18 D Updated Full Safety and Regulatory Compliance section on page 1 and added CTI to the parameter table. 08/18 E PCN-19281 - Updated Figure 17. Updated parameters: VBPP(H), IUV+, IUV-, IOV(H), IOV-, VV, tSS(RAMP), ISR(PU), ISR(PD), tR, tF ,RPU, VSR and IBP(SD). 11/19 F Updated safety information on page 1 and corrected typo in Package drawing on page 27. 06/20 G Updated tUV- parameter. 08/20 H Update Package Characteristics Table and VDE 0884-11 device list. 08/21 I Updated VDE-0884-17 device list. 09/21 For the latest updates, visit our website: www.power.com Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. Patent Information The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set forth at www.power.com/ip.htm. Life Support Policy POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein: 1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or death to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Power Integrations, the Power Integrations logo, CAPZero, ChiPhy, CHY, DPA-Switch, EcoSmart, E-Shield, eSIP, eSOP, HiperPLC, HiperPFS, HiperTFS, InnoSwitch, Innovation in Power Conversion, InSOP, LinkSwitch, LinkZero, LYTSwitch, SENZero, TinySwitch, TOPSwitch, PI, PI Expert, PowiGaN, SCALE, SCALE-1, SCALE-2, SCALE-3 and SCALE-iDriver, are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©2021, Power Integrations, Inc. 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