InnoSwitch3-Pro Family
Digitally Controllable Off-Line CV/CC QR Flyback Switcher IC
with Integrated High-Voltage Switch, Synchronous Rectification
and FluxLink Feedback
Product Highlights
VBUS
Digitally Controlled via I2C Interface
Dynamic adjustment of power supply voltage and current
Telemetry for power supply status and fault monitoring
Comprehensive set of configurable protection features
PowiGaN™ technology – up to 100 W without heatsinks (INN3378C,
INN3379C and INN3370C)
• Multi-mode Quasi-Resonant (QR) / DCM / CCM flyback controller,
high-voltage switch, secondary-side sensing and synchronous
rectifier driver
• Optimized efficiency across line and load range
• Integrated FluxLink™, HIPOT-isolated, feedback link
• Instantaneous transient response
• Drives low-cost N-channel FET series load switch
• Integrated 3.6 V supply for external MCU
InnoSwitch3-Pro
VB/D
VOUT
IS
GND
V
BPS
D
SR
Highly Integrated, Compact Footprint
RTN
FWD
•
•
•
•
CONTROL
uVCC
SDA
I2C
SCL
Primary Switch
and Controller
S
BPP
CC1
CC2
MCU
Secondary
Control IC
PI-8379-020119
Figure 1. Typical Application.
EcoSmart™ – Energy Efficient
• Less than 30 mW no-load including line sense and MCU
• Enables power supply designs that easily comply with all global
energy efficiency regulations
• Low heat dissipation
Advanced Protection / Safety Features
• Input voltage monitoring with accurate brown-in/brown-out and
overvoltage protection
• Output OV/UV fault detection with independently configured
responses
• Open SR FET gate detection
• Hysteretic thermal shutdown
• Programmable watchdog timer for system faults
Full Safety and Regulatory Compliance
•
•
•
•
Reinforced insulation
Isolation voltage >4000 VAC
100% production HIPOT compliance testing
UL1577 isolation voltage 4000 VAC (max) and TUV (EN62368) and
CQC (G4943.1) safety approved
Green Package
• Halogen free and RoHS compliant
Applications
•
•
•
•
•
High efficiency USB PD 3.0 + PPS/QC adapters
Multi protocol adapters including QuickCharge, AFC, FCP, SCP
Direct-charge mobile device chargers
Multi-chemistry tool and general purpose battery chargers
Adjustable CV and CC LED ballast
Description
The InnoSwitch™3-Pro series family of ICs dramatically simplifies the
development and manufacturing of fully programmable, highly efficient
power supplies, particularly those in compact enclosures. The universal
I2C interface enables dynamic control of output voltage and current
along with many configurable features. Telemetry provides reporting
of programmed features and fault modes.
www.power.com
Figure 2. High Creepage, Safety-Compliant InSOP-24D Package.
Output Power Table1
Product 4,5
230 VAC ± 15%
Adapter2
85-265 VAC
Open
Frame3
Adapter2
Open
Frame3
INN3365C/3375C
25 W
30 W
22 W
25 W
INN3366C/3376C
35 W
40 W
27 W
36 W
INN3377C
40 W
45 W
36 W
40 W
INN3367C
45 W
50 W
40 W
45 W
INN3368C
55 W
65 W
50 W
55 W
65 W
INN3378C
70 W
75 W
55 W
INN3379C
80 W
85 W
65 W
75 W
INN3370C
90 W
100 W
75 W
85 W
Table 1. Output Power Table.
Notes:
1. Maximum output power is dependent on the design, with maximum IC
package temperature kept tAR(SK).
The second is included to ensure that if communication is lost, the
primary tries to restart. Although this should never be the case in
normal operation, it can be useful when system ESD events (for
example) causes a loss of communication due to noise disturbing the
secondary controller. The issue is resolved when the primary restarts
after an auto-restart off-time.
The auto-restart is reset as soon as an AC reset occurs.
SOA Protection
In the event that there are two consecutive cycles where the drain
current is reached 110% of ILIM within ~500 ns (the blanking time +
current limit delay time) (including leading edge current spike), the
controller will skip 2.5 cycles or ~25 ms (based on full frequency of
100 kHz). This provides sufficient time for the transformer to reset
with large capacitive loads without extending the start-up time.
Input Line Voltage Monitoring
The UNDER/OVER INPUT VOLTAGE pin is used for input undervoltage
and overvoltage sensing and protection.
A sense resistor is tied between the high-voltage DC bulk capacitor
after the bridge (or to the AC side of the bridge rectifier for fast AC
reset) and the UNDER/OVER INPUT VOLTAGE pin to enable this
functionality. This function can be disabled by shorting the UNDER/
OVER INPUT VOLTAGE pin to primary GND.
At power-up, after the primary bypass capacitor is charged and the
ILIM state is latched, and prior to switching, the state of the UNDER/
OVER INPUT VOLTAGE pin is checked to confirm that it is above the
brown-in and below the overvoltage shutdown thresholds.
In normal operation, if the UNDER/OVER INPUT VOLTAGE pin current
falls below the brown-out threshold and remains below brown-out for
longer than tUV-, the controller enters auto-restart. Switching will only
resume once the UNDER/OVER INPUT VOLTAGE pin current is above
the brown-in threshold.
In the event that the UNDER/OVER INPUT VOLTAGE pin current is
above the overvoltage threshold, the controller will also enter
auto-restart. Again, switching will only resume once the UNDER/
OVER INPUT VOLTAGE pin current has returned to within its normal
operating range.
The input line UV/OV function makes use of a internal high-voltage
(V V) switch on the UNDER/OVER INPUT VOLTAGE pin to reduce
power consumption. The controller samples the input line at light
load conditions when the time between switching cycles is 50 msec
or more. At 1.1*Vout
bit[9] {Reg_OTP}
0x14
bit[5] {Reg_VOUTWK}
R_Word
bit[4] {Reg_VOUT10PCT}
IS-pin Short Circuit Detected
bit[3] {Reg_ISSC}
Output Short-Circuit Detected
bit[2] {Reg_CCSC}
Output Voltage UV Fault
Comparator
bit[1] {Reg_VOUT_UV}
Output Voltage OV Fault
Comparator
bit[0] {Reg_VOUT_OV}
CVO Mode AR
bit[15] {Reg_ar _CV}
IS-pin Short-Circuit AR
bit[12] {Reg_ar_ISSC}
Output Short-Circuit AR
bit[11] {Reg_ar_CCSC}
Output Voltage OV AR
bit[10] {Reg_ar_VOUT_OV}
Output Voltage UV AR
bit[9] {Reg_ar_VOUT_UV}
Latch-Off (LO) Occurred
CVO Mode LO
0x16
bit[7] {Reg_LO}
R_Word
bit[6] {Reg_Lo_CVO}
PSU Turn-Off CMD Received
bit[5] {Reg_PSUOFF}
IS-pin Short-Circuit LO
bit[4] {Reg_Lo_ISSC}
Output Voltage OV LO
bit[2] {Reg_Lo_VOUT_OV}
Output Voltage UV LO
bit[1] {Reg_Lo_VOUT_UV}
BPS-pin LO
bit[0] {Reg_BPS_OV}
Mask
READ12
Interrupts
0x18
R_Word
READ13
Average Output Current
0x1A
R_Word
READ14
Average Output Voltage
0x1C
R_Word
READ15
Voltage DAC
0x5C
R_Word
Table 3.
Status
bit[14]
bit[6] {Reg_CONTROL_S}
bit[13]
bit[5] {Reg_LO_Fault}
bit[12]
bit[4] {Reg_CCAR}
bit[11]
bit[3] {Reg_ISSC}
bit[10]
bit[2] {Reg_CCSC}
bit[9]
bit[1] {Reg_VOUT_UV}
bit[8]
bit[0] {Reg_VOUT_OV}
bit[15:8] 8b'0
bit[7:0] 16 sample average of READ 7
bit[15:12] 4b'0
bit[11:0] 16 sample average of READ 9
bit[15:8] DAC_100mV
bit[7:0] DAC_10mV
Telemetry (Read-Back) Register Assignments (cont.)
13
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
Command Registers
Constant current regulation is based on the average current measurement register (READ13).
System Ready Status Register
The system ready bit {Reg_control_s} must be read prior to the start
of any I2C transactions and after the InnoSwitch3-Pro has entered
into a reset state resulting from auto-restart (AR), latch-off (LO) or
initial power-up.
When the {Reg_control_s} bit is set to “1”, it means InnoSwitch3-Pro
is ready to receive I2C commands.
Example: For a power supply with maximum CC of 5 A (Rs = 6.4mW),
the following demonstrates changing the CC set point from 5 A to 2.5 A.
This corresponds to change in CC from 100% (0x80) to 50% (0x40) –
with odd parity this becomes 0x8040:
High FSW
VOUT 2%
VOUT 10%
ISSC
CCSC
UV
OV
REG
REG
REG
REG
0
0
REG
0
0
0
REG
REG
REG
REG
REG
REG
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
MSB
Secondary
OTP
VDIS
0x30 (8’b0011 0000)
CC Register (0x98)
0x40 (8’b0100 0000)
0x80 (8’b1000 0000)
Control_S
PI_SLAVE_ADDRESS [W]:
PI_Command:
Low Byte:
High Byte:
Interupt_EN
To read the {Reg_control_s} bit, write the READ10 sub address 0x14
into the 0x80 address. Then read High Byte data back from address
0x80. The bit 14 is {Reg_control_s}.
For a 5 A CC threshold, the current sense resistor is 6.4 mW.
The current limit step size for this example is 39.1 mA/step.
Null
Reserved
LSB
0
PI-8447-101118
Figure 12. {Reg_Control_s} Telemetry Register (READ 10).
PI_SLAVE_ADDRESS [W]:
Read Register:
PI_Command:
PI_SLAVE_ADDRESS [r]:
0x30 (8’b0011 0000)
0x80
READ10 (0x14), READ10 (0x14)
0x31 (8’b0011 0001)
Programming Output Voltage (CV), Output Constant Current
(CC), Constant Power Mode (CP), Cable Drop Compensation
(CDC) and Constant Voltage Only Mode (CVO)
CV Register (0x10)
The output voltage of the power supply is regulated on the Vout-pin.
The valid programming range is from 3 V to 24 V with 10 mV / lsb.
The default CV register value is 5 V. Below 5 V and at light load
below 50 mA, output monotonicity may not be visible with 10 mV / steps.
on
gi
12 V
8V
20 W
CC Region
0x30 (8’b0011 0000)
CV Register (0x10)
0x20 (8’b0010 0000)
0x86 (8’b1000 0110)
30 W
Re
PI_SLAVE_ADDRESS [W]:
PI_Command:
Low Byte:
High Byte:
CV Region
CP
Example: to change CV from 5 V to 8 V
Convert 8 V to lsb representation: 8/(10mV/lsb) = 800
Convert to hex format (800 = 0x0320)
With odd parity bits added the hex data is 0x8620)
The bit I2C command for this is shown below:
Constant Output Power Voltage Threshold VKP (0x1A)
A constant output power characteristic is programmed via the “knee
power voltage” in conjunction with the 100% constant current
regulation threshold (full-scale current setting). If the full-scale CC is
2.5 A and the knee power voltage is set to 8 V, the constant power is
20 W. If the VKP register were set to 12 V, the resultant constant
power characteristic above the VKP threshold would be 30 W.
Output Voltage (VDC)
Example: Reading the {Reg_control_s} bit:
This sequence of commands is shown in Figure 10 and Figure 23.
CC Register (0x98)
The constant current regulation register address is 0x18 and with odd
parity it is 0x98. The constant current regulation threshold is
adjustable from 20% (d’25) CC up to 100% (d’128) of the full scale.
The full-scale constant-current threshold is set with the sense resistor
between the IS and GND pins. The typical value for the full-scale
current voltage drop is 32 mV (ISV(TH)). The resolution step size is
(0.78%/step):
Output Current (A)
2.5 A
PI-8448-092517
Figure 13. Constant Output Power Profile.
32 mV/128 = 0.25 mV/step/Rs
14
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
From no-load to heavy loading conditions, InnoSwitch3-Pro will
operate in CV then transition into CP then into CC region below the
VKP threshold. Setting VKP to maximum value (24 V) results in no
Constant Output Power regulation region.
Example: To change VKP from 24 V (d’240) (0xF0 = 0x0170 with odd
parity) to 8 V (0x50 = 0x80D0):
PI_SLAVE_ADDRESS [W]:
PI_Command:
Low Byte:
High Byte:
0x30 (8’b0011 0000)
VKP Register (0x1A)
0xD0 (8’b1101 0000)
0x80 (8’b1000 0000)
Reducing the constant current regulation threshold does not modify
the maximum programmed output power with a given VKP setting.
From the example shown above, setting CC regulation to 2 A
(full-scale CC is still 2.5 A), with VKP = 8 V, would result in output
profile shown below with CP characteristic intercept of 10 V for the
same 20 W constant power characteristic.
Cable Drop Compensation (CDC) (0x16)
The amount of cable drop compensation has a controllable range of
0 V to 600 mV in 50 mV/steps. CDC is applied as a function of the
current through the sense resistor (resistor between IS and GND
pins) used to program the constant current regulation threshold. At
no-load there is no CDC and the compensation is increased linearly
as load increases and reaches the maximum programmed value at
the onset of the 100% constant-current regulation threshold
(full-scale voltage across the current sense resistor).
The table below shows the register values to program the desired
CDC:
CDC (mV)
Hex Value
Binary
0
0x00
4’b0000
100
0x02
4’b0010
150
0x03
4’b0011
200
0x04
4’b0100
250
0x05
4’b0101
300
0x06
4’b0110
350
0x07
4’b0111
400
0x08
4’b1000
450
0x09
4’b1001
10 V
500
0x0A
4’b1010
550
0x0B
4’b1011
8V
600
0x0C
4’b1100
20 W
Table 4.
Cable Drop Compensation.
If the current sense resistor between IS pin to GND pin is shorted,
there will be neither any cable drop compensation nor any constant
current regulation.
2A
2.5 A
Output Current (A)
Example: To change CDC from 0 V to 300 mV (0x06):
PI-8449-100417
Figure 14. Constant Output Power Profile with Reduced CC Regulation
Threshold.
Output Voltage (VDC)
CDC = 600 mV (0xC)
No-Load
CDC = 300 mV (0x6)
CDC = 100 mV (0x2)
CDC = 50 mV (0x1)
No CDC = 0 V
PI_SLAVE_ADDRESS [W]:
PI_Command:
Byte:
0x30 (8’b1011 0000)
CDC Register (0x16)
0x06 (4’b0110)
Constant Voltage Only Mode (0x0E)
The InnoSwitch3-Pro can be programmed to operate with constantvoltage only and have no constant current regulation mode. The set
output current register (0x98) sets the over-load threshold instead of
regulating the constant current when the CVO mode is enabled.
Once the load current exceeds the programmed current a peak load
timer (tPLT) is started. The options for the peak load timer (CVOL
Timer Register 0x2A) are 8/16/32 and 64 ms. If the peak load
exceeds the programmable timer, the InnoSwitch3-Pro can be
programmed to respond to this fault as auto-restart, latch-off or
no-response through the CVOL Register 0xA8. The default response
for CVOL (CVO response) is no-response with 8 ms timer.
Output Current (A) 100 % Threshold
PI-8450-092517
Figure 15. CDC as Function of Load Current.
15
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
Example: Enable CVO Mode, set tPLT to 16 msec and fault response to
latch-off (LO):
Output Voltage
Peak Load Timer Starts
After Load Exceeds CC
Threshold
Load Current
PI_SLAVE_ADDRESS [W]:
PI_Command:
Byte:
0x30 (8’b0011 0000)
CVO Register (0x0E)
0x01 (1’b1)
PI_SLAVE_ADDRESS [W]:
PI_Command:
Byte:
0x30 (8’b0011 0000)
CVOL Timer Register (0x2A)
0x01 (2’b01)
PI_SLAVE_ADDRESS [W]:
PI_Command:
Byte:
0x30 (8’b0011 0000)
CVOL Register (0xA8)
0x02 (2’b10)
The output undervoltage protection mode discussed in Output
Overvoltage and Undervoltage Protection Thresholds/Fault Behavior
section is still active in the CVO mode of operation even if the
individual UV fault response is set to ‘No response’. The following
control flow-chart shows the expected behavior of the device under
the different potential programming scenarios.
0x98 Register
Command
PI-8451-052118
Figure 16. Constant Voltage Only (CVO) Mode.
Output UV Fault
CVO Fault
No
CVO Set To
No Response?
Yes
Yes
UVL Set To
No Response?
No
UV Timer
CVO Timer
No Response
CVO
AR?
Yes
Yes
No
UV
AR?
No
Auto-Restart
(AR)
Latch-Off
(LO)
AR or LO Depending
on Which Fault Occurs
and Timer Expires First
PI-8452-052318
Figure 17. CVO and Output UV Control.
16
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
Programmable Protection Mechanisms
Output Overvoltage and Undervoltage Protection
Thresholds/Fault Behavior
Besides the ability of programing the OV/UV thresholds on the fly as a
function of the set CV, the behavior of the power supply once a fault
occurs (a. No-Fault which just sets the fault register, b. Auto-restart
(AR) or c. Latch-off (LO) the power supply) and timing for the UV fault
detection (8 to 64 msec) is programmable as well. The output
overvoltage delay is fixed at ~80 ms. All faults that are programmed
to have no-fault respose will be logged into the telemetry read-back
fault register. Since the minimum UV setting is 3 V, the response
should be set to no-response for 3 V operation.
response for CCSC should be set to No-Response for proper start-up
and may be programmed back to Auto-restart during normal
operation after the series bus-switch is closed.
CCSC (0xA0): write to this address to specify the behavior for an
output short-circuit.
Example: Set behavior of output short-circuit to No-response.
PI_SLAVE_ADDRESS [W]:
PI_Command:
Byte:
0x30 (8’b0011 0000)
CCSC Register (0x20)
0x00 (2’b00)
Note: Setting CCSC register to No-response and creating a shortcircuit condition at output will result in Auto-restart.
OVA(0x92) : write to this address to specify the overvoltage
threshold
UVA(0x94) : write to this address to specify the undervoltage
threshold
OVL(0x1C) : write to this address to specify the behavior to OV fault
UVL(0x9E) : write to this address to specify the behavior to UV fault
UVL Timer(0xA4) : write to this register specify the UV timer
Watchdog Timer (0x26)
The Watchdog timer supervises the communication on the I2C
command lines and has an adjustable time-out. InnoSwitch3-Pro will
go into a reset state if I2C commands are not received within the
programmable time interval. The watchdog timer does not engage
until the master issues the first I2C command (Read or Write). In the
reset state the following occurs:
Example: To change the absolute output undervoltage threshold 3 V
(d’30) (0x809E with odd parity) fault response to latch-off (LO) (0x01)
and configure fault timer to 64 msec (0x03):
1. VBUS switch is Disabled (Series switch is open).
2. VOUT pin voltage regulates at the default 5 V threshold.
3. All command registers are cleared.
PI_SLAVE_ADDRESS [W]:
PI_Command:
Low Byte:
High Byte:
0x30 (8’b0011 0000)
UVA Register (0x94)
0x9E (8’b1001 1110)
0x80 (8’b1000 0000)
By writing 0x00 into register 0x26, the Watchdog timer is disabled.
Disabling this feature can be useful in initial software debugging or
checking functionality of the device on the bench.
PI_SLAVE_ADDRESS [W]:
PI_Command:
Byte:
0x30 (8’b0011 0000)
UVL Register (0x9E)
0x01 (2’b01)
PI_SLAVE_ADDRESS [W]:
PI_Command:
Byte:
0x30 (8’b0011 0000)
UVL Timer Register (0xA4)
0x03 (2’b11)
IS Pin and Output Short-Circuit Fault Protection
The InnoSwitch3-Pro can be configured to monitor whether a
short-circuit fault occurs across the output current sense resistor or a
short-circuit fault across the IS to GND pins.
A fault is annunciated in the event the IS pin voltage does not exceed
approximately 50% of the full constant-current threshold (ISV(TH)) with
a switching frequency exceeding a programmed threshold. The
switching frequency can be selected in a range from 30 to 60 kHz.
This must be carefully selected to suit the expected operating
conditions of the design.
An IS pin short (ISSC) can be programmed to have a response to be
a. No-fault, b. Auto-restart (AR) or c. Latch-off (LO). In the event the
behavior is a No-fault, the Telemetry Read-Back Fault Register is
logged.
ISSC(0xA2) : write to this address to specify the behavior for an
IS-GND short.
Example: To set the behavior of an IS pin short to AR for switching
frequency exceeding 40 kHz. (4’b10 10 = 0x10):
PI_SLAVE_ADDRESS [W]:
PI_Command:
Byte:
0x30 (8’b0011 0000)
ISSC register (0xA2)
0x10 (4’b1010)
The InnoSwitch3-Pro sets the CCSC fault register (READ 10 bit 2)
once the voltage across the IS pin resistor exceeds more than ~3
times the IS(VTH). The CCSC register can be programmed to have
response of a (a.) No Fault or (b.) Auto-Restart. The default response
for this command register is Auto-restart. In applications where the
output capacitance after the series bus-switch exceeds 100 mF, the
Example: To disable the Watchdog timer:
PI_SLAVE_ADDRESS [W]:
PI_Command:
Byte:
0x30 (8’b0011 0000)
Watchdog Timer Register (0x26)
0x00 (2’b00)
Opening and Closing the Series VBUS Switch (0x04)
Enabling VBEN (closing the VBUS Series switch) speeds up the ADC
sampling frequency in order to achieve high control accuracy. Write
commands to CVC register (0x10) and CC register (0x98) cannot be
accepted faster than 80 msec when the VBEN is disabled (Series
VBUS switch open).
Write 0x03 (with odd parity this becomes 0x8083) into the VBEN
register (0x04) to close the series VBUS switch and write 0x00 to this
register to open the switch. When the VBUS switch is open (VBEN
disabled), the system is reset to the default output voltage set point
of 5 V. Disabling the series VBUS switch also resets all the programmable
command registers to their default values. The InnoSwitch3-Pro
controller is in a state of reset when VBEN is disabled or the VDIS
register is enabled. For both these commands, since the controller is
in reset, an ACK or Nack at the end of the command should not be
expected.
Enabling the VBEN register automatically disables the VDIS register
(0x08) described in Active VOUT Pin Bleeder and Output Load
Discharge Functions section.
Example: Enabling (Closing) the Series VBUS switch (0x8083):
PI_SLAVE_ADDRESS [W]:
PI_Command:
Byte:
0x30 (8’b0011 0000)
VBEN Register (0x04)
0x83 (8’b1000 0011)
Prior to sending command to open the series bus switch, a command
to set the output voltage (CV registor 0x10) to 5 V is recommended.
In the event of an auto-restart or latch-off, the bus switch is not
disabled.
The VBEN command must be sent to enable the series bus switch
(close the switch) prior to increasing the output voltage above 16 V.
17
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
Turn-Off the Power Supply (0x8A)
The I2C master has the ability to turn-off the power supply (through
an I2C command), which will require AC power cycling to restart the
power supply.
Example: Activate the Vout Bleeder:
PI_SLAVE_ADDRESS [W]: 0x30 (8’b0011 0000)
PI_Command:
BLEEDER Register (0x86)
Byte:
0x01 (1’b1)
Example: Turn-off the power supply:
Example: Discharge the VBUS
PI_SLAVE_ADDRESS [W]:
PI_Command:
Byte:
PI_SLAVE_ADDRESS [W]:
PI_Command:
Byte:
0x30 (8’b0011 0000)
Turn-Off PSU Register (0x8A)
0x01 (1’b1)
Fast VI Command
By default, the maximum speed in which CV (0x10) and CC (0x98)
commands can be sent to program output voltage/current
respectively is 10 msec. However, the speed limit can be removed by
setting 0x1 to the Fast VI Command Register (0x8C).
Example: To disable speed limit for V/I commands:
PI_SLAVE_ADDRESS [W]:
PI_Command:
Byte:
Secondary Over-Temperature Protection (0xAE)
As the secondary controller die temperature increases beyond ~125 °C,
the active VOUT pin bleeder function described above will be turned
off. The bleeder will not be permitted to be re-enabled until the
controller temperature falls below the programmable hysteresis value.
Example: Set Secondary OTP Hysteresis to 60 °C:
PI_SLAVE_ADDRESS [W]:
PI_Command:
Byte:
0x30 (8’b0011 0000)
Fast VI Speed Register (0x8C)
0x01 (1’b1)
0x30 (8’b0011 0000)
OTP Register (0xAE)
0x01 (1’b1)
Transient Response
If faster transient response is required in the application the
InnoSwitch3-Pro includes command registers to reduce the time for
low to high output voltage transitions. The command register
addresses and recommended settings are shown in the table below:
Active VOUT Pin Bleeder and Output Load Discharge
Functions
There may be circumstances where the VOUT pin strong bleeder
function must be activated to discharge the output voltage from a
high to low regulation set point.
The VOUT bleeder can be activated by writing 0x01 into BLEEDER
Register (0x86).
The BLEEDER register must not be enabled for extended period of
time to prevent excessive power dissipation in the controller. When
the BLEEDER function is being used to bleed the output voltage from
high to low set point, the status of the VOUT10PCT register (bit 4 in the
READ10 0x14 read register) should be used to disable the function.
The VOUT10PCT register is set once the output voltage is above 10%
of the target regulation voltage. The weak Bleeder Enabled Register,
READ10 (0X14) bit 5 can be used instead of the VOUT10PCT to
determine when the BLEEDER register should be disabled for no-load
transients from high to low output voltage transitions.
The InnoSwitch3-Pro automatically activates a weak current bleeder
(84% and increases to efficiency >89% for
the largest device.
3. Transformer primary inductance tolerance of ±10%.
4. Reflected output voltage (VOR) is set to maintain KP = 0.8 at
minimum input voltage conditions for universal line and KP = 1 for
high input line conditions.
5. Maximum conduction losses for adapter ratings is limited to 0.6 W
and 0.8 W for open frame.
6. Increased current limit is selected for peak and open frame power
columns and standard current limit for adapter columns.
7. The part is board mounted with SOURCE pins soldered to a
sufficient area of copper and/or a heat sink is used to keep the
SOURCE pin temperature at or below 110 °C.
8. Ambient temperature of 50 °C for open frame designs and 40 °C
for sealed adapters.
*Below a value of 1, KP is the ratio of ripple to peak primary current.
To prevent reduced power delivery, due to premature termination of
switching cycles, a transient KP limit of ≥0.25 is recommended. This
prevents the initial current limit (IINT) from being exceeded at switch
turn-on.
28
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
Primary-Side Overvoltage Protection
The primary-side output overvoltage protection provided by the
InnoSwitch3-Pro IC triggered by a threshold current of ISD into the
PRIMARY BYPASS pin. In addition to an internal filter, the PRIMARY
BYPASS pin capacitor forms an external filter providing noise
immunity from inadvertent triggering. For the bypass capacitor to be
effective as a high frequency filter, the capacitor should be located as
close as possible to the SOURCE and PRIMARY BYPASS pins of the
device.
The primary sensed OVP function can be realized by connecting a
series combination of a Zener diode, a resistor and a blocking diode
from the rectified and filtered bias winding voltage supply to the
PRIMARY BYPASS pin. The rectified and filtered bias winding output
voltage may be higher than expected (up to 1.5x or 2x the desired
value) due to poor coupling of the bias winding with the output
winding and the resulting ringing on the bias winding voltage waveform.
It is therefore recommended that the rectified bias winding voltage
be measured. This measurement should be ideally done at the lowest
input voltage and with highest load on the output. This measured
voltage should be used to select the components required to achieve
primary sensed OVP. It is recommended that a Zener diode with a
clamping voltage approximately 6 V lower than the bias winding
rectified voltage at which OVP is expected to be triggered be
selected. A forward voltage drop of 1 V can be assumed for the
blocking diode. A small signal standard recovery diode is recommended. The blocking diode prevents any reverse current charging
the bias capacitor during start-up. Finally, the value of the series
resistor required can be calculated such that a current higher than ISD
will flow into the PRIMARY BYPASS pin during any output overvoltage.
Reducing No-Load Consumption
The InnoSwitch3-Pro IC can start in self-powered mode from the
PRIMARY BYPASS pin capacitor charged through the internal current
source. Use of a bias winding is however required to provide supply
current to the PRIMARY BYPASS pin once the InnoSwitch3-Pro IC has
become operational. Auxiliary or bias winding provided on the
transformer is required for this purpose. The addition of a bias
winding that provides bias supply to the PRIMARY BYPASS pin
enables design of power supplies with no-load power consumption
down to 5 V).
A glass passivated standard recovery rectifier diode with low junction
capacitance is recommended to prevent the snappy recovery typically
seen with fast or ultrafast diodes that can lead to higher radiated EMI.
29
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
An aluminum capacitor of at least 22 mF with a voltage rating 1.2
times greater than the highest voltage developed across the capacitor
is recommended. Highest voltage is typically developed across this
capacitor when the supply is operated at the highest rated output
voltage and rated load with the lowest input AC supply voltage. It is
recommended to ground the bias winding capacitor to the negative of
the input bulk capacitor than the SOURCE pin.
+
R1
VB/D
VOUT
IS
GND
BPS
V
SR
D
Line UV and OV Protection
Resistors connected from the UNDER/OVER INPUT VOLTAGE pin to
the DC bus enable sensing of input voltage to provide line undervoltage and overvoltage protection. For a typical universal input
application, a resistor value of approximately 3.8 MW is recommended.
Figure 29 shows circuit configurations that enable selectively either
the line UV or the line OV feature, disabling the other.
FWD
R2
CONTROL
S
uVCC
SDA
I2C
SCL
BPP
CC1
CC2
MCU
InnoSwitch3-Pro
PI-8546-111617
(a)
The InnoSwitch3-Pro IC features a primary sensed OV protection
feature that can be used to latch-off/AR the power supply. Once the
power supply is in latch-off/AR, it can be reset if the UNDER/OVER
INPUT VOLTAGE pin current is reduced to zero. Once the power
supply is latched off, even after input supply is turned off, it can take
considerable amount of time to reset InnoSwitch3-Pro IC controller as
the energy stored in the DC bus will continue to provide bias supply
to the controller. In case of latch-off, a fast AC reset can be achieved
using the modified circuit configuration shown in Figure 30. The
voltage across capacitor CS reduces rapidly after input supply is
disconnected reducing current into the INPUT VOLTAGE MONITOR pin
of the InnoSwitch3-Pro IC and resetting the InnoSwitch3-Pro IC
controller.
+
R1
1N4148
VB/D
VOUT
IS
GND
BPS
V
SR
D
FWD
R2
CONTROL
S
uVCC
SDA
I2C
SCL
BPP
InnoSwitch3-Pro
CC1
CC2
MCU
PI-8547-111617
(b)
Figure 29. (a) Line UV Only; (b) Line OV Only.
InnoSwitch3-Pro
Primary FET
and Controller
CONTROL
S
BPP
VB/D
VOUT
IS
GND
BPS
V
SR
D
CS
100 nF
FWD
SR FET
uVCC
SDA
I2C
SCL
Secondary
Control IC
CC1
CC2
MCU
PI-8548-112019
Figure 30. Fast AC Reset Configuration.
30
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
Primary Sensed OVP (Overvoltage Protection)
The voltage developed across the output of the bias winding tracks
the power supply output voltage. Though not precise, a reasonably
accurate detection of the amplitude of the output voltage can be
achieved by the primary-side controller using the bias winding
voltage. A Zener diode connected from the bias winding output to
the PRIMARY BYPASS pin can reliably detect a secondary overvoltage
fault and causes the primary-side controller to latch-off/AR. It is
recommended that the highest voltage at the output of the bias
winding should be measured for normal steady-state conditions
(at full rated load and lowest rated input voltage) and also under
transient load conditions. A Zener diode rated for 1.25 times this
measured voltage will typically ensure that OVP protection will not
trigger under any normal operating conditions but will only operate in
case of a fault condition.
could lead to output voltage overshoot during start-up. The values
lower than 1.5 mF may not offer enough capacitance, which can cause
unpredictable operation. The capacitor must be located adjacent to
the IC pins. At least 10 V is recommended voltage rating to give
enough margin from BPS voltage, and 0805 size is necessary to
guarantee the actual value in operation since the capacitance of
ceramic capacitors drops significantly with applied DC voltage
especially with small package SMD such as 0603. 6.3 V / 0603 / X5U
or Z5U type of MLCC is not recommended for this reason. The
ceramic capacitor type designations, such as X7R, X5R from different
manufacturers or different product families do not have the same
voltage coefficients. It is recommended that capacitor data sheets
be reviewed to ensure that the selected capacitor will not have more
than 20% drop in capacitance at 4.4 V. Capacitors with X5R or X7R
dielectrics should be used for best results.
Primary-Side Snubber Clamp
A snubber circuit should be used on the primary-side as shown in the
example circuit in Figure 26. This prevents excess voltage spikes at
the Drain of the switch at the instant of turn-off of the switch during
each switching cycle. Though conventional RCD clamps can be used,
RCDZ clamps offer the highest efficiency. The circuit example shown
in Figure 26 uses RCD clamp with a resistor in series with the clamp
diode. This resistor dampens the ringing at the drain and also limits
the reverse current through the clamp diode during reverse recovery.
Standard recover glass passivated diodes with low junction capacitance are recommended as these enable partial energy recovery from
the clamp thereby improving efficiency.
When the output voltage of the power supply is 5 V or higher, the
supply current for the secondary-side controller is supplied by the
OUTPUT VOLTAGE (VOUT) pin of the IC as the voltage at this pin is
higher than the SECONDARY BYPASS pin voltage. During start-up
and operating conditions where the output voltage of the power
supply is below 5 V, the secondary-side controller is supplied current
from an internal current source connected to the FORWARD pin. If
the output voltage of the power supply is below 5 V and the load at
the output of the power supply is very light, the operating frequency
can drop considerably and the current supplied to the secondary-side
controller from the FORWARD pin may not be sufficient to maintain
the SECONDARY BYPASS pin voltage at 4.4 V. For such applications,
InnoSwitch3-Pro IC has an internal charge pump to regulate the
voltage of the SECONDARY BYPASS pin at 4.4 V.
Components for InnoSwitch3-PRO
Secondary-Side Circuit
SECONDARY BYPASS Pin – Decoupling Capacitor
A 2.2 mF, 10 V / X7R or X5R / 0805 or larger size multi-layer ceramic
capacitor should be used for decoupling the SECONDARY BYPASS pin
of the InnoSwitch3-Pro IC. Since the SECONDARY BYPASS pin
voltage needs to be 4.4 V before the output voltage reaches to the
regulation voltage level, a significantly higher BPS capacitor value
FORWARD Pin Resistor
A 47 W 5% resistor is recommended to ensure sufficient IC supply
current. A lower resistor value should not be used as it can affect
device operation such as the synchronous rectifier drive timing. In
some cases a higher value should be used if pulse grouping is
observed. However this number should not exceed 150 W.
31
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
0V
VSRTH
0V
VSRTH
VD
VD
PI-8392-082317
Figure 31. Unacceptable FORWARD Pin Waveform After Handshake With
SR FET Conduction During Flyback Cycle.
PI-8395-121117
Figure 34. Acceptable FORWARD Pin Waveform Before Handshake With Body
Diode Conduction During Flyback Cycle.
SR FET Operation and Selection
Although a simple diode rectifier and filter works for the output, use
of a SR FET enables significant improvement in operating efficiency
often necessary to meet the European CoC and the U.S. DoE energy
efficiency requirements. The secondary-side controller turns on the
SR FET once the flyback cycle begins. The SR FET gate should be
tied directly to the SYNCHRONOUS RECTIFIER DRIVE pin of the
InnoSwitch3-Pro IC (with no additional resistors connected to the
gate circuit of the SR FET if a single SR FET is used). The SR FET is
turned off once the Drain voltage of the SR FET drops below 0 V.
0V
VSRTH
VD
PI-8393-080917
Figure 32. Acceptable FORWARD Pin Waveform After Handshake With
SR FET Conduction During Flyback Cycle.
A FET with 18 mW RDS(ON) is good for 5 V, 2 A output, and a FET with
8 mW RDS(ON) is suitable for designs rated for 12 V, 3 A output. The SR
FET driver uses the SECONDARY BYPASS pin for its supply rail, and
this voltage is typically 4.4 V. A FET with too high a threshold voltage
is therefore not suitable, and FETs with a low threshold voltage of
1.5 V to 2.5 V are ideal although FETs with a threshold voltage
(absolute maximum) as high as 4 V may be used provided their data
sheets clearly specify RDS(ON) over-temperature range for a gate
voltage of 4.5 V.
There is a slight delay between the commencement of the flyback
cycle and the turn-on of the SR FET. During this time, the body diode
of the SR FET conducts. If an external parallel Schottky diode is
used, this current mostly flows through the Schottky diode. Once the
InnoSwitch3-Pro IC detects end of the flyback cycle, voltage across
SR FET RDS(ON) drops below VSR(TH), any remaining portion of the
flyback cycle is completed with the current commutating to the body
diode of the SR FET or the external parallel Schottky diode. A
Schottky diode parallel to the SR FET may be added to provide higher
efficiency and typically a 1 A surface mount Schottky diode is often
adequate. However, the gains are modest; for a 5 V, 2 A design the
external diode adds ~0.1% to full load efficiency at 85 VAC and
~0.2% at 230 VAC.
0V
VSRTH
VD
t1
t2
PI-8394-080917
Figure 33. Unacceptable FORWARD Pin Waveform Before Handshake With Body
Diode Conduction During Flyback Cycle.
The voltage rating of the Schottky diode and the SR FET should be at
least 1.3 to 1.4 times the expected peak inverse voltage (PIV) based
on the turns ratio used for the transformer. 60 V rated FETs and
diodes are suitable for most 5 V designs that use a VOR < 60 V, and
100 V rated FETs and diodes are suitable for 12 V design.
Note:
If t1 + t2 = 1.5 ms ± 50 ns, the controller may fail the handshake and
trigger a primary bias winding OVP latch-off/AR.
32
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
The interaction between the leakage reactance of the secondary and
the SR FET capacitance (COSS) leads to ringing on the voltage
waveforms at the instance of voltage reversal at the winding due to
the primary switch turn-on. This ringing can be suppressed using a
RC snubber connected across the SR FET. A snubber resistor in the
range of 10 W to 47 W may be used (a higher resistance value leads
to noticeable drop in efficiency). A capacitance of 1 nF to 2.2 nF is
adequate for most designs.
Output Decoupling Capacitor
A ceramic output decoupling capacitor up to 10 mF is required to pass
18 kV ESD air discharge.
In designs where the SR FET drain waveform is not as shown in
Figure 31 during voltage transitions, and looks similar to Figure 30 it
is recommended that voltage transitions be made in small increments
of 200 mV.
Bus Discharge
The resistor value for bus discharge is chosen as per the discharge
time requirements for high-voltage to low-voltage transitions. A
100 W resistor value is recommended to meet the USB PD discharge
time specification. A general purpose diode in series is recommended
for unidirectional current flow.
Output Capacitor
Low ESR aluminum electrolytic capacitors are suitable for use with
most high frequency flyback switching power supplies though the use
of aluminum-polymer solid capacitors have gained considerable
popularity due to their compact size, stable temperature characteristics, extremely low ESR and high RMS ripple current rating. These
capacitors enable design of ultra-compact chargers and adapters.
Typically, 200 mF to 300 mF of aluminum-polymer capacitance per
ampere of output current is adequate. The other factor that
influences choice of the capacitance is the output ripple. Care should
be taken to ensure that capacitors have a voltage rating higher than
the highest output voltage with sufficient margin (>20%).
Output Overload Protection
The maximum power which can be delivered by the power supply is
obtained by the product of the programmed VKP and the full scale
current limit. For output voltage below the programmed VKP
threshold, the InnoSwitch3-Pro IC will limit the output current once
the programmed current limit is reached (if it is less than the full
scale current limit) or voltage across the IS and GND pins exceeds the
ISV(TH) threshold and provides current limited or constant current
operation. The full scale current limit is set by the resistor between
the IS and GND pins. A lower value of current limit can be programmed
over I2C. For any output voltage above the programmed VKP threshold,
InnoSwitch3-Pro IC will provide a constant power characteristic. An
increase in load current within the programmed current limit will
result in a drop in output voltage such that the product of output
voltage and current equals the maximum power set by the product of
VKP and set current limit.
Decoupling Capacitor at μVCC Pin
It is recommended that at least a 2.2 mF ceramic capacitor be placed
between the uVCC and GND pins.
Pull-Up Resistors for SDA and SCL Pins
A 4.7 kW pull-up resistor from each of the SDA and SCL pin to the
uVCC pin is recommended for communication at a frequency of
400 kHz. Maximum value of the pull-up resistor is dependent on the
capacitance presented by the SDA/SCL lines and the I2C master. The
resultant voltage rise to the VIL threshold assuming a total capacitance
of 20 pF is tabulated as a function of SCL clock frequency in Table 7.
Decoupling Capacitor at VO Pin
It is recommended that a 1-2.2 mF ceramic capacitor be placed close
to the VO pin.
IS to GND Pin Current Sense Resistor
This sense resistor is chosen such that the required full scale current
produces a 32 mV drop across IS and GND pins. A 1% or lower
tolerance resistor is recommended. This sense resistor needs to be
placed as close to the InnoSwitch3-Pro IC pins as possible for
accurate current measurement and CC regulation.
Bus Switch
A low RDS(ON) N-channel FET bus switch is recommended to reduce
impact of efficiency at high load currents. The FET need not be a
logic level FET. It should be sufficiently enhanced at a gate threshold
of 4 V.
External Controller
An external controller is needed to send the I2C commands to the
InnoSwitch3-Pro IC over the SDA and SCL lines. For standalone
applications, the external controller can get its supply from the uVCC
pin of the InnoSwitch3-Pro IC. It should be able to sustain operation
for a supply voltage as low as 2.8 V.
Recommendations for Circuit Board Layout
See Figure 35 for a recommended circuit board layout for a switching
power supply using InnoSwitch3-Pro IC.
Single-Point Grounding
Use a single-point ground connection from the input filter capacitor to
the area of copper connected to the SOURCE pins.
Bypass Capacitors
The PRIMARY BYPASS and SECONDARY BYPASS pin capacitor must
be located directly adjacent to the PRIMARY BYPASS-SOURCE and
SECONDARY BYPASS-SECONDARY GROUND pins respectively and
connections to these capacitors should be routed with short traces.
Primary Loop Area
The area of the primary loop that connects the input filter capacitor,
transformer primary and IC should be kept as small as possible.
IS to GND Pin Capacitor
A 1 mF or higher ceramic capacitor is recommended to be used
between the IS and GND pins of the InnoSwitch3-Pro IC for accurate
constant current regulation.
Primary Clamp Circuit
A clamp is used to limit peak voltage on the DRAIN pin at turn-off.
This can be achieved by using an RCD clamp or a Zener diode (~200 V)
and diode clamp across the primary winding. To reduce EMI, minimize
the loop from the clamp components to the transformer and IC.
Thermal Considerations
The SOURCE pin is internally connected to the IC lead frame and
provides the main path to remove heat from the device. Therefore
the SOURCE pin should be connected to a copper area underneath
the IC to act not only as a single point ground, but also as a heat
sink. As this area is connected to the quiet source node, this area
should be maximized for good heat sinking. Similarly for output
SR FET, maximize the PCB area connected to the pins on the package
through which heat is dissipated from the SR FET.
Sufficient copper area should be provided on the board to keep the IC
temperature safely below the absolute maximum limits. It is
recommended that the copper area provided for the copper plane on
which the SOURCE pin of the IC is soldered is sufficiently large to
33
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
keep the IC temperature below 110 °C when operating the power
supply at full rated load and at the lowest rated input AC supply
voltage. Further de-rating can be applied depending on any
additional specific requirements.
uVCC, SDA and SCL Pins
The traces to SDA and SCL pins should be kept away from any noise
node or trace. If possible a shield trace should be made in parallel to
the SDA and SCL traces.
Y Capacitor
The Y capacitor should be placed directly between the primary input
filter capacitor positive terminal and the output positive or return
terminal of the transformer secondary. Such a placement will route
high amplitude common mode surge currents away from the IC.
Note – if an input π (C, L, C) EMI filter is used then the inductor in the
filter should be placed between the negative terminals of the input
filter capacitors.
ESD
Sufficient clearance should be maintained (>8 mm) between the
primary-side and secondary-side circuits to enable easy compliance
with any ESD / hi-pot requirements.
Output SR FET
For best performance, the area of the loop connecting the secondary
winding, the output SR FET and the output filter capacitor, should be
minimized. The Source pin connection of the SR FET should be
connected to the output capacitor negative terminal and the GND pin
of the InnoSwitch3-Pro IC in a short connection to reduce the trace
impedance drop as this is critical for FWD pin sensing wrt IC GND pin
in order to turn OFF the SR FET during Discontinuous mode of
operation. The connection between the Drain of the SR FET and the
FWD pin resistor should also be made short. In addition, sufficient
copper area should be provided at the terminals of the SR FET for
heat sinking.
IS-GND Pin, Sense Resistor Traces
It is recommended to have the traces from the current sense resistor
to the IS-GND pins to be in a star connection at the respective two
nodes of the current sense resistor in order to have an accurate CC
set-point. The IS-GND sense traces should be at the innermost of
the solder pads of the current sense resistor to avoid measuring any
drop across the solder pads of the resistor or the load traces coming
in and out of the sense resistor.
The spark gap is best placed directly between output positive rail and
one of the AC inputs. In this configuration a 6.4 mm spark gap is
often sufficient to meet the creepage and clearance requirements of
many applicable safety standards. This is less than the primary to
secondary spacing because the voltage across spark gap does not
exceed the peak of the AC input. To further improve ESD performance, spark gaps can be added under common mode chokes.
If there is a controller used for USB PD communication then the
Ground of the controller should be connected to the GND pin of the
InnoSwitch3-Pro IC and not the GND pin of the type C connector, this
helps for ESD performance. However, if there is a separate daughter
board connected with the controller IC on it and the Ground path
becomes long then the Ground of the controller IC can be connected
closer to the USB connector GND pins to help in the eye diagram
during USB PD compliance tests.
Drain Node
The drain switching node is the dominant noise generator. As such
the components connected the drain node should be placed close to
the IC and away from sensitive feedback circuits. The clamp circuit
components should be located physically away from the PRIMARY
BYPASS pin and associated circuit trace lengths should be minimized.
The loop area of the loop comprising of the input rectifier filter
capacitor, the primary winding and the IC primary-side switch should
be kept as small as possible.
34
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
Layout Example
Optional Y capacitor connection to
the plus bulk rail on the primary-side
for surge protection
Maximize source area
for good heat sinking
PCB Top Side
Keep drain and clamp loop short;
keep drain components away from
PRIMARY BYPASS and UNDER/
OVER INPUT VOLTAGE pin circuitry
Keep BPP and BPS
capacitors near the IC
>6.4 mm spark gap
Keep IS-GND sense
resistor close to IC
Keep output SR FET
and output filter
capacitor loop short
PCB Bottom Side
Maximize source Place VOLTAGE pin sense
resistor close to the
area for good
heat sinking
VOLTAGE pin
In order to increase ESD immunity
and to meet isolation requirement,
no traces are routed beneath the IC
Place forward sense
resistor near the IC
PI-8611-020520
Figure 35. PCB Layout Recommendation.
35
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
Optional Y capacitor connection to
the plus bulk rail on the primary-side
for surge protection
Maximize source area
for good heat sinking
Keep output SR FET source,
output capacitor negative
terminal and IC GND
connection short
PCB Top Side
Keep drain and clamp loop short;
keep drain components away from
PRIMARY BYPASS and UNDER/
OVER INPUT VOLTAGE pin circuitry
Keep BPP and BPS
capacitors near the IC
>6.4 mm spark gap
Keep IS GND sense
resistor close to IC and
connect in star connection
at the nodes of resistor
Place forward sense resistor
near the IC and keep the FWD
SR FET drain connection short
PCB Bottom Side
Maximize source
area for good
heat sinking
Place VOLTAGE pin sense
resistor close to the
VOLTAGE pin
In order to increase ESD immunity
and to meet isolation requirement,
no traces are routed beneath the IC
PI-8612-020520
Figure 36. PCB Layout Recommendation.
Recommendations for EMI Reduction
1. Appropriate component placement and small loop areas of the
primary and secondary power circuits help minimize radiated and
conducted EMI. Care should be taken to achieve a compact loop
area and keeping the switching nodes/traces away from the quiet
nodes/traces.
2. A small capacitor in parallel to the clamp diode on the primaryside can help reduced radiated EMI.
3. A resistor in series with the bias winding helps reduce radiated EMI.
4. Common mode chokes are typically required at the input of the
power supply to sufficiently attenuate common mode noise. The
same can be achieved by using shield windings on the transformer.
Shield windings can also be used in conjunction with common
mode filter inductors at input to achieve improved conducted and
radiated EMI margins.
5. Values of components of the RC snubber connected across the
output SR FET can help reduce high frequency radiated and
conducted EMI.
6. A π filter comprising of differential inductors and capacitors can
be used in the input rectifier circuit to reduce low frequency
differential EMI.
7. A 1 mF or higher ceramic capacitor when connected at the output
of the power supply helps to reduce radiated EMI.
36
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
Recommendations for Transformer Design
Transformer design must ensure that the power supply is able to
deliver the rated power at the lowest input voltage. The lowest
voltage on the rectified DC bus of the power supply depends on the
capacitance of the filter capacitor used. At least 2 mF / W is recommended to keep the DC bus voltage always above 70 V, though
3 mF / W provides sufficient margin. The ripple on the DC bus should
be measured and care should be taken to verify this voltage to
confirm the design calculations for transformer primary-winding
inductance selection.
Switching Frequency (FSW)
It is a unique feature in InnoSwitch3-Pro ICs that a designer can set
the switching frequency at full load between 25 kHz to 95 kHz
depending on the design specification. To have lower device
temperature, the switching frequency can be set to around 60 kHz.
To have smaller size transformer, the switching frequency needs to be
set to a value closer to a maximum of 95 kHz. When setting the full
load switching frequency, it is important to consider primary
inductance and peak current tolerances to ensure that average
switching frequency does not exceed 110 kHz which may trigger
auto-restart due to overload protection. The following table provides
a guide for frequency selection based on the device size. This
represents the best compromise between the overall device losses
(conduction and switching losses) based on size of the internal
high-voltage switch.
INN3365C / INN3375C
80 kHz
INN3366C / INN3376C
75 kHz
INN3377C
70 kHz
INN3367C / INN3368C
65 kHz
PowiGaN device INN3378C
70 kHz
PowiGaN device INN3379C
65 kHz
PowiGaN device INN3370C
60 kHz
Reflected Output Voltage, VOR (V)
This parameter describes the effect on the primary switch Drain
voltage of the secondary-winding voltage during the diode / SR
conduction which is reflected back to the primary through the turns
ratio of the transformer. To make full use of QR capability and ensure
flattest efficiency over line / load, it is better to set reflected output
voltage (VOR) to maintain KP = 0.8 at minimum input voltage conditions for universal line input and KP = 1 for high-line input only
conditions.
The following should be kept in mind for design optimization:
1. Higher VOR allows increased power delivery at VMIN, which
minimizes the value of the input capacitor and maximizes power
delivery from a given InnoSwitch3-Pro device.
2. Higher VOR reduces the voltage stress on the output diodes and
SR FETs.
3. Higher VOR increases leakage inductance that reduces efficiency of
the power supply.
4. Higher VOR increases peak and RMS current on the secondary-side
which may increase secondary-side copper and diode losses.
There are some exceptions to this. For very high output currents
where the VOR should be reduced to get highest efficiency, and higher
output voltages above 15 V, VOR should be higher to maintain a
reasonable PIV across the output synchronous rectifier.
Ripple to Peak Current Ratio, KP
A KP below 1, indicates continuous conduction mode, KP is the ratio of
ripple-current to peak-primary-current (Figure 38).
KP ≡ KRP = IR /IP
A value of KP higher than 1, indicates discontinuous conduction mode.
In this case, KP is the ratio of primary switch off-time to the secondary diode conduction-time.
KP ≡ KDP = (1 – D) x T / t = VOR × (1 – DMAX) / (VMIN – VDS) × DMAX
It is recommended that a KP close to 0.9 at the minimum expected DC
bus voltage should be used for most InnoSwitch3-Pro IC designs. A
KP value of 1
T = 1/fS
Primary
D×T
(1-D) × T = t
Secondary
(b) Borderline Discontinuous/Continuous, KP = 1
PI-2578-103114
Figure 37. Discontinuous Mode Current Waveform, KP ≥ 1.
38
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
Transformer Construction for Mitigation of Audible Noise
Although InnoSwitch3-Pro features audible noise reduction engine
which prevents operation in the predominant audible range, application of the thixotropic epoxy glue in the transformer air gap is
recommended. This helps to damp any audible noise when the
power supply operates at light load which results in the low
frequency operation.
VOR and the clamp voltage VCLM should be selected such that the peak
drain voltage is lower than 650 V for all normal operating conditions.
This provides sufficient margin to ensure that occasional increase in
voltage during line transients such as line surges will maintain the
peak drain voltage well below 750 V under abnormal transient
operating conditions. This ensures excellent long term reliability and
design margin.
Design Considerations When Using PowiGaN
Devices (INN3378C, INN3379C and INN3370C)
VOR choice will affect the operating efficiency and should be selected
carefully. Table below shows the typical range of VOR for optimal
performance:
For a flyback converter configuration, typical voltage waveform at the
drain pin of the IC is shown in Figure 39.
VOR is the reflected output voltage across the primary winding when
the secondary is conducting. VBUS is the DC voltage connected to one
end of the transformer primary winding.
In addition to VBUS+VOR, the drain also sees a large voltage spike at
turn off that is caused by the energy stored in the leakage inductance
of the primary winding. To keep the drain voltage from exceeding the
rated maximum continuous drain voltage, a clamp circuit is needed
across the primary winding. The forward recovery of the clamp diode
will add a spike at the instant of turn-OFF of the primary switch. VCLM
in Figure 39 is the combined clamp voltage including the spike. The
peak drain voltage of the primary switch is the total of VBUS, VOR and VCLM.
Output Voltage
Optimal Range for VOR
5V
45 - 70
12 V
80 - 120
15 V
100 - 135
20 V
120 - 150
24 V
135 - 180
750 V = VMAX(NON-REPETITIVE)
Safe Surge Voltage
Region (SSVR)
Typical margin (150 V)
gives de-rating of >80%
650 V = VMAX(CONTINUOUS)
VCLM
VOR
380 VDC
VBUS
Primary Switch Voltage Stress (264 VAC)
PI-8769-071218
Figure 39. Peak Drain Voltage for 264 VAC Input Voltage.
Quick Design Checklist
As with any power supply design, all InnoSwitch3-Pro designs should
be verified on the bench to make sure that component limits are not
exceeded under worst-case conditions.
The following minimum set of tests is strongly recommended:
1. Maximum Drain Voltage – Verify that VDS of InnoSwitch3-Pro and
SR FET do not exceed 90% of breakdown voltages at highest
input voltage and peak (overload) output power in normal
operating and start-up conditions.
2. Maximum Drain Current – At maximum ambient temperature,
maximum input voltage and peak output (overload) power, verify
drain current waveforms for any signs of transformer saturation
and excessive leading edge current spikes at start-up. Repeat
under steady-state conditions and verify that the leading edge
current spike event is below ILIMIT(MIN) at the end of the tLEB(MIN).
Under all conditions, the maximum drain current should be below
the specified absolute maximum ratings.
Thermal Check – At specified maximum output power, minimum input
voltage and maximum ambient temperature, verify that the temperature specification limits are not exceeded for InnoSwitch3-Pro IC,
transformer, output SR FET, and output capacitors. Enough thermal
margin should be allowed for part-to-part variation of the RDS(ON) of
InnoSwitch3-Pro IC as specified in the data sheet.
Under low-line, maximum power, a maximum InnoSwitch3-Pro IC
SOURCE pin temperature of 110 °C is recommended to allow for
these variations.
39
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
Thermal Resistance Test Conditions for
PowiGaN Devices (INN3378C, INN3379C and
INN3370C)
Thermal resistance value is for primary power device junction to
ambient only.
Testing performed on custom thermal test PCB as shown in Figure 40.
The test board consists of 2 layers of 2 oz. Cu with the InSOP
package mounted to the top surface and connected to a bottom layer
Cu heat sinking area of 550 mm2.
Connection between the two layers was made by 82 vias in a 5 x 17
matrix outside the package mounting area. Vias are spaced at
40 mils, with 12 mil diameter and plated through holes are not filled.
Figure 40. Thermal Resistance Test Conditions for PowiGaN
Thermal resistance
value
is for INN3379C
primary and
power
device junction to
Devices
(INN3378C,
INN3370C.)
ambient only.
Testing performed on custom thermal test PCB as shown in the figure
above. The test board consists of 2 layers of 2 oz. Cu with the InSOP
package mounted to the top surface and connected to a bottom layer
Cu heatsinking area of 550mm2.
Connection between the two layers was made by 82 vias in a 5 x 17
matrix outside the package mounting area. Vias are spaced at 40 mils,
with 12 mil diameter and plated through holes are not filled.
Figure xx. Thermal Resistance Test Conditions for INN3379C and INN3370C
40
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
Absolute Maximum Ratings1,2
DRAIN Pin Voltage: INN33x5C−INN33x8C ...... -0.3 V to 650 V / 725 V
DRAIN Pin Voltage6: INN3378C−INN3370C................... -0.3 V to 750 V
DRAIN Pin Peak Current: INN3365C........................................ 3.87 A7
INN3375C........................................ 4.11 A7
INN3366C........................................4.88 A7
INN3376C........................................ 5.19 A7
INN3367C........................................5.57 A7
INN3377C........................................ 5.92 A7
INN3368C........................................ 6.24 A7
PowiGaN device INN3378C.................6.5 A7
PowiGaN device INN3379C..................10 A7
PowiGaN device INN3370C..................14 A7
BPP/BPS Pin Voltage..........................................................-0.3 to 6 V
BPP/BPS Current .................................................................. 100 mA
SCL, SDA, uVCC Pin Voltage..............................................-0.3 to 6 V
uVCC Current5 ........................................................................ 12 mA
FWD Pin Voltage ....................................................... -1.5 V to 150 V
SR Pin Voltage ..............................................................-0.3 V to 6 V
V Pin Voltage ............................................................ -0.3 V to 650 V
VOUT Pin Voltage ....................................................... -0.3 V to 27 V
VB/D Pin Voltage ......................................................... -0.3 V to 35 V
IS Pin Voltage ...............................................................-0.3 V to 0.3 V8
Storage Temperature .................................................. -65 to 150 °C
Operating Junction Temperature3.................................. -40 to 150 °C
Ambient Temperature.................................................. -40 to 105 °C
Lead Temperature4................................................................ 260 °C
Notes:
1. All voltages referenced to SOURCE and Secondary GROUND,
TA = 25 °C.
2. Maximum ratings specified may be applied one at a time without
causing permanent damage to the product. Exposure to Absolute
Maximum Ratings conditions for extended periods of time may
affect product reliability.
3. Normally limited by internal circuitry.
4. 1/16” from case for 5 seconds.
5. Only at 5 V output, the uVCC pin can supply 48 mA maximum
current for 0.5 seconds.
6. PowiGaN devices:
Maximum drain voltage (non-repetitive pulse); for derating
calculation............................................................-0.3 V to 750 V
Maximum continuous drain voltage.........................-0.3 V to 650 V
7. Please refer to Figures 42, 48 and 56 for maximum allowable
voltage and current combinations.
8. Absolute maximum voltage for less than 500 µs is 3 V.
Thermal Resistance
Thermal Resistance:
INN33x5C to INN33x8C
(qJA)............................. 76 °C/W1, 65 °C/W2
(qJC)..............................................8 °C/W3
PowiGaN devices INN3378C to INN3370C
(qJA)............................................ 50 °C/W4
Parameter
Notes:
1. Soldered to 0.36 sq. inch (232 mm2) 2 oz. (610 g/m2) copper clad.
2. Soldered to 1 sq. inch (645 mm2), 2 oz. (610 g/m2) copper clad.
3. The case temperature is measured on the top of the package.
4. Please see Figure 40.
Conditions
Rating
Units
Current from pin (16-19) to pin 24
1.5
A
TAMB = 25 °C
(device mounted in socket resulting in TCASE = 120 °C)
1.35
W
TAMB = 25 °C
(device mounted in socket)
0.125
W
Clearance
12.1
mm (typ)
Creepage
11.7
mm (typ)
Distance Through
Insulation (DTI)
0.4
mm (min)
6
kV (min)
600
-
Ratings for UL1577
Primary-Side
Current Rating
Primary-Side
Power Rating
Secondary-Side
Power Rating
Package Characteristics
Transient Isolation
Voltage
Comparative Tracking
Index (CTI)
41
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
Symbol
Conditions
SOURCE = 0 V
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Min
Typ
Max
Units
Startup Switching
Frequency
fSW
TJ = 25 °C
23
25
27
kHz
Jitter Modulation
Frequency
fM
TJ = 25 °C
fSW = 100 kHz
0.80
1.25
1.70
kHz
Maximum On-Time
tON(MAX)
TJ = 25 °C
12.4
14.6
16.9
µs
Minimum Primary
Feedback Block-Out
Timer
tBLOCK
tOFF(MIN)
µs
Parameter
Control Functions
IS1
BPP Supply Current
IS2
BPP Pin Charge Current
ICH1
VBPP = VBPP + 0.1 V
(Switch not Switching)
TJ = 25 °C
VBPP = VBPP + 0.1 V
(Switch Switching
at 132 kHz)
TJ = 25 °C
VBP = 0 V, TJ = 25 °C
INN33x5C –
INN33x8C
145
200
425
INN3378C –
INN3370C
145
266
425
INN3365C
0.49
0.65
1.03
INN3366C
0.64
0.86
1.21
INN3367C
0.77
1.03
1.38
INN3368C
0.90
1.20
1.75
INN3375C
0.59
0.79
1.10
INN3376C
0.77
1.02
1.38
INN3377C
0.90
1.20
1.73
INN3378C
0.93
1.24
1.79
INN3379C
INN3370
1.46
1.95
2.81
INN33x5C –
INN33x8C
-1.73
-1.35
-0.88
INN3378C –
INN3370C
-1.75
-1.35
-0.88
mA
mA
mA
ICH2
VBP = 4 V, TJ = 25 °C
-5.98
-4.65
-3.32
BPP Pin Voltage
VBPP
TJ = 25 °C
4.65
4.90
5.15
V
BPP Pin Voltage
Hysteresis
VBPP(H)
TJ = 25 °C
0.22
0.39
0.55
V
BPP Shunt Voltage
VSHUNT
IBPP = 2 mA
5.15
5.36
5.65
V
VBPP(RESET)
TJ = 25 °C
2.80
3.15
3.50
V
INN33x5C –
INN33x8C
23.9
26.1
28.2
INN3378C –
INN3370C
22.4
24.4
26.7
INN33x5C –
INN33x8C
21.0
23.7
25.5
INN3378C –
INN3370C
19.0
21.6
23.5
BPP Power-Up Reset
Threshold Voltage
UV/OV Pin Brown-In
Threshold
IUV+
UV/OV Pin Brown-Out
Threshold
IUV-
Brown-Out Delay Time
tUV-
TJ = 25 °C
TJ = 25 °C
35
µA
µA
ms
42
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
Parameter
Symbol
Conditions
SOURCE = 0 V
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Min
Typ
Max
INN33x5C –
INN33x8C
106
115
118
INN3378C –
INN3370C
106
112
118
Units
Control Functions (cont.)
UV/OV Pin Line
Overvoltage Threshold
IOV+
TJ = 25 °C
UV/OV Pin Line
Overvoltage Hysteresis
IOV(H)
UV/OV Pin Line
Overvoltage Recovery
Threshold
IOV-
TJ = 25 °C
VOLTAGE Pin Line Overvoltage Deglitch Filter
tOV+
TJ = 25 °C
VOLTAGE Pin
Voltage Rating
VV
TJ = 25 °C
TJ = 25 °C
INN33x5C –
INN33x8C
7
INN3378C –
INN3370C
8
µA
µA
100
µA
Line Fault Protection
3
µs
650
V
Circuit Protection
Standard Current Limit
(BPP) Capacitor =
0.47 mF
See Note D
Increased Current Limit
(BPP) Capacitor =
4.7 mF
See Note D
Overload Detection
Frequency
di/dt = 213 mA/ms
TJ = 25 °C
INN33x5C
883
950
1017
di/dt = 238 mA/ms
TJ = 25 °C
INN33x6C
1162
1250
1338
INN3377C
1255
1350
1445
INN3367C
1348
1450
1552
di/dt = 375 mA/ms
TJ = 25 °C
INN3368C
1534
1650
1766
di/dt = 375 mA/ms
TJ = 25 °C
INN3378C
1581
1700
1819
di/dt = 425 mA/ms
TJ = 25 °C
INN3379C
1767
1900
2033
di/dt = 525 mA/ms
TJ = 25 °C
INN3370C
2139
2300
2461
di/dt = 213 mA/ms
TJ = 25 °C
INN33x5C
1046
1150
1254
di/dt = 238 mA/ms
TJ = 25 °C
INN33x6C
1319
1450
1581
INN3377C
1410
1550
1689
INN3367C
1501
1650
1799
di/dt = 375 mA/ms
TJ = 25 °C
INN3368C
1683
1850
2017
di/dt = 375 mA/ms
TJ = 25 °C
INN3378C
1767
1900
2033
di/dt = 425 mA/ms
TJ = 25 °C
INN3379C
1980
2130
2279
di/dt = 525 mA/ms
TJ = 25 °C
INN3370C
2395
2576
2756
102
110
118
di/dt = 300 mA/ms
TJ = 25 °C
ILIMIT
di/dt = 300 mA/ms
TJ = 25 °C
ILIMIT+1
fOVL
TJ = 25 °C
mA
mA
kHz
43
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
Symbol
Conditions
SOURCE = 0 V
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Min
Typ
Max
Units
BYPASS Pin Fault
Shutdown Threshold
Current
ISD
TJ = 25 °C
6.0
7.5
11.3
mA
Auto-Restart On-Time
t AR
TJ = 25 °C
75
82
89
ms
Auto-Restart Trigger
Skip Time
t AR(SK)
TJ = 25 °C
See Note A
Auto-Restart Off-Time
t AR(OFF)
TJ = 25 °C
1.7
t AR(OFF)SH
TJ = 25 °C
0.17
Parameter
Circuit Protection
Short Auto-Restart
Off-Time
1.3
sec
2.11
sec
0.20
0.23
sec
TJ = 25 °C
1.95
2.24
TJ = 100 °C
3.02
3.47
TJ = 25 °C
1.95
2.24
TJ = 100 °C
3.02
3.47
TJ = 25 °C
1.30
1.50
TJ = 100 °C
2.02
2.32
TJ = 25 °C
1.34
1.54
TJ = 100 °C
2.08
2.39
TJ = 25 °C
1.02
1.17
TJ = 100 °C
1.58
1.82
TJ = 25 °C
1.20
1.38
TJ = 100 °C
1.86
2.14
TJ = 25 °C
0.86
0.99
TJ = 100 °C
1.33
1.53
TJ = 25 °C
0.52
0.68
TJ = 100 °C
0.78
1.02
TJ = 25 °C
0.35
0.44
TJ = 100 °C
0.49
0.62
TJ = 25 °C
0.29
0.39
TJ = 100 °C
0.41
0.54
Output
INN3365C
ID = ILIMIT+1
INN3375C
ID = ILIMIT+1
INN3366C
ID = ILIMIT+1
INN3376C
ID = ILIMIT+1
ON-State Resistance
RDS(ON)
INN3367C
ID = ILIMIT+1
INN3377C
ID = ILIMIT+1
INN3368C
ID = ILIMIT+1
INN3378C
ID = ILIMIT+1
INN3379C
ID = ILIMIT+1
INN3370C
ID = ILIMIT+1
OFF-State Drain
Leakage Current
IDSS1
VBPP = VBPP + 0.1 V
VDS = 80% Peak Drain Voltage
TJ = 125 °C
IDSS2
VBPP = VBPP + 0.1 V
VDS = 325 V
TJ = 25 °C
Drain Supply Voltage
200
15
TSD
See Note A
Thermal Shutdown
Hysteresis
TSD(H)
See Note A
135
mA
mA
50
Thermal Shutdown
W
V
142
70
150
°C
°C
44
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
Parameter
Symbol
Conditions
SOURCE = 0 V
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Min
Typ
Max
Units
fSREQ
TJ = 25 °C
118
132
145
kHz
Secondary
Maximum Secondary
Frequency
Minimum Off-time
tOFF(MIN)
2.48
3.38
4.37
ms
BPS Pin Latch
Command Shutdown
Threshold Current
IBPS(SD)
5.2
8.9
12
mA
5
5.15
V
Start-up VOUT Pin
Regulation Voltage
VOUTREG
TJ = 25 °C
4.85
VOUT(R)
Default = 5 V
3.00
24.00
V
TOLVOUT
Tolerance
TJ = 25 °C
-3
+3
%
Output Voltage
Step Size
∆VOUT
TJ = 25 °C
Report-Back Output
Voltage Tolerance
VOUT(T)
TJ = 25 °C
-3
+3
0.6 - 1.0
TJ = 25 °C, See Note C
-5
+5
0.2
TJ = 25 °C, See Note C
-15
+15
Output Voltage
Programming Range
10
mV
%
Normalized Output
Current
IOUT
Normalized Output
Current Step Size
∆IOUT
TJ = 25 °C
0.78
%
tVI
See Note B
10
ms
Minimum Time Delay
Between I2C Commands
tDELAY
See Note B
Internal Current Limit
Voltage Threshold
ISV(TH)
TJ = 25 °C
Across External IS to GND Pin Resistor
See Note F
Cable Drop
Compensation (CDC)
Programming Range
∆φCD
TJ = 25 °C
Default = 0 V
0
600
mV
TOLφCD
CDC ≥ 100 mV
TJ = 25 °C
-25
25
mV
Maximum V/I
Update Rate
CDC Tolerance
%
150
ms
32
mV
CDC Programming
Step Size
∆φCD
Output Overvoltage
Programming Range
VOVA
Default = 6.2 V
6.2
25
V
Output Overvoltage
Tolerance
TOLOVA
TJ = 25 °C
-3
3
%
50
mV
Output Overvoltage
Programming Step Size
∆VOVA
Output Undervoltage
Programming Range
VUVA
Default = 3.6 V
3
24
V
Output Undervoltage
Tolerance
TOLUVA
TJ = 25 °C
-3
3
%
100
mV
45
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
Parameter
Symbol
Conditions
SOURCE = 0 V
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Min
Typ
Max
Units
Secondary (cont.)
Output Undervoltage
Programming Step Size
Output Undervoltage
Timer Programming
Options
100
∆VUVA
tUVL
TJ = 25 °C
See Notes B, E
Programming Option 1
8
Programming Option 2
16
Programming Option 3
32
Programming Option 4
64
mV
ms
Constant Output Power
Onset Threshold
Programming Range
VKP
Default = 24 V
5.3
24
V
Constant Output Power
Tolerance
TOLPOUT
At 85% of Full Scale Current
-10
+10
%
Constant Output Power
Onset Threshold
Programming Step Size
∆VKP
Constant Voltage Mode
Timer Programming
Options
Watchdog Timer
tCVO
tWDT
100
TJ = 25 °C
See Notes B, E
Programming Option 1
8
Programming Option 2
16
Programming Option 3
32
Programming Option 4
64
Default Programming Option 1
See Note B
0.5
Programming Option 2, See Note B
1
Programming Option 3, See Note B
2
VB/D Drive Voltage
V VB/D
With Respect to VOUT Pin
VB/D Turn-On Time
tR(VB/D)
TJ = 25 °C
CLOAD = 10 nF
VB/D Turn-Off Time
tF(VB/D)
TJ = 25 °C
CLOAD = 10 nF
VB/D Pin Load
Discharge Internal
On-State Resistance
RB/D(ON)
20
VB/D Pin Load
Discharge Internal
Off-State Resistance
RB/D(OFF)
80
4
mV
ms
sec
10
V
4
10
ms
4
10
ms
35
70
W
kW
Programming Option 1
See Note B
40
Programming Option 2
See Note B
60
Secondary OverTemperature Hysteresis
TSEC(HYS)
VOUT Pin Bleeder
Current
IVOBLD
VOUT = 5 V
170
270
380
mA
uVCC Supply Voltage
uVCC
IuVCC = 0 A
VOUT = 5 V
3.42
3.60
3.78
V
°C
46
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
Parameter
Symbol
Conditions
SOURCE = 0 V
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Min
Typ
Max
Units
Secondary (cont.)
uVCC > 3.3 V, VOUT = 5 V
Maximum uVCC Supply
Current
IuVCC
TJ = 25 °C, See Note 5 in Absolute
Maximum Ratings Table
uVCC Reset Voltage
Threshold
BPS Pin Voltage
BPS Pin Current
mA
uVCC > 3.3 V
3.9 V ≤ VOUT
10
RuVCC
TJ = 25 °C
18
uVCCRST
See Note B
TJ = 25 °C
uVCC Pin Output
Resistance
48
24
W
2.65
V
4.4
4.6
V
TJ = 25 °C
VBUS Switch Open
0.67
0.85
TJ = 25 °C
VBUS Switch Closed
1.03
1.3
3.8
4.0
4.2
VBPS
ISNL
BPS Pin Undervoltage
Threshold
VBPS(UVLO)TH
BPS Pin Undervoltage
Hysteresis
VBPS(UVLO)TH
Soft Start Frequency
Ramp Time
tSS(RAMP)
FORWARD Pin
Breakdown Voltage
BVFWD
21
mA
3.6
0.65
TJ = 25 °C
7.5
11.8
V
V
19
150
ms
V
Synchronous Rectifier @ TJ = 25 °C
SR Pin Drive Voltage
4.2
VSR
4.4
4.6
V
-2.5
0
mV
SR Pin Voltage
Threshold
VSR(TH)
SR Pin Pull-Up Current
ISR(PU)
TJ = 25 °C
CLOAD = 2 nF
fS = 100 kHz
125
165
195
mA
SR Pin Pull-Down
Current
ISR(PD)
TJ = 25 °C
CLOAD = 2 nF
fS = 100 kHz
238
265
314
mA
Rise Time
tR(SR)
TJ = 25 °C
CLOAD = 2nF
See Note B
10-90%
50
ns
Fall Time
tF(SR)
TJ = 25 °C
CLOAD = 2nF
See Note B
90-10%
30
ns
Output Pull-Up
Resistance
RPU
TJ = 25 °C
VBPS + 0.1 V
ISR = 30 mA
7.2
8.9
12
W
Output Pull-Down
Resistance
RPD
TJ = 25 °C
VBPS + 0.2 V
ISR = 30 mA
3.5
4.7
5.5
W
47
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
Parameter
Symbol
Conditions
SOURCE = 0 V
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Min
Typ
Max
Units
50
400
700
kHz
I2C Bus Specifications (SDA and SCL Pins) *See Note B
SCL Clock Frequency
fSCL
Low-level Input Voltage
VIL
-0.5
0.3 ×
uVCC
V
High-level Input Voltage
VIH
0.7 ×
uVCC
uVCC +
0.5 V
V
Hysteresis of Schmitt
Trigger Inputs
VHYS
0.05 ×
uVCC
Low-Level Output
Voltage (Open Drain or
Collector)
VOL
Low-level Output
Current
IOL
Output Fall-Time from
VIH(MIN) to VIL(MAX)
tOF
Bus Capacitance from 10 pF to 400 pF
-
250
ns
SDA/SCL Input Current
II
(0.1 × uVCC) < (VSCL/VSDA) < (0.9 × uVCC)
-1
1
mA
SDA/SCL Capacitance
CI
-
10
pF
Pulse Width of Spike
Suppressed by Input
Filter
tSP
50
ns
See Note G
uVCC >2.8 V
3 mA Sink Current
0
V
0.4
3
V
mA
High Period for SCL Clock
tHIGH
fSCL = 400 kHz
0.6
ms
Low Period for SCL Clock
tLOW
fSCL = 400 kHz
1.3
ms
Serial Data Set-up Time
tSU:DAT
100
ns
Serial Data Hold time
tHD:DAT
0
sec
Valid Data Time
tVD:DAT
SCL Low to SDA Output Valid
0.9
ms
Valid Data Time for ACK
tVD:ACK
ACK from SCL Low to SDA Low
0.9
ms
I C Bus Free Time
Between Start and Stop
tBUF
I2C Fall Time
(Both SCL and SDA)
t fCL
300
ns
I2C Rise Time
(Both SCL and SDA)
trCL
300
ns
2
1.3
ms
I2C Start or Repeated
Start Condition Set-up
Time
tSU:STA
0.6
ms
I2C Start or Repeated
Start Condition Hold
Time
tHD:STA
0.6
ms
48
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
Parameter
Symbol
Conditions
SOURCE = 0 V
TJ = -40 °C to 125 °C
(Unless Otherwise Specified)
Min
Typ
Max
Units
I2C Bus Specifications (SDA and SCL Pins) *See Note B
I2C Stop Condition
Setup Time
tSU:STO
0.6
ms
Capacitive Load
CB
Noise Margin at the
Low Level
VNL
0.1 ×
uVCC
V
Noise Margin at the
High Level
VNH
0.1 ×
uVCC
V
50
ms
SCL Pin Interrupt Timer
400
TJ = 25 °C
tINT(SCL)
pF
NOTES:
A.
B.
C.
D.
This parameter is derived from characterization.
This parameter is guaranteed by design.
Use 1% tolerance resistor.
To ensure correct current limit it is recommended that nominal 0.47 mF / 4.7 mF capacitors are used. In addition, the BPP capacitor value
tolerance should be equal or better than indicated below across the ambient temperature range of the target application. The minimum and
maximum capacitor values are guaranteed by characterization.
Nominal BPP Pin
Capacitor Value
BPP Capacitor Value Tolerance
Minimum
Maximum
0.47 mF
-60%
+100%
4.7 mF
-50%
N/A
Recommended to use at least 10 V / 0805 / X7R SMD MLCC.
E. Settling delay in averaging register will increase total observed time under light and no-load conditions.
F. This parameter should be used only for calculation of typical value of current sense resistor. The value programmed in CC register (0x98)
regulates the output current. The tolerance is specified in the Normalized Output Current parameter (IOUT).
G. Guarantee minimum low period for SCL clock of 930 ns while operating at any SCL clock frequency. This may require using asymmetrical
SCL clock (reduced duty cycle) at higher frequencies.
49
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
Repeated
Start
Start
tf
SDA
Stop
Start
tr
V IH
V IL
t BUF
t HD :DAT
t SU :DAT
t SU:STA
t SU:STO
t LOW
SCL
t HD:sta
t HIGH
Figure 41. I2C Timing Diagram.
50
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
Scaling Factors:
INN3365 3.20
INN3366 4.80
INN3367 6.10
INN3368 7.65
1.2
1.0
0.8
0.6
0.4
TCASE = 25 °C
TCASE = 100 °C
0.2
0
100 200 300 400 500
0
600 700
Drain Voltage (V)
4
6
8
10
Figure 43. Output Characteristics.
75
Power (mW)
PI-8507-102617
Scaling Factors:
INN3365 3.20
INN3366 4.80
INN3367 6.10
INN3368 7.65
1000
2
Drain Voltage (V)
Figure 42. Maximum Allowable Drain Current vs. Drain Voltage
(INN336x).
10000
0
100
PI-8508-102617
0.0
Drain Capacitance (pF)
PI-8506-101218
1.0
1.4
Drain Current (A)
PI-8505-072519
Drain Current (A)
(Normalized to Absolute
MaximumCurrent Rating)
Typical Performance Curves
Scaling Factors:
INN3365 3.20
INN3366 4.80
INN3367 6.10
INN3368 7.65
50
25
10
Switching Frequency = 100 kHz
1
100
200
300
400
500
600
Figure 44. COSS vs. Drain Voltage.
25
50
75 100 125 150
Junction Temperature (°C)
Figure 46. Breakdown vs. Temperature (Exclude INN3378C / INN3379C
/ INN3370C).
SYNCHRONOUS RECTIFIER DRIVE
Pin Voltage Limits (V)
PI-2213-012301
Breakdown Voltage
(Normalized to 25 °C)
1.0
0
100
200
300
400
500
600
Figure 45. Drain Capacitance Power.
1.1
0.9
-50 -25
0
Drain Voltage (V)
Drain Voltage (V)
VSR(t)
PI-7474-011215
1
0
-0.0
-0.3
-1.8
500 ns
Time (ns)
Figure 47. SYNCHRONOUS RECTIFIER DRIVE Pin Negative
Voltage.
51
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
0.75
0.50
0.25
1.0
0.8
0.6
0.4
TCASE = 25 °C
TCASE = 100 °C
0.2
0
0
100 200 300 400 500 600 700 800
Drain Voltage (V)
4
6
8
10
Figure 49. Output Characteristics.
100
PI-8511-102617
Scaling Factors:
INN3375 3.20
INN3376 4.60
INN3377 5.20
Scaling Factors:
INN3375 3.20
INN3376 4.60
INN3377 5.20
75
Power (mW)
1000
2
Drain Voltage (V)
Figure 48. Maximum Allowable Drain Current vs. Drain Voltage
(INN3375/76/77).
10000
0
100
10
PI-8512-102617
0.0
Drain Capacitance (pF)
Scaling Factors:
INN3375 3.20
INN3376 4.60
INN3377 5.20
1.2
Drain Current (A)
1.0
PI-8510-101218
1.4
PI-8966-042919
Drain Current (A)
(Normalized to Absolute
Maximum Current Rating)
Typical Performance Curves (cont.)
50
25
Switching Frequency = 100 kHz
1
1
100
200
300
400
500
0
600
0
100
200
300
400
500
600
Drain Voltage (V)
Drain Voltage (V)
Figure 50. COSS vs. Drain Voltage.
Figure 51. Drain Capacitance Power.
PI-8432-090717
Normalized Current Limit
1.4
1.2
1.0
0.8
0.6
Normalized
di/dt = 1
0.4
0.2
0
1
Note: For the
normalized current
limit value, use the
typical current limit
specified for the
appropriate BP/M
capacitor.
2
3
4
Normalized di/dt
Figure 52. Standard Current Limit vs. di/dt.
52
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
15
10
5
2
4
6
8
Scaling Factors:
INN3378C 0.62
INN3379C 1.0
INN3370C 1.4
200
100
50
100
200
300
400
Drain Voltage (V)
Figure 55. Drain Capacitance Power.
250
350
450
550
Figure 54. COSS vs. Drain Voltage.
150
0
150
Drain Voltage (V)
PI-8854k-101819
250
0 50
10
Drain Voltage VDS (V)
Power (mW)
100
10
0
Figure 53. Output Characteristics.
0
1000
500
100
PI-8851l-102219
0
TCASE = 25 °C
TCASE = 100 °C
Scaling Factors:
INN3378C 0.62
INN3379C 1.0
INN3370C 1.4
PI-8852k-101819
20
10000
Drain Capacitance (pF)
Scaling Factors:
INN3378C 0.62
INN3379C 1.0
INN3370C 1.4
Drain Current (A)
Drain Current IDS (A)
25
PI-8853k-101819
Typical Performance Curves (cont.)
10
Scaling Factors:
INN3378C 0.65
INN3379C 1.0
INN3370C 1.4
1
0.1
0.01
0.001
10
100
Drain Voltage (V)
1000
Figure 56. Maximum Allowable Drain Current vs. Drain Voltage
(PowiGaN Devices INN3378-INN3370).
53
www.power.com
Rev. R 06/23
www.power.com
0.057
0.049
Body Thickness
1.45
1.25
2
1
0.75 [0.030]
C B
24
SIDE VIEW
Coplanarity: 17 Leads
0.10 [0.004] C
TOP VIEW
0.012
0.008
4
C
Seating
Plane
C A B
16X
12 Lead Tips
C
C
A
4
2X
C A
2
3
Detail A
0.30
0.18
0.41
[0.016]
8.25
[0.325]
0.75
[0.030]
0.032
0.020
1.58
[0.062]
Standoff
0.010
0.004
6. Datums A & B to be determined at Datum H.
5. Controlling dimensions in millimeters [inches].
4. Does not include inter-lead flash or protrusions.
3. Dimensions noted are inclusive of plating thickness.
PI-8106-052620
POD-InSOP-24D Rev B
2.81
[0.111]
8.25
[0.325]
7.50
[0.295]
6.75
[0.266]
4.80
[0.189]
0.45 [0.018]
Ref.
PCB PAD LAYOUT
1.58
[0.062]
C
0.25
0.10
12.72
[0.501]
DETAIL A
Seating Plane
H
2. Dimensions noted are determined at the outermost extremes of the plastic body exculsive of mold flash, tie bar burrs, gate burrs, and interlead flash,
but including any mismatch between the top and bottom of the plastic body. Maximum mold protrusion is 0.18 [0.007] per side.
17X
0.012
0.007
0.25 [0.010]
0° – 8°
0.81
0.51
Gauge
Plane
0.20 [0.008] Ref.
BOTTOM VIEW
0.10 [0.004]
9.40 [0.370]
END VIEW
0.107
0.102
1.32 [0.052] Ref.
0.15 [0.006]
13.43 [0.529]
0.15 [0.006]
5 Lead Tips
0.25 [0.010] M
3
0.30
0.20
12
13
3
2.71
2.59
Notes:
1. Dimensioning and Tolerancing per ASME Y14.5M – 1994.
1.60 [0.063] Max.
Total Mounting Height
Pin #1 I.D.
10.80 [0.425]
0.10 [0.004]
2X
3.35 [0.132] Ref.
0.50 [0.020] Ref.
InSOP-24D
InnoSwitch3-Pro
Rev. R 06/23
54
InnoSwitch3-Pro
PACKAGE MARKING
InSOP-24D
INN3365C
4D842A1
A
E
1931
A H302
C
D
B
F
A. Power Integrations Registered Trademark
B. Assembly Date Code (last two digits of year (YY) followed by 2-digit work
week (WW)
C. Product Identification (Part #/Package Type)
D. Lot Identification Code
E. Pin 1 Indicator
F. Test Lot Information
PI-8645i-081020
55
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
Feature Code Table
Summary Features
H3011 / H3022
ILIM Selectable
Yes
Over-Temperature Protection
Hysteretic
Line OV/UV
Enabled
Line UV Timer (35 ms or 400 ms)
35 ms
Note 1. Not available for PowiGaN Devices INN3378 – INN3370.
Note 2. Recommended for all new designs.
MSL Table
Part Number
MSL Rating
INN33xxC
3
ESD and Latch-Up Table
Test
Conditions
Results
Latch-up at 125 °C
JESD78D
Charge Device Model ESD
ANSI/ESDA/JEDEC JS-002-2014
> ±1 kV on all pins
Human Body Model ESD
ANSI/ESDA/JEDEC JS-002-2014
> ±2 kV on all pins
> ±100 mA or > 1.5 × VMAX on all pins
Part Ordering Information
• InnoSwitch3 Product Family
• Pro Series Number
• Package Identifier
C
InSOP-24D
• H Code
• Tape & Reel and Other Options
INN 3365 C - H302 - TL
TL
Tape & Reel, 2 k pcs per reel.
56
www.power.com
Rev. R 06/23
InnoSwitch3-Pro
Revision Notes
Date
C
Code L release.
03/18
D
Added READ13, 14, 15 telemetry registers. Updated H301 feature summary. Clarified register descriptions.
06/18
E
Register fixes, schematic updates, added CTI parameter.
08/18
F
Added H302 column to Part Ordering Table.
05/19
G
Code A release of PowiGaN Devices INN3379C and INN3370C. Updated IDSS1 and IDSS2 parameters.
07/19
H
PCN-19432 – Updated Figure 35. Deleted VBPP(H) & IOV(H) Min & Max values. Updated IUV- Min value, IVOBLD Max value,
IuVCC Min value, tSS(RAMP) Max value, ISR(PU) Min value, ISR(PD) Option A & B Max values & RPU Max & Min values. Updated
tUV- Typ value, included IOV- Min value.
10/19
I
Code S release of PowiGaN Device INN3378C.
11/19
J
Code A release. Added new application design example.
01/20
K
Updated IDSS1 parameter to read VDS = 80% Peak Drain Voltage.
03/20
L
Updated safety information on page 1 and corrected typo in Package drawing on page 53.
06/20
M
Updated Package Marking.
08/20
N
Corrected Figure 29 caption text.
09/20
O
Updated Figure 11, added new paragraph under SCL/SDA Pull-up Requirements section and Note reference for fSCL
parameter. Updated per PCN-18441.
11/20
P
Added clarification on VBEN command.
04/22
Q
Updated 4th bullet point under Full Safety and Regulatory Compliance section on page 1.
11/22
R
Updated Note 6 in Absolute Maximum Ratings table.
06/23
57
www.power.com
Rev. R 06/23
For the latest updates, visit our website: www.power.com
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations
does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY
HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one
or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of
Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set
forth at www.power.com/ip.htm.
Life Support Policy
POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:
1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose
failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or
death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness.
Power Integrations, the Power Integrations logo, CAPZero, ChiPhy, CHY, DPA-Switch, EcoSmart, E-Shield, eSIP, eSOP, HiperLCS, HiperPLC,
HiperPFS, HiperTFS, InnoSwitch, Innovation in Power Conversion, InSOP, LinkSwitch, LinkZero, LYTSwitch, SENZero, TinySwitch, TOPSwitch, PI,
PI Expert, PowiGaN, SCALE, SCALE-1, SCALE-2, SCALE-3 and SCALE-iDriver, are trademarks of Power Integrations, Inc. Other trademarks are
property of their respective companies. ©2023, Power Integrations, Inc.
Power Integrations Worldwide Sales Support Locations
World Headquarters
5245 Hellyer Avenue
San Jose, CA 95138, USA
Main: +1-408-414-9200
Customer Service:
Worldwide: +1-65-635-64480
Americas: +1-408-414-9621
e-mail: usasales@power.com
China (Shanghai)
Rm 2410, Charity Plaza, No. 88
North Caoxi Road
Shanghai, PRC 200030
Phone: +86-21-6354-6323
e-mail: chinasales@power.com
Germany
(AC-DC/LED/Motor Control Sales)
Einsteinring 24
85609 Dornach/Aschheim
Germany
Tel: +49-89-5527-39100
e-mail: eurosales@power.com
Germany (Gate Driver Sales)
HellwegForum 3
59469 Ense
Germany
Tel: +49-2938-64-39990
e-mail: igbt-driver.sales@power.com
India
#1, 14th Main Road
China (Shenzhen)
17/F, Hivac Building, No. 2, Keji Nan Vasanthanagar
Bangalore-560052 India
8th Road, Nanshan District,
Phone: +91-80-4113-8020
Shenzhen, China, 518057
e-mail: indiasales@power.com
Phone: +86-755-8672-8689
e-mail: chinasales@power.com
Italy
Via Milanese 20, 3rd. Fl.
20099 Sesto San Giovanni (MI) Italy
Phone: +39-024-550-8701
e-mail: eurosales@power.com
Japan
Yusen Shin-Yokohama 1-chome Bldg.
1-7-9, Shin-Yokohama, Kohoku-ku
Yokohama-shi,
Kanagawa 222-0033 Japan
Phone: +81-45-471-1021
e-mail: japansales@power.com
Korea
RM 602, 6FL
Korea City Air Terminal B/D, 159-6
Samsung-Dong, Kangnam-Gu,
Seoul, 135-728, Korea
Phone: +82-2-2016-6610
e-mail: koreasales@power.com
Singapore
51 Newton Road
#19-01/05 Goldhill Plaza
Singapore, 308900
Phone: +65-6358-2160
e-mail: singaporesales@power.com
Taiwan
5F, No. 318, Nei Hu Rd., Sec. 1
Nei Hu Dist.
Taipei 11493, Taiwan R.O.C.
Phone: +886-2-2659-4570
e-mail: taiwansales@power.com
UK
Building 5, Suite 21
The Westbrook Centre
Milton Road
Cambridge
CB4 1YG
Phone: +44 (0) 7823-557484
e-mail: eurosales@power.com
工商网监
湘ICP备2023018690号
