INN3677C-H602-TL

InnoSwitch3-EP Family Off-Line CV/CC QR Flyback Switcher IC with Integrated Primary Switch, Synchronous Rectification and FluxLink Feedback Product Highlights Highly Integrated, Compact Footprint EcoSmart™ – Energy Efficient • Less than 30 mW no-load including line sense • Easily meets all global energy efficiency regulations InnoSwitch3-EP FB GND V BPS D SR SR FET FWD • High efficiency across load range • PowiGaN™ technology – up to 100 W without heat sinks • Multi-mode Quasi-Resonant (QR) / CCM flyback controller, highvoltage switch, secondary-side sensing and synchronous rectification driver • Excellent multi-output cross regulation with weighted secondary-side regulation (SSR) feedback and synchronous FETs • Integrated FluxLink™, HIPOT-isolated, feedback link • Exceptional CV/CC accuracy, independent of external components • Adjustable accurate output current sense using external resistor VOUT Primary Switch and Controller S BPP IS Figure 1. Typical Application Schematic. Optional Current Sense Adjustment Secondary Control IC PI-8184-020623 Advanced Protection / Safety Features • • • • • Open SR FET-gate detection Fast input line UV/OV protection Auto-restart fault response for output OVP 725 V and 750 V switch for excellent surge withstand 900 V and 1700 V switch for industrial design or extra safety margin Optional Features • Output UV protection • With auto-restart peak power delivery Full Safety and Regulatory Compliance • • • • Reinforced isolation Isolation voltage >4000 VAC 100% production HIPOT tested UL1577 isolation voltage 4000 VAC (max), TUV (EN62368-1), CQC (GB4943.1) and DIN EN IEC 60747-17 (VDE 0884-17) safety approved. See Note 4 • Excellent noise immunity enables designs that achieve class “A” performance criteria for EN61000-4 suite; EN61000-4-2, 4-3 (30 V/m), 4-4, 4-5, 4-6, 4-8 (100 A/m) and 4-9 (1000 A/m) Green Package • Halogen free and RoHS compliant Applications • Auxiliary, standby and bias power supplies for appliances, computers and consumer products • Utility meter, smart grid and industrial power supplies Description The InnoSwitch™3-EP family of ICs dramatically simplifies the design and manufacture of flyback power converters, particularly those requiring high efficiency and/or compact size. The InnoSwitch3-EP family combines primary and secondary controllers and safety-rated feedback into a single IC. InnoSwitch3-EP family devices incorporate multiple protection features including line over and undervoltage protection, output overvoltage and over-current limiting, and over-temperature shutdown. Devices are available with standard and peak power delivery options, and commonly used auto-restart protection behaviors. www.power.com Figure 2. High Creepage, Safety-Compliant InSOP-24D Package. Output Power Table Product 3 725 V MOSFET INN3672C INN3673C INN3674C INN3675C INN3676C INN3677C 750 V PowiGaN Switch INN3678C INN3679C INN3670C 900 V MOSFET INN3692C INN3694C INN3696C 900 V PowiGaN Switch INN3697C INN3699C INN3690C 1700 V Switch INN3647C INN3649C Peak or Open Frame1,2 Peak or Open Frame1,2 230 VAC ± 15% 12 W 15 W 25 W 30 W 40 W 45 W 230 VAC ± 15% 75 W 85 W 100 W 230 VAC ±15% 12 W 25 W 35 W 230 VAC ±15% 55 W 85 W 100 W 85 ‒ 670 VAC 45 W 65 W 85 ‒ 265 VAC 10 W 12 W 20 W 25 W 36 W 40 W 85 ‒ 265 VAC 65 W 75 W 85 W 85 ‒ 440 VAC 10 W 20 W 30 W 85 ‒ 400 VAC 50 W 75 W 85 W 200 ‒ 1000 VDC 50 W 70 W Table 1. Output Power Table. Notes: 1. Minimum continuous power in a typical non-ventilated enclosed adapter measured at 40 °C ambient. Max output power is dependent on the design. With condition that package temperature must be < 125 °C. 2. Minimum peak power capability. 3. Package: InSOP-24D. 4. UL1577, TUV, CQC and DIN EN IEC 60747-17 are pending for INN369xC devices. While DIN IEC 60747-17 is pending for INN364xC devices. This Product is Covered by Patents and/or Pending Patent Applications. March 2023 InnoSwitch3-EP DRAIN (D) UNDER/OVER INPUT VOLTAGE (V) PRIMARY BYPASS (BPP) PRIMARY BYPASS REGULATOR ENABLE ENABLE FAULT AUTO-RESTART COUNTER LINE INTERFACE GATE RESET BPP/UV PRIMARY BYPASS PIN CAPACITOR SELECT AND CURRENT LIMIT PRIM-CLK UV/OV OSCILLATOR/ TIMERS GATE tON(MAX) JITTER FAULT OV/UV VSHUNT VBP+ From Secondary Controller SecPulse DRIVER Q S Q R PRIM/SEC tOFF(BLOCK) PRIM-CLK ILIM + PRIMARY OVP LATCH/ AUTO-RESTART LATCH-OFF/ AUTO-RESTART - RECEIVER CONTROLLER SECLATCH BPP/UV LEB VILIM - VILIM PRIM/SEC SecREQ BPP IS + GATE GATE Power Switch PRIMARY BYPASS PIN UNDERVOLTAGE tOFF(BLOCK) THERMAL SHUTDOWN SenseFET BPP/UV tON(MAX) PI-8044h-111219 SOURCE (S) Figure 3. Primary Controller Block Diagram. FORWARD (FW) SYNC RECTIFIER DRIVE (SR) VOUT SR CONTROL INH VO VO REGULATOR VBPS FORWARD ENABLE SR SECONDARY BYPASS (BPS) BPSUV + - DETECTOR + S Q R Q VBPS(UVLO)(TH) SR THRESHOLD QR HANDSHAKE/ AUTO-RESTART INH DCM CONTROL - QR TsMAX VREF CABLE DROP COMPENSATION/ FEEDBACK COMPENSATION SR + tOFF(MIN) OSCILLATOR/ TIMER FEEDBACK (FB) + INH FEEDBACK DRIVER SECONDARY LATCH/ AUTO-RESTART - IS THRESHOLD tSECINH(MAX) tSS(RAMP) SECONDARY GROUND (GND) ISENSE (IS) PI-8045l-101619 Figure 4. Secondary Controller Block Diagram. 2 www.power.com Rev. S 03/23 InnoSwitch3-EP Pin Functional Description ISENSE (IS) Pin (Pin 1) Connection to the power supply output terminals. An external current sense resistor should be connected between this and the GND pin. If current regulation/accurate over-current protection is not required, this pin should be tied to the GND pin. SECONDARY GROUND (GND) (Pin 2) GND for the secondary IC. Note this is not the power supply output GND due to the presence of the sense resistor between this and the ISENSE pin. FEEDBACK (FB) Pin (Pin 3) Connection to an external resistor divider to set the power supply output voltage. V 13 BPP 14 NC 15 S 16-19 D 24 SECONDARY BYPASS (BPS) Pin (Pin 4) Connection point for an external bypass capacitor for the secondary IC supply. SYNCHRONOUS RECTIFIER DRIVE (SR) Pin (Pin 5) Gate driver for external SR FET. If no SR FET is used connect this pin to GND. OUTPUT VOLTAGE (VOUT) Pin (Pin 6) Connected directly to the output voltage, to provide current for the controller on the secondary-side and provide secondary protection. FORWARD (FWD) Pin (Pin 7) The connection point to the switching node of the transformer output winding providing information on primary switch timing. Provides power for the secondary-side controller when VOUT is below threshold. NC Pin (Pin 8-12) Leave open. Should not be connected to any other pins. UNDER/OVER INPUT VOLTAGE (V) Pin (Pin 13) A high-voltage pin connected to the AC or DC side of the input bridge for detecting undervoltage and overvoltage conditions at the power supply input. This pin should be tied to SOURCE pin to disable UV/OV protection. PRIMARY BYPASS (BPP) Pin (Pin 14) The connection point for an external bypass capacitor for the primary-side supply. This is also the ILIM selection pin for choosing standard ILIM or ILIM+1. NC Pin (Pin 15) Leave open or connect to SOURCE pin or BPP pin. SOURCE (S) Pin (Pin 16-19) These pins are the power switch source connection. Also ground reference for primary BYPASS pin. DRAIN (D) Pin (Pin 24) Power switch drain connection. 12 NC 11 NC 10 NC 9 NC 8 NC 7 FWD 6 VOUT 5 SR 4 BPS 3 FB 2 GND 1 IS PI-7877-022216 Figure 5. Pin Configuration. InnoSwitch3-EP Functional Description The InnoSwitch3-EP combines a high-voltage power switch, along with both primary-side and secondary-side controllers in one device. The architecture incorporates a novel inductive coupling feedback scheme (FluxLink) using the package lead frame and bond wires to provide a safe, reliable, and cost-effective means to transmit accurate, output voltage and current information from the secondary controller to the primary controller. The primary controller on InnoSwitch3-EP is a Quasi-Resonant (QR) flyback controller that has the ability to operate in continuous conduction mode (CCM), boundary mode (CrM) and discontinuous conduction mode (DCM). The controller uses both variable frequency and variable current control schemes. The primary controller consists of a frequency jitter oscillator, a receiver circuit magnetically coupled to the secondary controller, a current limit controller, 5 V regulator on the PRIMARY BYPASS pin, audible noise reduction engine for light load operation, bypass overvoltage detection circuit, a lossless input line sensing circuit, current limit selection circuitry, over-temperature protection, leading edge blanking, secondary output diode / SR FET short protection circuit and a power switch. The InnoSwitch3-EP secondary controller consists of a transmitter circuit that is magnetically coupled to the primary receiver, a constant voltage (CV) and a constant current (CC) control circuit, a 4.4 V regulator on the SECONDARY BYPASS pin, synchronous rectifier FET driver, QR mode circuit, oscillator and timing circuit, and numerous integrated protection features. Figure 3 and Figure 4 show the functional block diagrams of the primary and secondary controller, highlighting the most important features. 3 www.power.com Rev. S 03/23 InnoSwitch3-EP Primary Controller PRIMARY BYPASS Pin Regulator The PRIMARY BYPASS pin has an internal regulator that charges the PRIMARY BYPASS pin capacitor to VBPP by drawing current from the DRAIN pin whenever the power switch is off. The PRIMARY BYPASS pin is the internal supply voltage node. When the power switch is on, the device operates from the energy stored in the PRIMARY BYPASS pin capacitor. In addition, a shunt regulator clamps the PRIMARY BYPASS pin voltage to VSHUNT when current is provided to the PRIMARY BYPASS pin through an external resistor. This allows the InnoSwitch3-EP to be powered externally through a bias winding, decreasing the no-load consumption to less than 30 mW in a 5 V output design. Primary Bypass ILIM Programming InnoSwitch3-EP ICs allows the user to adjust current limit (ILIM) settings through the selection of the PRIMARY BYPASS pin capacitor value. A ceramic capacitor can be used. There are 2 selectable capacitor sizes - 0.47 mF and 4.7 mF for setting standard and increased ILIM settings respectively. Primary Bypass Undervoltage Threshold The PRIMARY BYPASS pin undervoltage circuitry disables the power switch when the PRIMARY BYPASS pin voltage drops below ~4.5 V (VBPP - VBP(H)) in steady-state operation. Once the PRIMARY BYPASS pin voltage falls below this threshold, it must rise to VSHUNT to re-enable turn-on of the power switch. Primary Bypass Output Overvoltage Function The PRIMARY BYPASS pin has a latching/auto-restart OV protection feature depending on H Code. A Zener diode in parallel with the resistor in series with the PRIMARY BYPASS pin capacitor is typically used to detect an overvoltage on the primary bias winding and activate the protection mechanism. In the event that the current into the PRIMARY BYPASS pin exceeds ISD, the device will latch-off or disable the power switch switching for a time t AR(OFF), after which time the controller will restart and attempt to return to regulation (see Secondary Fault Response in the Feature Code Addendum). VOUT OV protection is also included as an integrated feature on the secondary controller (see Output Voltage Protection). Over-Temperature Protection The thermal shutdown circuitry senses the primary Switch die temperature. The threshold is set to TSD with either a hysteretic or latch-off response depending on H Code. Hysteretic response: If the die temperature rises above the threshold, the power switch is disabled and remains disabled until the die temperature falls by TSD(H) at which point switching is re-enabled. A large amount of hysteresis is provided to prevent over-heating of the PCB due to a continuous fault condition. Latch-off response: If the die temperature rises above the threshold the power switch is disabled. The latching condition is reset by bringing the PRIMARY BYPASS pin below VBPP(RESET) or by going below the UNDER/OVER INPUT VOLTAGE pin UV (IUV-) threshold. PI-8205-120516 1.05 Normalized ILIM (A) InnoSwitch3-EP has variable frequency QR controller plus CCM/CrM/ DCM operation for enhanced efficiency and extended output power capability. 1.0 0.95 0.9 0.85 0.8 0.75 30 40 50 60 70 80 90 100 Steady-State Switching Frequency (kHz) Figure 6. Normalized Primary Current vs. Frequency. Current Limit Operation The primary-side controller has a current limit threshold ramp that is linearly decreasing to the time from the end of the previous primary switching cycle (i.e. from the time the primary Switch turns off at the end of a switching cycle). This characteristic produces a primary current limit that increases as the switching frequency (load) increases (Figure 6). This algorithm enables the most efficient use of the primary switch with the benefit that this algorithm responds to digital feedback information immediately when a feedback switching cycle request is received. At high load, switching cycles have a maximum current approaching 100% ILIM. This gradually reduces to 30% of the full current limit as load decreases. Once 30% current limit is reached, there is no further reduction in current limit (since this is low enough to avoid audible noise). The time between switching cycles will continue to increase as load reduces. Jitter The normalized current limit is modulated between 100% and 95% at a modulation frequency of fM. This results in a frequency jitter of ~7 kHz with average frequency of ~100 kHz. Auto-Restart In the event a fault condition occurs (such as an output overload, output short-circuit, or external component/pin fault), the InnoSwitch3-EP enters auto-restart (AR) or latches off. The latching condition is reset by bringing the PRIMARY BYPASS pin below ~3 V or by going below the UNDER/OVER INPUT VOLTAGE pin UV (IUV-) threshold. In auto-restart, switching of the power switch is disabled for t AR(OFF). There are 2 ways to enter auto-restart: 1. Continuous secondary requests at above the overload detection frequency fOVL (~110 kHz) for longer than 82 ms (tAR). 2. No requests for switching cycles from the secondary for >tAR(SK). The second is included to ensure that if communication is lost, the primary tries to restart. Although this should never be the case in normal operation, it can be useful when system ESD events (for example) causes a loss of communication due to noise disturbing the secondary controller. The issue is resolved when the primary restarts after an auto-restart off-time. 4 www.power.com Rev. S 03/23 InnoSwitch3-EP The auto-restart is reset as soon as an AC reset occurs. SOA Protection In the event that there are two consecutive cycles where the 110% ILIM is reached within ~500 ns (the blanking time + current limit delay time) (including leading edge current spike), the controller will skip 2.5 cycles or ~25 ms (based on full frequency of 100 kHz). This provides sufficient time for the transformer to reset with large capacitive loads without extending the start-up time. Secondary Rectifier/SR Switch Short Protection (SRS) In the event that the output diode or SR FET is short-circuited before or during the primary conduction cycle, the drain current (prior to the end of the leading edge blanking time) can be much higher than the maximum current limit threshold. If the controller turns the highvoltage power switch off, the resulting peak drain voltage could exceed the rated BVDSS of the device, resulting in catastrophic failure even with minimum on-time. To address this issue, the controller features a circuit that reacts when the drain current exceeds the maximum current limit threshold prior to the end of leading-edge blanking time. If the leading-edge current exceeds current limit within a cycle (200 ns), the primary controller will trigger a 30 ms off-time event. SOA mode is triggered if there are two consecutive cycles above current limit within tLES (~500 ns). SRS mode also triggers t AR(OFF)SH off-time, if the current limit is reached within 200 ns after a 30 ms off-time. SRS protection is not available on PowiGaN devices INN3678C, INN3679C and INN3670C. Input Line Voltage Monitoring The UNDER/OVER INPUT VOLTAGE pin is used for input undervoltage and overvoltage sensing and protection. A sense resistor is tied between the high-voltage DC bulk capacitor after the bridge (or to the AC side of the bridge rectifier for fast AC reset) and the UNDER/OVER INPUT VOLTAGE pin to enable this functionality. This function can be disabled by shorting the UNDER/ OVER INPUT VOLTAGE pin to SOURCE pin. At power-up, after the primary bypass capacitor is charged and the ILIM state is latched, and prior to switching, the state of the UNDER/ OVER INPUT VOLTAGE pin is checked to confirm that it is above the brown-in and below the overvoltage shutdown thresholds. In normal operation, if the UNDER/OVER INPUT VOLTAGE pin current falls below the brown-out threshold and remains below brown-out for longer than tUV-, the controller enters auto-restart. Switching will only resume once the UNDER/OVER INPUT VOLTAGE pin current is above the brown-in threshold. In the event that the UNDER/OVER INPUT VOLTAGE pin current is above the overvoltage threshold, the controller will also enter auto-restart. Again, switching will only resume once the UNDER/ OVER INPUT VOLTAGE pin current has returned to within its normal operating range. The input line UV/OV function makes use of an internal high-voltage Switch on the UNDER/OVER INPUT VOLTAGE pin to reduce power consumption. If the cycle off-time tOFF is greater than 50 ms, the internal high-voltage Switch will disconnect the external sense resistor from the internal IC to eliminate current drawn through the sense resistor. The line sensing function will activate again at the beginning of the next switching cycle. P: Primary Chip S: Secondary Chip Start P: Powered Up, Switching S: Powering Up P: Auto-Restart S: Powering Up tAR(OFF) S: Has powered up within tAR No P: Goes to Auto-Restart Off S: Bypass Discharging Yes tAR P: Switching S: Sends Handshaking Pulses P: Has Received Handshaking Pulses No P: Continuous Switching S: Doesn’t Take Control No P: Not Switching S: Doesn’t Take Control Yes P: Stops Switching, Hands Over Control to Secondary S: Has Taken Control? Yes End of Handshaking, Secondary Control Mode PI-7416a-102116 Figure 7. Primary-Secondary Handshake Flowchart. Primary-Secondary Handshake At start-up, the primary-side initially switches without any feedback information (this is very similar to the operation of a standard TOPSwitch™, TinySwitch™ or LinkSwitch™ controllers). If no feedback signals are received during the auto-restart on-time (t AR), the primary goes into auto-restart mode. Under normal conditions, the secondary controller will power-up via the FORWARD pin or from the OUTPUT VOLTAGE pin and take over control. From this point onwards the secondary controls switching. If the primary controller stops switching or does not respond to cycle requests from the secondary during normal operation (when the secondary has control), the handshake protocol is initiated to ensure that the secondary is ready to assume control once the primary begins to switch again. An additional handshake is also triggered if the secondary detects that the primary is providing more cycles than were requested. 5 www.power.com Rev. S 03/23 InnoSwitch3-EP The most likely event that could require an additional handshake is when the primary stops switching as the result of a momentary line brown-out event. When the primary resumes operation, it will default to a start-up condition and attempt to detect handshake pulses from the secondary. If the secondary does not detect that the primary responds to switching requests for 8 consecutive cycles, or if the secondary detects that the primary is switching without cycle requests for 4 or more consecutive cycles, the secondary controller will initiate a second handshake sequence. This provides additional protection against cross-conduction of the SR FET while the primary is switching. This protection mode also prevents an output overvoltage condition in the event that the primary is reset while the secondary is still in control. Wait and Listen When the primary resumes switching after initial power-up recovery from an input line voltage fault (UV or OV) or an auto-restart event, it will assume control and require a successful handshake to relinquish control to the secondary controller. As an additional safety measure the primary will pause for an auto-restart on-time period, t AR (~82 ms), before switching. During this “wait” time, the primary will “listen” for secondary requests. If it sees two consecutive secondary requests, separated by ~30 ms, the primary will infer secondary control and begin switching in slave mode. If no pulses occurs during the t AR “wait” period, the primary will begin switching under primary control until handshake pulses are received. Audible Noise Reduction Engine The InnoSwitch3-EP features an active audible noise reduction mode whereby the controller (via a “frequency skipping” mode of operation) avoids the resonant band (where the mechanical structure of the power supply is most likely to resonate − increasing noise amplitude) between 5 kHz and 12 kHz - 200 ms and 83 ms period respectively. If a secondary controller switch request occurs within this time window from the last conduction cycle, the gate drive to the power switch is inhibited. Secondary Controller As shown in the block diagram in Figure 4, the IC is powered by a 4.4 V (VBPS) regulator which is supplied by either VOUT or FWD. The SECONDARY BYPASS pin is connected to an external decoupling capacitor and fed internally from the regulator block. The FORWARD pin also connects to the negative edge detection block used for both handshaking and timing to turn on the SR FET connected to the SYNCHRONOUS RECTIFIER DRIVE pin. The FORWARD pin voltage is used to determine when to turn off the SR FET in discontinuous conduction mode operation. This is when the voltage across the RDS(ON) of the SR FET drops below zero volts. In continuous conduction mode (CCM) the SR FET is turned off when the feedback pulse is sent to the primary to demand the next switching cycle, providing excellent synchronous operation, free of any overlap for the FET turn-off. The mid-point of an external resistor divider network between the OUTPUT VOLTAGE and SECONDARY GROUND pins is tied to the FEEDBACK pin to regulate the output voltage. The internal voltage comparator reference voltage is VFB (1.265 V). The external current sense resistor connected between ISENSE and SECONDARY GROUND pins is used to regulate the output current in constant current regulation mode. Minimum Off-Time The secondary controller initiates a cycle request using the inductiveconnection to the primary. The maximum frequency of secondarycycle requests is limited by a minimum cycle off-time of tOFF(MIN). This is in order to ensure that there is sufficient reset time after primary conduction to deliver energy to the load. Maximum Switching Frequency The maximum switch-request frequency of the secondary controller is fSREQ. Frequency Soft-Start At start-up the primary controller is limited to a maximum switching frequency of fSW and 75% of the maximum programmed current limit at the switch-request frequency of 100 kHz. The secondary controller temporarily inhibits the FEEDBACK short protection threshold (VFB(OFF)) until the end of the soft-start (tSS(RAMP)) time. After hand-shake is completed the secondary controller linearly ramps up the switching frequency from fSW to fSREQ over the tSS(RAMP) time period. In the event of a short-circuit or overload at start-up, the device will move directly into CC (constant-current) mode. The device will go into auto-restart (AR), if the output voltage does not rise above the VFB(AR) threshold before the expiration of the soft-start timer (tSS(RAMP)) after handshake has occurred. The secondary controller enables the FEEDBACK pin-short protection mode (VFB(OFF)) at the end of the tSS(RAMP) time period. If the output short maintains the FEEDBACK pin below the short-circuit threshold, the secondary will stop requesting pulses triggering an auto-restart cycle. If the output voltage reaches regulation within the tSS(RAMP) time period, the frequency ramp is immediately aborted and the secondary controller is permitted to go full frequency. This will allow the controller to maintain regulation in the event of a sudden transient loading soon after regulation is achieved. The frequency ramp will only be aborted if quasi-resonant-detection programming has already occurred. Maximum Secondary Inhibit Period Secondary requests to initiate primary switching are inhibited to maintain operation below maximum frequency and ensure minimum off-time. Besides these constraints, secondary-cycle requests are also inhibited during the “ON” time cycle of the primary switch (time between the cycle request and detection of FORWARD pin falling edge). The maximum time-out in the event that a FORWARD pin falling edge is not detected after a cycle requested is ~30 ms. Output Voltage Protection In the event that the sensed voltage on the FEEDBACK pin is 2% higher than the regulation threshold, a bleed current of ~2.5 mA (3 mA max) is applied on the OUTPUT VOLTAGE pin (weak bleed). This bleed current increases to ~200 mA (strong bleed) in the event that the FEEDBACK pin voltage is raised beyond ~10% of the internal FEEDBACK pin reference voltage. The current sink on the OUTPUT VOLTAGE pin is intended to discharge the output voltage after momentary overshoot events. The secondary does not relinquish control to the primary during this mode of operation. If the voltage on the FEEDBACK pin is sensed to be 20% higher than the regulation threshold, a command is sent to the primary to either latch-off or begin an auto-restart sequence (see Secondary Fault Response in Feature Code Addendum). This integrated VOUT OVP can be used independently from the primary sensed OVP or in conjunction. 6 www.power.com Rev. S 03/23 InnoSwitch3-EP During normal operation, the secondary will stop requesting pulses from the primary to initiate an auto-restart cycle when the FEEDBACK pin voltage falls below the VFB(OFF) threshold. The deglitch filter on the protection mode is on for less than ~10 ms. By this mechanism, the secondary will relinquish control after detecting that the FEEDBACK pin is shorted to ground. FORWARD Pin Voltage Auto-Restart Thresholds The FEEDBACK pin includes a comparator to detect when the feedback voltage falls below VFB(AR), for a duration exceeding tFB(AR). The secondary controller will relinquish control when this fault condition is detected. This threshold is meant to limit the range of constant current (CC) operation and is included to support high power charger applications. SECONDARY BYPASS Pin Overvoltage Protection The InnoSwitch3-EP secondary controller features a SECONDARY BYPASS pin OV feature similar to the PRIMARY BYPASS pin OV feature. When the secondary is in control, in the event that the SECONDARY BYPASS pin current exceeds IBPS(SD) (~7 mA) the secondary will send a command to the primary to initiate an auto-restart off-time (t AR(OFF)). Output Constant Current Regulation/Output Over-Current Protection The InnoSwitch3-EP regulates the output current through an external current sense resistor between the ISENSE and SECONDARY GROUND pins and also controls output power in conjunction with the output voltage sensed on the OUTPUT VOLTAGE pin. If constant current regulation/accurate over-current protection is not required, the ISENSE pin must be tied to the SECONDARY GROUND pin. Also see ‘Peak Power Delivery’ section. SR Disable Protection In each cycle SR is only engaged if a set cycle was requested by the secondary controller and the negative edge is detected on the FORWARD pin. In the event that the voltage on the ISENSE pin exceeds approximately 3 times the CC threshold, the SR FET drive is disabled until the surge current has diminished to nominal levels. PI-8147-102816 FEEDBACK Pin Short Detection If the sensed FEEDBACK pin voltage is below VFB(OFF) at start-up, the secondary controller will complete the handshake to take control of the primary complete tSS(RAMP) and will stop requesting cycles to initiate auto-restart (no cycle requests made to primary for longer than t AR(SK) second triggers auto-restart). Request Window Output Voltage Primary VDS Time Time Figure 8. Intelligent Quasi-Resonant Mode Switching. 7 www.power.com Rev. S 03/23 InnoSwitch3-EP SR Static Pull-Down To ensure that the SR gate is held low when the secondary is not in control, the SYNCHRONOUS RECTIFIER DRIVE pin has a nominally “ON” device to pull the pin low and reduce any voltage on the SR gate due to capacitive coupling from the FORWARD pin. Open SR Protection In order to protect against an open SYNCHRONOUS RECTIFIER DRIVE pin system fault the secondary controller has a protection mode to ensure the SYNCHRONOUS RECTIFIER DRIVE pin is connected to an external FET. If the external capacitance on the SYNCHRONOUS RECTIFIER DRIVE pin is below 100 pF, the device will assume the SYNCHRONOUS RECTIFIER DRIVE pin is “open” and there is no FET to drive. If the pin capacitance detected is above 100 pF, the controller will assume an SR FET is connected. If there is an external current sense resistor on the IS pin, the InnoSwitch has options to set the overload response in two different ways. If the device is configured to have the FEEDBACK pin auto-restart enabled, once the load current reaches the current limit threshold set by the IS pin resistor, the output voltage will fold back and autorestart will occur once the output voltage falls below the AR threshold for a time period exceeding the AR timer. If the device is configured for overload response, once the load current exceeds the current sense threshold the output voltage does not fold back. The auto-restart timer will begin and auto-restart occurs if the load current remains higher than the current sense threshold for a time period exceeding the AR timer. In the event the SYNCHRONOUS RECTIFIER DRIVE pin is detected to be open, the secondary controller will stop requesting pulses from the primary to initiate auto-restart. Intelligent Quasi-Resonant Mode Switching In order to improve conversion efficiency and reduce switching losses, the InnoSwitch3-EP features a means to force switching when the voltage across the primary switch is near its minimum voltage when the converter operates in discontinuous conduction mode (DCM). This mode of operation is automatically engaged in DCM and disabled once the converter moves to continuous-conduction mode (CCM). Rather than detecting the magnetizing ring valley on the primaryside, the peak voltage of the FORWARD pin voltage as it rises above the output voltage level is used to gate secondary requests to initiate the switch “ON” cycle in the primary controller. The secondary controller detects when the controller enters in discontinuous-mode and opens secondary cycle request windows corresponding to minimum switching voltage across the primary power switch. Quasi-Resonant (QR) mode is enabled for 20 ms after DCM is detected or when ring amplitude (pk-pk) >2 V. Afterwards, QR switching is disabled, at which point switching may occur at any time a secondary request is initiated. The secondary controller includes blanking of ~1 ms to prevent false detection of primary “ON” cycle when the FORWARD pin rings below ground. See Figure 8. Peak Power Delivery Output overload response depends on whether the IS pin is shorted to ground or the design includes a current sense resistor to set the overload threshold. No CC with Overload Response AR when Load > ISVTH for t > tIS(AR) Output Voltage If the SYNCHRONOUS RECTIFIER DRIVE pin is tied to ground at start-up, the SR drive function is disabled and the open SYNCHRONOUS RECTIFIER DRIVE pin protection mode is also disabled. Constant Current when VFB(AR) is enabled AR when VFB < VFB(AR) for t(FBAR) Load Current ISVTH Threshold PI-8962-040819 Figure 9. Current Sense Resistor in a Design. The two cases where a current sense resistor is included in the design are shown in the Figure 9 above. If the IS pin is shorted to the GND pin, the overload response heavily depends on the operating conditions. If the device is configured to have feedback auto-restart enabled (VFB(AR)), auto-restart will occur if the output voltage droops below the auto-restart threshold for longer than the auto-restart timer (tFB(AR)). Otherwise, the auto-restart occurs if the primary switches above the overload frequency limit (fOVL) for longer than the auto-restart on-time (t AR). 8 www.power.com Rev. S 03/23 InnoSwitch3-EP Applications Example C10 470 pF 250 VAC 2 VR2 SMAZ8V2-13-F 8.2 V FL1 C21 R25 1 nF 30 Ω 200 V 1/8 W C4 1000 pF 630 V R3 2 MΩ 1% BR1 DF08S 800 V R22 68 Ω R4 1.8 MΩ 1% C3 10 µF 400 V Q1 AO6420 3 T1 EE1621 O R6 6.2 kΩ 1/10 W C5 22 µF 50 V C7 2.2 µF 25 V VR1 MMSZ5231B-7-F D3 BAV21WS-7-F R13 33.2 kΩ 1% 1/16 W R9 47 Ω 1/10 W D V BPS D7 DFLR1200-7 N L1 330 µH C23 2.2 nF 50 V 5 NC S BPP C6 4.7 µF 16 V FB InnoSwitch3-EP U1 INN3672C-H602 R27 1.2 MΩ 1% 1/16 W 12 V RTN 5 V, 0.3 A L3 10 µH C12 2.2 µF 25 V C8 330 pF 50 V CONTROL R26 36 Ω 1/10 W R16 133 kΩ 1% 1/16 W C14 2.2 µF 25 V GND 90 - 265 VAC R29 100 Ω 1/10 W C18 560 µF 6.3 V VO L t C24 2.2 nF 50 V R24 C22 62 Ω 1 nF 1/8 W 200 V D1 DFLR1600-7 600 V FWD RT1 10 Ω 6 4 R30 100 Ω 1/10 W Q2 AO4486 SR C2 10 µF 400 V F1 1A 1 R8 200 kΩ C19 680 µF 16 V FL2 12 V, 0.7 A L2 10 µH R12 0.02 Ω 1% IS 5V PI-8374-012919 RTN Figure 10. Schematic DER-611, 5 V, 0.3 A and 12 V, 0.7 A for HVAC (Heating, Ventilation and Air-Conditioning) Application. The circuit shown in Figure 10 is a low cost 5 V, 0.3 A and 12 V, 0.7 A dual output power supply using INN3672C. This dual output design features high efficient design satisfying cross regulation requirement without a post-regulator. Bridge rectifier BR1 rectifies the AC input supply. Capacitors C2 and C3 provide filtering of the rectified AC input and together with inductor L1 form a pi-filter to attenuate differential mode EMI. Y capacitor C10 connected between the power supply output and input help reduce common mode EMI. Thermistor RT1 limits the inrush current when the power supply is connected to the input AC supply. Input fuse F1 provides protection against excess input current resulting from catastrophic failure of any of the components in the power supply. One end of the transformer primary is connected to the rectified DC bus; the other is connected to the drain terminal of the Switch inside the InnoSwitch3-EP IC (U1). A low-cost RCD clamp formed by diode D1, resistors R22, R8, and capacitor C4 limits the peak drain voltage of U1 at the instant of turn-off of the Switch inside U1. The clamp helps to dissipate the energy stored in the leakage reactance of transformer T1. The InnoSwitch3-EP IC is self-starting, using an internal high-voltage current source to charge the PRIMARY BYPASS pin capacitor (C6) when AC is first applied. During normal operation the primary-side block is powered from an auxiliary winding on the transformer T1. Output of the auxiliary (or bias) winding is rectified using diode D7 and filtered using capacitor C5. Resistor R6 limits the current being supplied to the PRIMARY BYPASS pin of InnoSwitch3-EP IC (U1). The latch-off/auto-restart primary-side overvoltage protection is obtained using Zener diode VR1 with current limiting resistor R26. The secondary-side controller of the InnoSwitch3-EP IC provides output voltage sensing, output current sensing and drive to a Switch providing synchronous rectification. The 5 V secondary of the transformer is rectified by SR FET Q1 and filtered by capacitor C18. High frequency ringing during switching transients that would otherwise create radiated EMI is reduced via a snubber (resistor R24 and capacitor C22). The 12 V secondary of the transformer is rectified by SR FET Q2 and filtered by capacitor C19. High frequency ringing during switching transients that would otherwise create radiated EMI is reduced via a snubber (resistor R25 and capacitor C21). Synchronous rectifications (SR) are provided by Switches Q1 and Q2. Q1 and Q2 are turned on by the secondary-side controller inside IC U1, based on the winding voltage sensed via resistor R9 and fed into the FORWARD pin of the IC. In continuous conduction mode of operation, the Switch is turned off just prior to the secondary-side’s commanding a new switching cycle from the primary. In discontinuous conduction mode of operation, the power switch is turned off when the voltage drop across the Switch falls below 0 V. Secondary-side control of the primary-side power switch avoids any possibility of cross conduction of the two switches and provides extremely reliable synchronous rectification. The secondary-side of the IC is self-powered from either the secondary winding forward voltage or the output voltage. Capacitor C7 connected to the SECONDARY BYPASS pin of InnoSwitch3-EP IC U1, provides decoupling for the internal circuitry. Total output current is sensed by R12 between the IS and GROUND pins with a threshold of approximately 35 mV to reduce losses. Once the current sense threshold is exceeded the device adjusts the number of switch pulses to maintain a fixed output current. 9 www.power.com Rev. S 03/23 InnoSwitch3-EP The output voltages are sensed via resistor divider R13, R16, and R27, and output voltages are regulated so as to achieve a voltage of 1.265 V on the FEEDBACK pin. The 12 V phase boost circuit, R30 and C24, in parallel with 12 V feedback resistor, R27, and 5 V phase boost circuit, R29 and C23, in parallel with 5 V feedback resistor, R16, reduce the output voltage ripples. Capacitor C8 provides noise filtering of the signal at the FEEDBACK pin. Zener VR2 was added for tighter cross-regulation to limit the 12 V output when it is unloaded. Resistors R3 and R4 provide line voltage sensing and provide a current to U1, which is proportional to the DC voltage across capacitor C3. At approximately 100 VDC, the current through these resistors exceeds the line undervoltage threshold, which results in enabling of U1. At approximately 435 VDC, the current through these resistors exceeds the line over voltage threshold, which results in disabling of U1. 10 www.power.com Rev. S 03/23 InnoSwitch3-EP C3 680 pF 250 VAC 2 C4 2.2 nF 630 V J1 BR1 GBL06 600 V F1 3.15 A R5 20 Ω R7 680 kΩ R6 20 Ω J3 FL1 D4 BAV19WS 100 V R3 2.00 MΩ 1% R4 1.80 MΩ 1% R11 10 Ω FL2 C9 330 µF 25 V C8 330 µF 25 V 3 C7 1 nF 200 V R16 11.5 kΩ 1% 1/10 W Q1 AON6220 D1 DFLR1800-7 R15 169 kΩ 1% 1/16 W C13 330 pF 100 V 6 4 3 D2 R2 1 MΩ J2 L2 04291-T231 18 mH C2 100 µF 400 V R8 3 kΩ 1/10 W T1 EQ25 R9 47 Ω R12 47 Ω 1/10 W C15 10 µF 35 V D3 BAV19WS 100 V C16 1 µF 100 V C11 2.2 µF 25 V D V BPS 2 VO L1 4 250 µH 1 SR 3 CAPZero-2 U2 CAP200DG C1 330 nF 275 VAC 4 FWD 2 D1 VR1 MMSZ5242B-7-F 1 90 - 265 VAC C10 2.2 µF 25 V D2 BAV3004WS-7 300 V CONTROL S C5 6.8 µF 63 V BPP C6 4.7 µF 16 V C12 1000 pF 50 V GND R1 1 MΩ R14 0.009 Ω 1% 1/2 W FB InnoSwitch3-EP U1 INN3679C-H606 IS R13 0.0 Ω 1/10 W J4 PI-8770b-012720 Figure 11. 20 V, 3.25 A Notebook Adapter. The circuit shown in Figure 11 is a 20 V, 3.25 A adapter using INN3679C. This design is DOE Level 6 and EC CoC 5 compliant. Fuse F1 isolates the circuit and provides protection from component failure, and the common mode choke L1 and L2 with capacitor C1 attenuation for EMI. Bridge rectifier BR1 rectifies the AC line voltage and provides a full wave rectified DC across the filter capacitor C2. Capacitor C3 is used to mitigate the common mode EMI. Resistors R1 and R2 along with U2 discharges capacitor C1 when the power supply is disconnected from AC mains. One end of the transformer (T1) primary is connected to the rectified DC bus; the other is connected to the drain terminal of the switch inside the InnoSwitch3-EP IC (U1). Resistors R3 and R4 provide input voltage sense protection for undervoltage and overvoltage conditions. A low-cost RCD clamp formed by diode D1, resistors R5, R6, and R7, and capacitor C4 limits the peak drain voltage of U1 at the instant of turn off of the switch inside U1. The clamp helps to dissipate the energy stored in the leakage reactance of transformer T1. The IC is self-starting, using an internal high-voltage current source to charge the BPP pin capacitor (C6) when AC is first applied. During normal operation the primary-side block is powered from an auxiliary winding on the transformer T1. Output of the auxiliary (or bias) winding is rectified using diode D2 and filtered using capacitor C5. Resistor R8 limits the current being supplied to the BPP pin of the InnoSwitch3-EP IC (U1). Output regulation is achieved using ramp time modulation control, the frequency and ILIM of switching cycles are adjusted based on the output load. At high load, most switching cycles are enabled which have high value of ILIM in the selected ILIM range, and at light load or no-load most cycles are disabled and the ones enabled have low value of ILIM in the selected ILIM range. Once a cycle is enabled, the switch will remain on until the primary current ramps to the device current limit for the specific operating state. Zener diode VR1 along with R9 and D3 offers primary sensed output overvoltage protection. In a flyback converter, output of the auxiliary winding tracks the output voltage of the converter. In case of overvoltage at output of the converter, the auxiliary winding voltage increases and causes breakdown of VR1 which then causes a current to flow into the BPP pin of InnoSwitch3-EP IC U1. If the current flowing into the BPP pin increases above the ISD threshold, the U1 controller will latch-off and prevent any further increase in output voltage. The secondary-side of the InnoSwitch3-EP IC provides output voltage, output current sensing and drive to a MOSFET providing synchronous rectification. The secondary of the transformer is rectified by SR FET Q1 and filtered by capacitors C8 and C9. Capacitors C15 and C17 are used to reduce the high frequency output voltage ripple. High frequency ringing during switching transients that would otherwise create radiated EMI is reduced via a RCD snubber R11, C7 and D4. Diode D4 was used to minimize the dissipation in resistor R11. The gate of Q1 is turned on by secondary-side controller inside IC U1, based on the winding voltage sensed via resistor R12 and fed into the FWD pin of the IC. In continuous conduction mode of operation, the MOSFET is turned off just prior to the secondary-side commanding a new switching cycle from the primary. In discontinuous mode of operation, the power switch is turned off when the voltage drop across the MOSFET falls below a threshold of approximately VSR(TH) mV. Secondary-side control of the primary-side power switch avoids any possibility of cross conduction of the two switches and provides extremely reliable synchronous rectification. The secondary-side of the IC U1 is self-powered from either the secondary winding forward voltage or the output voltage. Capacitor C10 connected to the BPS pin of IC U1 provides decoupling for the internal circuitry. Capacitor C11 provides decoupling for the VO pin. Below the CC threshold, the device operates in constant voltage mode. During constant voltage mode operation, output voltage regulation is achieved through sensing the output voltage via divider resistors R15 and R16. The voltage across R16 is fed into the FB pin with an internal reference voltage threshold of 1.265 V. Output voltage is regulated so as to achieve a voltage of 1.265 V on the FB pin. Capacitor C13 provides noise filtering of the signal at the FB pin. 11 www.power.com Rev. S 03/23 InnoSwitch3-EP During CC operation, when the output voltage falls, the device will directly power itself from the secondary winding. During the on-time of the primary-side power switch, the forward voltage that appears across the secondary winding is used to charge the decoupling capacitor C10 via resistor R12 and an internal regulator. This allows output current regulation to be maintained down to ~3.4 V. Output current is sensed by monitoring the voltage drop across resistor R14 between the IS and SECONDARY GROUND pins. A threshold of approximately 35 mV reduces losses. C12 provides filtering on the IS pin from external noise. Once the internal current sense threshold is exceeded the device regulates the number of switch pulses to maintain a fixed output current. Layout Example Keep drain and clamp loop short; keep drain components away from BPP and V pin circuitry. Y capacitor connection to the plus bulk rail on the primary-side for surge protection. Maximize source area for good heat sinking. 6.5 mm spark gap. Keep IS-GND pin sense resistor close to output capacitor and output connector. Keep ISGND pin decoupling capacitor close to the IC. Keep FEEDBACK pin decoupling capacitor close to the IC. Keep output SR FET and output filter capacitor loop short. Place forward and feedback sense resistors near the IC. Place V pin sense resistor close to the IC. Keep BPP and BPS capacitors near the IC. Maximize drain area of SR FET for good heat sinking. PCB - Bottom Side PI-9112-012820 Figure 12. PCB Layout. 12 www.power.com Rev. S 03/23 InnoSwitch3-EP Key Application Considerations Output Power Table The data sheet output power table (Table 1) represents the maximum practical continuous output power level that can be obtained under the following conditions: 1. The minimum DC input voltage is 90 V or higher for 85 VAC input, 220 V or higher for 230 VAC input or 115 VAC with a voltagedoubler. Input capacitor voltage should be sized to meet these criteria for AC input designs. 2. Efficiency assumptions depend on power level. Smallest device power level assumes efficiency >84% increasing to >89% for the largest device (for thermally constrained environment efficiency should be >92% with larger devices). 3. Transformer primary inductance tolerance of ±10%. 4. Reflected output voltage (VOR) is set to maintain KP = 0.8 at minimum input voltage for universal line and KP = 1 for high input line designs. 5. Maximum conduction losses for adapters is limited to 0.6 W, 0.8 W for open frame designs. 6. Increased current limit is selected for peak and open frame power columns and standard current limit for adapter columns. 7. The part is board mounted with SOURCE pins soldered to a sufficient area of copper and/or a heat sink to keep the SOURCE pin temperature at or below 110 °C. 8. Ambient temperature of 50 °C for open frame designs and 40 °C for sealed adapters. 9. Below a value of 1, KP is the ratio of ripple to peak primary current. To prevent reduced power delivery, due to premature termination of switching cycles, a transient KP limit of ≥0.25 is recommended. This prevents the initial current limit (IINT) from being exceeded at Switch turn-on. Primary-Side Overvoltage Protection (Latch-Off/ Auto-Restart Mode) Primary-side output overvoltage protection provided by the InnoSwitch3-EP IC uses an internal protection depending on H Code that is triggered by a threshold current of ISD into the PRIMARY BYPASS pin. In addition to an internal filter, the PRIMARY BYPASS pin capacitor forms an external filter helping noise immunity. For the bypass capacitor to be effective as a high frequency filter, the capacitor should be located as close as possible to the SOURCE and PRIMARY BYPASS pins of the device. The primary sensed OVP function can be realized by connecting a series combination of a Zener diode, a resistor and a blocking diode from the rectified and filtered bias winding voltage supply to the PRIMARY BYPASS pin. The rectified and filtered bias winding output voltage may be higher than expected (up to 1.5X or 2X the desired value) due to poor coupling of the bias winding with the output winding and the resulting ringing on the bias winding voltage waveform. It is therefore recommended that the rectified bias winding voltage be measured. This measurement should be ideally done at the lowest input voltage and with highest load on the output. This measured voltage should be used to select the components required to achieve primary sensed OVP. It is recommended that a Zener diode with a clamping voltage approximately 6 V lower than the bias winding rectified voltage at which OVP is expected to be triggered be selected. A forward voltage drop of 1 V can be assumed for the blocking diode. A small signal standard recovery diode is recommended. The blocking diode prevents any reverse current discharging the bias capacitor during start-up. Finally, the value of the series resistor required can be calculated such that a current higher than ISD will flow into the PRIMARY BYPASS pin during an output overvoltage. Reducing No-Load Consumption The InnoSwitch3-EP IC can start in self-powered mode, drawing energy from the BYPASS pin capacitor charged through an internal current source. Use of a bias winding is however required to provide supply current to the PRIMARY BYPASS pin once the InnoSwitch3-EP IC has started switching. An auxiliary (bias) winding provided on the transformer serves this purpose. A bias winding driver supply to the PRIMARY BYPASS pin enables design of power supplies with no-load power consumption less than 15 mW. Resistor R6 shown in Figure 10 should be adjusted to achieve the lowest no-load input power. Secondary-Side Overvoltage Protection (Auto-Restart Mode) The secondary-side output overvoltage protection provided by the InnoSwitch3-EP IC uses an internal auto restart circuit that is triggered by an input current exceeding a threshold of IBPS(SD) into the SECONDARY BYPASS pin. The direct output sensed OVP function can be realized by connecting a Zener diode from the output to the SECONDARY BYPASS pin. The Zener diode voltage needs to be the difference between 1.25 × VOUT and 4.4 V − the SECONDARY BYPASS pin voltage. It is necessary to add a low value resistor in series with the OVP Zener diode to limit the maximum current into the SECONDARY BYPASS pin. Selection of Components Components for InnoSwitch3-EP Primary-Side Circuit BPP Capacitor A capacitor connected from the PRIMARY BYPASS pin of the InnoSwitch3-EP IC to GND provides decoupling for the primary-side controller and also selects current limit. A 0.47 mF or 4.7 mF capacitor may be used. Though electrolytic capacitors can be used, often surface mount multi-layer ceramic capacitors are preferred for use on double sided boards as they enable placement of capacitors close to the IC. Their small size also makes it ideal for compact power supplies. At least 10 V, 0805 or larger size rated X5R or X7R dielectric capacitors are recommended to ensure that minimum capacitance requirements are met. The ceramic capacitor type designations, such as X7R, X5R from different manufacturers or different product families do not have the same voltage coefficients. It is recommended that capacitor data sheets be reviewed to ensure that the selected capacitor will not have more than 20% drop in capacitance at 5 V. Do not use Y5U or Z5U / 0603 rated MLCC due to this type of SMD ceramic capacitor has very poor voltage and temperature coefficient characteristics. Bias Winding and External Bias Circuit The internal regulator connected from the DRAIN pin of the Switch to the PRIMARY BYPASS pin of the InnoSwitch3-EP primary-side controller charges the capacitor connected to the PRIMARY BYPASS pin to achieve start-up. A bias winding should be provided on the transformer with a suitable rectifier and filter capacitor to create a bias supply that can be used to supply at least 1 mA of current to the PRIMARY BYPASS pin. The turns ratio for the bias winding should be selected such that 7 V is developed across the bias winding at the lowest rated output voltage of the power supply at the lowest load condition. If the voltage is lower than this, no-load input power will increase. 13 www.power.com Rev. S 03/23 InnoSwitch3-EP The bias current from the external circuit should be set to IS1(MAX) to achieve lowest no-load power consumption when operating the power supply at 230 VAC input, (VBPP > 5 V). A glass passivated standard recovery rectifier diode with low junction capacitance is recommended to avoid the snappy recovery typically seen with fast or ultrafast diodes that can lead to higher radiated EMI. An aluminum capacitor of at least 22 mF with a voltage rating 1.2 times greater than the highest voltage developed across the capacitor is recommended. Highest voltage is typically developed across this capacitor when the supply is operated at the highest rated output voltage and load with the lowest input AC supply voltage. Line UV and OV Protection Resistors connected from the UNDER/OVER INPUT VOLTAGE pin to the DC bus enable sensing of input voltage to provide line undervoltage and overvoltage protection. For a typical universal input application, a resistor value of 3.8 MW is recommended. Figure 17 shows circuit configurations that enable either the line UV or the line OV feature only to be enabled. InnoSwitch3-EP features a primary sensed OV protection feature that can be used to latch-off the power supply. Once the power supply is latched off, it can be reset if the UNDER/OVER INPUT VOLTAGE pin current is reduced to zero. Once the power supply is latched off, even after the input supply is turned off, it can take considerable amount of time to reset the InnoSwitch3-EP controller as the energy stored in the DC bus will continue to provide current to the controller. A fast AC reset can be achieved using the modified circuit configuration shown in Figure 18. The voltage across capacitor CS reduces rapidly after input supply is disconnected reducing current into the INPUT VOLTAGE MONITOR pin of the InnoSwitch3-EP IC and resetting the InnoSwitch3-EP controller. Primary Sensed OVP (Overvoltage Protection) The voltage developed across the output of the bias winding tracks the power supply output voltage. Though not precise, a reasonably accurate detection of the amplitude of the output voltage can be achieved by the primary-side controller using the bias winding voltage. A Zener diode connected from the bias winding output to the PRIMARY BYPASS pin can reliably detect a secondary overvoltage fault and cause the primary-side controller to latch-off or auto-restart depending on H Code. It is recommended that the highest voltage at the output of the bias winding should be measured for normal steadystate conditions (at full load and lowest input voltage) and also under transient load conditions. A Zener diode rated for 1.25 times this measured voltage will typically ensure that OVP protection will only operate in case of a fault. Primary-Side Snubber Clamp A snubber circuit should be used on the primary-side as shown in Figure 10. This prevents excess voltage spikes at the drain of the Switch at the instant of turn-off of the Switch during each switching cycle though conventional RCD clamps can be used. RCDZ clamps offer the highest efficiency. The circuit example shown in Figure 10 uses an RCD clamp with a resistor in series with the clamp diode. This resistor dampens the ringing at the drain and also limits the reverse current through the clamp diode during reverse recovery. Standard recovery glass passivated diodes with low junction capacitance are recommended as these enable partial energy recovery from the clamp thereby improving efficiency. Components for InnoSwitch3-EP Secondary-Side Circuit SECONDARY BYPASS Pin – Decoupling Capacitor A 2.2 mF, 10 V / X7R or X5R /0805 or larger size multi-layer ceramic capacitor should be used for decoupling the SECONDARY BYPASS pin of the InnoSwitch3-EP IC. Since the SECONDARY BYPASS Pin voltage needs to be 4.4 V earlier than output voltage reaches the regulation voltage level, the significantly higher BPS capacitor value could lead to output voltage overshoot during start-up. Values lower than 1.5 mF may not enough capacitance, which can cause unpredictable operation. The capacitor must be located adjacent to the IC pins. At least 10 V is recommended voltage rating to give enough margin from BPS voltage, and 0805 size is necessary to guarantee the actual value in operation since the capacitance of ceramic capacitors drops significantly with applied DC voltage especially with small package SMD such as 0603. 6.3 V / 0603 / X5U or Z5U type of MLCC is not recommended for this reason. The ceramic capacitor type designations, such as X7R, X5R from different manufacturers or different product families do not have the same voltage coefficients. It is recommended that capacitor data sheets be reviewed to ensure that the selected capacitor will not have more than 20% drop in capacitance at 4.4 V. Capacitors with X5R or X7R dielectrics should be used for best results. FORWARD Pin Resistor A 47 W, 5% resistor is recommended to ensure sufficient IC supply current. A higher or lower resistor value should not be used as it can affect device operation such as the timing of the synchronous rectifier drive. Figures 11, 12, 13 and 14 below show examples of unacceptable and acceptable FORWARD pin voltage waveforms. VD is forward voltage drop across the SR. 0V VSR(TH) VD PI-8392-051818 Figure 13. Unacceptable FORWARD Pin Waveform After Handshake with SR Switch Conduction During Flyback Cycle. 0V VSR(TH) VD PI-8393-051818 Figure 14. Acceptable FORWARD Pin Waveform After Handshake with SR Switch Conduction During Flyback Cycle. 14 www.power.com Rev. S 03/23 InnoSwitch3-EP voltage of 1.5 V to 2.5 V are ideal although Switches with a threshold voltage (absolute maximum) as high as 4 V may be used provided their data sheets specify RDS(ON) across temperature for a gate voltage of 4.5 V. 0V VSR(TH) VD t1 t2 PI-8394-051818 Figure 15. Unacceptable FORWARD Pin Waveform before Handshake with Body Diode Conduction During Flyback Cycle. Note: If t1 + t2 = 1.5 ms ± 50 ns, the controller may fail the handshake and trigger a primary bias winding OVP latch-off/auto-restart. 0V VSR(TH) There is a slight delay between the commencement of the flyback cycle and the turn-on of the SR FET. During this time, the body diode of the SR FET conducts. If an external parallel Schottky diode is used, this current mostly flows through the Schottky diode. Once the InnoSwitch3-EP IC detects end of the flyback cycle, voltage across SR FET RDS(ON) reaches 0 V, any remaining portion of the flyback cycle is completed with the current commutating to the body diode of the SR FET or the external parallel Schottky diode. Use of the Schottky diode parallel to the SR FET may provide higher efficiency and typically a 1 A surface mount Schottky diode is adequate. However, the gains are modest. For a 5 V, 2 A design the external diode adds ~0.1% to full load efficiency at 85 VAC and ~0.2% at 230 VAC. The voltage rating of the Schottky diode and the SR FET should be at least 1.4 times the expected peak inverse voltage (PIV) based on the turns ratio used for the transformer. 60 V rated FETs and diodes are suitable for most 5 V designs that use a VOR < 60 V, and 100 V rated FETs and diodes are suitable for 12 V designs. The interaction between the leakage reactance of the output windings and the SR FET capacitance (COSS) leads to ringing on the voltage waveform at the instance of voltage reversal at the winding due to primary Switch turn-on. This ringing can be suppressed using an RC snubber connected across the SR FET. A snubber resistor in the range of 10 W to 47 W may be used (higher resistance values lead to noticeable drop in efficiency). A capacitance value of 1 nF to 2.2 nF is adequate for most designs. Output Capacitor Low ESR aluminum electrolytic capacitors are suitable for use with most high frequency flyback switching power supplies, though the use of aluminum-polymer solid capacitors have gained considerable popularity due to their compact size, stable temperature characteristics, extremely low ESR and high RMS ripple current rating. These capacitors enable the design of ultra-compact chargers and adapters. VD PI-8393-051818 Figure 16. Acceptable FORWARD Pin Waveform before Handshake with Body Diode Conduction During Flyback Cycle. SR Switch Operation and Selection Although a simple diode rectifier and filter works for the output, use of an SR FET enables the significant improvement in operating efficiency often necessary to meet the European CoC and the U.S. DoE energy efficiency requirements. The secondary-side controller turns on the SR FET once the flyback cycle begins. The SR FET gate should be tied directly to the SYNCHRONOUS RECTIFIER DRIVE pin of the InnoSwitch3-EP IC (no additional resistors should be connected in the gate circuit of the SR FET). The SR FET is turned off once the VDS of the SR FET reaches 0 V. A FET with 18 mW RDS(ON) is appropriate for a 5 V, 2 A output, and a FET with 8 mW RDS(ON) is suitable for designs rated with a 12 V, 3 A output. The SR FET driver uses the SECONDARY BYPASS pin for its supply rail, and this voltage is typically 4.4 V. A FET with a high threshold voltage is therefore not suitable; FETs with a threshold Typically, 200 mF to 300 mF of aluminum-polymer capacitance per ampere of output current is adequate. The other factor that influences choice of the capacitance is the output ripple. Ensure that capacitors with a voltage rating higher than the highest output voltage plus sufficient margin be used. Output Voltage Feedback Circuit The output voltage FEEDBACK pin voltage is 1.265 V [VFB]. A voltage divider network should be connected at the output of the power supply to divide the output voltage such that the voltage at the FEEDBACK pin will be 1.265 V when the output is at its desired voltage. The lower feedback divider resistor should be tied to the SECONDARY GROUND pin. A 300 pF (or smaller) decoupling capacitor should be connected at the FEEDBACK pin to the SECONDARY GROUND pin of the InnoSwitch3-EP IC. This capacitor should be placed close to the InnoSwitch3-EP IC. 15 www.power.com Rev. S 03/23 InnoSwitch3-EP Recommendations for Circuit Board Layout R1 See Figure 19 for a recommended circuit board layout for an InnoSwitch3-EP based power supply. R2 Single-Point Grounding Use a single-point ground connection from the input filter capacitor to the area of copper connected to the SOURCE pins. Bypass Capacitors The PRIMARY BYPASS and SECONDARY BYPASS pin capacitor must be located directly adjacent to the PRIMARY BYPASS-SOURCE and SECONDARY BYPASS-SECONDARY GROUND pins respectively and connections to these capacitors should be routed with short traces. FB GND V BPS D SR 1N4148 FWD + VOUT S Primary Loop Area The area of the primary loop that connects the input filter capacitor, transformer primary and IC should be kept as small as possible. IS BPP InnoSwitch3-EP PI-8410-081717 Primary Clamp Circuit A clamp is used to limit peak voltage on the DRAIN pin at turn-off. This can be achieved by using an RCD clamp or a Zener diode (~200 V) and diode clamp across the primary winding. To reduce EMI, minimize the loop from the clamp components to the transformer and IC. + R1 Thermal Considerations The SOURCE pin is internally connected to the IC lead frame and provides the main path to remove heat from the device. Therefore the SOURCE pin should be connected to a copper area underneath the IC to act not only as a single point ground, but also as a heat sink. As this area is connected to the quiet source node, it can be maximized for good heat sinking without compromising EMI performance. Similarly for the output SR Switch, maximize the PCB area connected to the pins on the package through which heat is dissipated from the SR Switch. 6.2 V FB GND BPS V SR D FWD R2 VOUT S IS BPP InnoSwitch3-EP PI-8411-051818 Figure 17. (Top) Line OV Only; (Bottom) Line UV Only. InnoSwitch3-EP CS 100 nF FB GND BPS V SR D FWD SR FET VOUT Primary FET and Controller S BPP IS Secondary Control IC PI-8412-081717 Figure 18. Fast AC Reset Configuration. 16 www.power.com Rev. S 03/23 InnoSwitch3-EP Sufficient copper area should be provided on the board to keep the IC temperature safely below the absolute maximum limits. It is recommended that the copper area provided for the copper plane on which the SOURCE pin of the IC is soldered is sufficiently large to keep the IC temperature below 110 °C when operating the power supply at full rated load and at the lowest rated input AC supply voltage. Y Capacitor The Y capacitor should be placed directly between the primary input filter capacitor positive terminal and the output positive or return terminal of the transformer secondary. This routes high amplitude common mode surge currents away from the IC. Note – if an input pi-filter (C, L, C) EMI filter is used then the inductor in the filter should be placed between the negative terminals of the input filter capacitors. Output SR Switch For best performance, the area of the loop connecting the secondary winding, the output SR Switch and the output filter capacitor, should be minimized. ESD Sufficient clearance should be maintained (>8 mm) between the primary-side and secondary-side circuits to enable easy compliance with any ESD / hi-pot requirements. The spark gap is best placed directly between output positive rail and one of the AC inputs. In this configuration a 6.4 mm spark gap is often sufficient to meet the creepage and clearance requirements of many applicable safety standards. This is less than the primary to secondary spacing because the voltage across spark gap does not exceed the peak of the AC input. Drain Node The drain switching node is the dominant noise generator. As such the components connected the drain node should be placed close to the IC and away from sensitive feedback circuits. The clamp circuit components should be located physically away from the PRIMARY BYPASS pin and trace lengths minimized. The loop area of the loop comprising of the input rectifier filter capacitor, the primary winding and the IC primary-side Switch should be kept as small as possible. 17 www.power.com Rev. S 03/23 InnoSwitch3-EP Layout Example 6.4 mm spark gap AC side directly connected to input line Maximize source area for good heat sinking PCB - Top Side Current sense resistor (R12) and secondary bypass capacitor (C7) are placed across ISENSE and GROUND pins, BPS and GROUND pins respectively Keep drain and clamp loop short; Keep drain components away from PRIMARY BYPASS pin circuitry SOURCE pin ground provides heat sink and shield between DRAIN and signal pins circuitry Feedback lower resistor (R13) and decoupling capacitor (C8) are placed across FEEDBACK and GROUND pins Tight loop area for the 12 V (1) and 5 V (2) outputs power train Place VOLTAGE pin resistor (R4) and BPP bypass capacitor (C6) close to the IC pin In order to increase ESD immunity and to meet isolation requirement, no traces are routed beneath the IC Tight loop area for the external bias supply with dedicated ground trace returned to the bulk negative PCB - Bottom Side PI-8413-091919 Figure 19. PCB. 18 www.power.com Rev. S 03/23 InnoSwitch3-EP Recommendations for EMI Reduction Consider the following for design optimization: 1. Appropriate component placement and small loop areas of the primary and secondary power circuits help minimize radiated and conducted EMI. Care should be taken to achieve a compact loop area. 2. A small capacitor in parallel to the clamp diode on the primaryside can help reduce radiated EMI. 3. A resistor in series with the bias winding helps reduce radiated EMI. 4. Common mode chokes are typically required at the input of the power supply to sufficiently attenuate common mode noise. However, the same performance can be achieved by using shield windings on the transformer. Shield windings can also be used in conjunction with common mode filter inductors at input to improve conducted and radiated EMI margins. 5. Adjusting SR switch RC snubber component values can help reduce high frequency radiated and conducted EMI. 6. A pi-filter comprising differential inductors and capacitors can be used in the input rectifier circuit to reduce low frequency differential EMI. 7. A 1 mF ceramic capacitor connected at the output of the power supply helps to reduce radiated EMI. 1. Higher VOR allows increased power delivery at VMIN, which minimizes the value of the input capacitor and maximizes power delivery from a given InnoSwitch3-EP device. 2. Higher VOR reduces the voltage stress on the output diodes and SR Switches. 3. Higher VOR increases leakage inductance which reduces power supply efficiency. 4. Higher VOR increases peak and RMS current on the secondary-side which may increase secondary-side copper and diode losses. Recommendations for Transformer Design Transformer design must ensure that the power supply delivers the rated power at the lowest input voltage. The lowest voltage on the rectified DC bus depends on the capacitance of the filter capacitor used. At least 2 mF/W is recommended to always keep the DC bus voltage above 70 V, though 3 mF/W provides sufficient margin. The ripple on the DC bus should be measured to confirm the design calculations for transformer primary-winding inductance selection. Switching Frequency (fSW) It is a unique feature in InnoSwitch3-EP that for full load, the designer can set the switching frequency to between 25 kHz to 95 kHz. For lowest temperature, the switching frequency should be set to around 60 kHz. For a smaller transformer, the full load switching frequency needs to be set to 95 kHz. When setting the full load switching frequency it is important to consider primary inductance and peak current tolerances to ensure that average switching frequency does not exceed 110 kHz which may trigger auto-restart due to overload protection. The following table provides a guide to frequency selection based on device size. This represents the best compromise between overall device losses (conduction losses and switching losses) based on the size of the integrated high-voltage Switch. INN3672C and INN3673C 85-90 kHz INN3674C and INN3675C 80 kHz INN3676C 75 kHz INN3677C 70 kHz INN369x 70 kHz PowiGaN device INN3678C 70 kHz PowiGaN device INN3679C 65 kHz PowiGaN device INN3670C 60 kHz INN364x 45 kHz Reflected Output Voltage, VOR (V) This parameter describes the effect on the primary Switch drain voltage of the secondary-winding voltage during diode/SR conduction which is reflected back to the primary through the turns ratio of the transformer. To make full use of QR capability and ensure flattest efficiency over line/load, set reflected output voltage (VOR) to maintain KP = 0.8 at minimum input voltage for universal input and KP = 1 for high-line-only conditions. There are some exceptions to this. For very high output currents the VOR should be reduced to get highest efficiency. For output voltages above 15 V, VOR should be higher to maintain an acceptable PIV across the output synchronous rectifier. Ripple to Peak Current Ratio, KP A KP below 1 indicates continuous conduction mode, where KP is the ratio of ripple-current to peak-primary-current (Figure 20). KP ≡ KRP = IR / IP A value of KP higher than 1, indicates discontinuous conduction mode. In this case KP is the ratio of primary Switch off-time to the secondary diode conduction-time. KP ≡ KDP = (1 – D) x T/ t = VOR × (1 – DMAX) / ((VMIN – VDS) × DMAX) It is recommended that a KP close to 0.9 at the minimum expected DC bus voltage should be used for most InnoSwitch3-EP designs. A KP value of 1 T = 1/fS Primary D×T (1-D) × T = t Secondary (b) Borderline Discontinuous/Continuous, KP = 1 PI-2578-103114 Figure 21. Discontinuous Conduction Mode Current Waveform, KP > 1. 20 www.power.com Rev. S 03/23 InnoSwitch3-EP Transformer Primary Inductance, LP Once the lowest operating input voltage, switching frequency at full load, and required VOR are determined, the transformers primary inductance can be calculated. The PIXls design spreadsheet can be used to assist in designing the transformer. Quick Design Checklist As with any power supply, the operation of all InnoSwitch3-EP designs should be verified on the bench to make sure that component limits are not exceeded under worst-case conditions. As a minimum, the following tests are strongly recommended: 1. Maximum Drain Voltage – Verify that VDS of InnoSwitch3-EP and SR FET do not exceed 90% of breakdown voltages at the highest input voltage and peak (overload) output power in normal operation and during start-up. 2. Maximum Drain Current – At maximum ambient temperature, maximum input voltage and peak output (overload) power. Review drain current waveforms for any signs of transformer saturation or excessive leading-edge current spikes at start-up. Repeat tests under steady-state conditions and verify that the leading edge current spike is below ILIMIT(MIN) at the end of tLEB(MIN). Under all conditions, the maximum drain current for the primary Switch should be below the specified absolute maximum ratings. 3. Thermal Check – At specified maximum output power, minimum input voltage and maximum ambient temperature, verify that temperature specification limits for InnoSwitch3-EP IC, transformer, output SR FET, and output capacitors are not exceeded. Enough thermal margin should be allowed for part-to-part variation of the RDS(ON) of the InnoSwitch3-EP IC. Under low-line, maximum power, a maximum InnoSwitch3-EP SOURCE pin temperature of 110 °C is recommended to allow for these variations. Design Considerations When Using 750 V and 900 V PowiGaN Devices For a flyback converter configuration, typical voltage waveform at the DRAIN pin of the IC is shown in Figure 22 for 750 V device and Figure 23 for 900 V device. VOR is the reflected output voltage across the primary winding when the secondary is conducting. VBUS is the DC voltage connected to one end of the transformer primary winding. In addition to VBUS+VOR, the drain also sees a large voltage spike at turn off that is caused by the energy stored in the leakage inductance of the primary winding. To keep the drain voltage from exceeding the rated maximum continuous drain voltage, a clamp circuit is needed across the primary winding. The forward recovery of the clamp diode will add a spike at the instant of turn-OFF of the primary switch. VCLM in Figure 22 and Figure 23 is the combined clamp voltage including the spike. The peak drain voltage of the primary switch is the total of VBUS, VOR and VCLM. VOR and the clamp voltage VCLM should be selected such that the peak drain voltage is lower than 650 V for 750 V device and 810 V for 900 V device for all normal operating conditions. This provides sufficient margin to ensure that occasional increase in voltage during line transients such as line surges will maintain the peak drain voltage well below 750 V and 900 V under abnormal transient operating conditions. This ensures excellent long term reliability and design margin. To make full use of QR capability and ensure flattest efficiency over line/load, set reflected output voltage (VOR) to maintain KP = 0.8 at minimum input voltage for universal input and KP ≥ 1 for high-lineonly conditions. Consider the following for design optimization: 1. Higher VOR allows increased power delivery at VMIN, which minimizes the value of the input capacitor and maximizes power delivery from a given PowiGaN device. 2. Higher VOR reduces the voltage stress on the output diodes and SR FETs. 3. Higher VOR increases leakage inductance which reduces power supply efficiency. 4. Higher VOR increases peak and RMS current on the secondary-side which may increase secondary-side copper and diode losses. There are some exceptions to this. For very high output currents the VOR should be reduced to get highest efficiency. For output voltages above 15 V, VOR should be maintained higher to maintain an acceptable PIV across the output synchronous rectifier. VOR choice will affect the operating efficiency and should be selected carefully. Table below shows the typical range of VOR for optimal performance: Output Voltage Optimal Range for VOR 5V 45 - 70 12 V 80 - 120 15 V 100 - 135 20 V 120 - 150 24 V 135 - 180 (for 750 V GaN) 135 - 150 (for 900 V GaN) 21 www.power.com Rev. S 03/23 InnoSwitch3-EP 750 V = VMAX(NON-REPETITIVE) Safe Surge Voltage Region (SSVR) Typical margin (150 V) gives de-rating of >80% VCLM 650 V = VMAX(CONTINUOUS) VCLM < 90 V VOR 380 VDC VBUS Primary Switch Voltage Stress (264 VAC) PI-8769g-031023 Figure 22. Peak Drain Voltage for 264 VAC Input Voltage using 750 V PowiGaN. 900 V = VMAX(NON-REPETITIVE) Safe Surge Voltage Region (SSVR) Typical margin (175 V) gives de-rating of >80% VCLM 725 V = VMAX(CONTINUOUS) VCLM < 75 V VOR 540 VDC VBUS Primary Switch Voltage Stress (380 VAC) PI-8769h-031323 Figure 23. Peak Drain Voltage for 380 VAC Input Voltage using 900 V PowiGaN. 22 www.power.com Rev. S 03/23 InnoSwitch3-EP Thermal Resistance Test Conditions for PowiGaN Devices Thermal resistance value is for primary power device junction to ambient only. Testing performed on custom thermal test PCB as shown in Figure 24. The test board consists of 2 layers of 2 oz. Cu with the InSOP package mounted to the top surface and connected to a bottom layer Cu heat sinking area of 550 mm2. Connection between the two layers was made by 82 vias in a 5 x 17 matrix outside the package mounting area. Vias are spaced at 40 mils, with 12 mil diameter and plated through holes are not filled. Figure 24. Thermal Resistance Test Conditions for PowiGaN Thermal resistance value is for INN3679C primary and power device junction to Devices (INN3678C, INN3670C.) ambient only. Testing performed on custom thermal test PCB as shown in the figure above. The test board consists of 2 layers of 2 oz. Cu with the InSOP package mounted to the top surface and connected to a bottom layer Cu heatsinking area of 550mm2. Connection between the two layers was made by 82 vias in a 5 x 17 matrix outside the package mounting area. Vias are spaced at 40 mils, with 12 mil diameter and plated through holes are not filled. Figure xx. Thermal Resistance Test Conditions for INN3379C and INN3370C 23 www.power.com Rev. S 03/23 InnoSwitch3-EP Absolute Maximum Ratings1,2 DRAIN Pin Voltage: INN3672C - INN3677C.................. -0.3 V to 725 V INN3678C - INN3670C................. -0.3 V to 750 V6 INN369x.....................................-0.3 V to 900 V7 INN364x.................................... -0.3 V to 1700 V DRAIN Pin Peak Current: INN3672C........................................ 1.70 A3 INN3673C........................................2.38 A3 INN3674C........................................ 3.47 A3 INN3675C........................................ 4.11 A3 INN3676C........................................ 5.19 A3 INN3677C........................................ 5.92 A3 PowiGaN device INN3678C.................6.5 A3 PowiGaN device INN3679C..................10 A3 PowiGaN device INN3670C..................14 A3 PowiGaN device INN3697C.................3.2 A3 PowiGaN device INN3699C..................10 A3 PowiGaN device INN3690C..................14 A3 INN3692C..........................................2.2 A3 INN3694C........................................ 3.96 A3 INN3696C........................................ 5.72 A3 INN3647C............................................ 5 A3 INN3649C...........................................10 A3 BPP/BPS Pin Voltage ........................................................-0.3 to 6 V BPP/BPS Current .................................................................. 100 mA FWD Pin Voltage ....................................................... -1.5 V to 150 V FB Pin Voltage ..............................................................-0.3 V to 6 V SR Pin Voltage ..............................................................-0.3 V to 6 V VOUT Pin Voltage ....................................................... -0.3 V to 27 V V Pin Voltage............................................................. -0.3 V to 725 V IS Pin Voltage8 ...........................................................-0.3 V to 0.3 V Storage Temperature....................................................-65 to 150 °C Operating Junction Temperature4 ................................. -40 to 150 °C Ambient Temperature...................................................-40 to 105 °C Lead Temperature4................................................................ 260 °C NOTES: 1. All voltages referenced to SOURCE and Secondary GROUND, TA = 25 °C. 2. Maximum ratings specified may be applied one at a time without causing permanent damage to the product. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect product reliability. 3. Please refer to Figure 25, 31, 39, 43 and 47 about maximum allowable voltage and current combinations. 4. Normally limited by internal circuitry. 5. 1/16” from case for 5 seconds. 6. PowiGaN devices: INN367x Maximum drain voltage (non-repetitive pulse)..........-0.3 V to 750 V Maximum continuous drain voltage.........................-0.3 V to 650 V 7. PowiGaN devices: INN369x Maximum drain voltage (non-repetitive pulse)..........-0.3 V to 900 V Maximum continuous drain voltage.........................-0.3 V to 725 V 8. Absolutely maximum voltage for less than 500 msec is 3 V. Thermal Resistance Thermal Resistance: INN3672C to INN3677C & INN3692C to INN3696C (qJA)..................................... 76 °C/W1, 65 °C/W2 (qJC)......................................................8 °C/W3 PowiGan Devices (qJA).................................................... 50 °C/W4 INN3647C (qJA).....................................92 °C/W1, 64 °C/W2 (qJC).................................................... 19 °C/W3 INN3649C (qJA).....................................76 °C/W1, 70 °C/W2 (qJC).................................................... 11 °C/W3 Notes: 1. Soldered to 0.36 sq. inch (232 mm2) 2 oz. (610 g/m2) copper clad. 2. Soldered to 1 sq. inch (645 mm2), 2 oz. (610 g/m2) copper clad. 3. The case temperature is measured on the top of the package. 4. Please see Figure 23. 24 www.power.com Rev. S 03/23 InnoSwitch3-EP Symbol Conditions SOURCE = 0 V TJ = -40 °C to 125 °C (Unless Otherwise Specified) Min Typ Max Units Startup Switching Frequency fSW TJ = 25 °C 23 25 27 kHz Jitter Frequency fM TJ = 25 °C fSW = 100 kHz 0.80 1.25 1.70 kHz tON(MAX) TJ = 25 °C 12.4 14.6 16.9 µs tOFF(MIN) µs Parameter Control Functions Maximum On-Time Minimum Primary Feedback Block-Out Timer tBLOCK IS1 VBPP = VBPP + 0.1 V (Switch not Switching) TJ = 25 °C BPP Supply Current IS2 BPP Pin Charge Current VBPP = VBPP + 0.1 V (Switch Switching at 132 kHz) TJ = 25 °C INN36xxC 145 200 300 µA INN3678C INN3670C INN3647C INN3649C 145 266 425 µA INN3672C 0.33 0.44 0.60 INN3673C 0.36 0.48 0.65 INN3674C 0.44 0.58 0.83 INN3675C 0.59 0.79 1.10 INN3676C 0.77 1.02 1.38 INN3677C 0.90 1.20 1.73 INN3692C 0.33 0.44 0.60 INN3694C 0.44 0.58 0.85 INN3696C 0.7 0.90 1.35 INN3678C 0.93 1.24 1.79 INN3679C INN3670C 1.46 1.95 2.81 INN3697C TBD 1.95 TBD INN3699C TBD 1.95 TBD INN3690C TBD 1.95 TBD INN3647C 0.93 1.25 1.80 INN3649C 1.46 1.95 2.81 ICH1 VBP = 0 V, TJ = 25 °C -1.75 -1.35 -0.88 ICH2 VBP = 4 V, TJ = 25 °C -5.98 -4.65 -3.32 mA mA BPP Pin Voltage VBPP INN36xxC 4.65 4.90 5.15 INN3647C INN3649C 4.65 4.90 5.20 BPP Pin Voltage Hysteresis VBPP(H) TJ = 25 °C BPP Shunt Voltage VSHUNT IBPP = 2 mA 5.15 5.36 5.65 V VBPP(RESET) TJ = 25 °C 2.80 3.15 3.50 V INN36xxC INN369xC 23.9 26.1 28.2 INN3678C - INN3670C INN3647C / INN3649C 22.4 24.4 26.7 BPP Power-Up Reset Threshold Voltage UV/OV Pin Brown-In Threshold IUV+ TJ = 25 °C 0.39 V V µA 25 www.power.com Rev. S 03/23 InnoSwitch3-EP Parameter Symbol Conditions SOURCE = 0 V TJ = -40 °C to 125 °C (Unless Otherwise Specified) Min Typ Max INN36xxC INN369xC 21.0 23.7 25.5 INN3678C - INN3670C INN3647C / INN3649C 19 21.6 23.5 Units Control Functions (cont.) UV/OV Pin Brown-Out Threshold IUV- Brown-Out Delay Time tUV- TJ = 25 °C TJ = 25 °C 35 INN36xxC INN369xC UV/OV Pin Line Overvoltage Threshold IOV+ TJ = 25 °C INN3678C INN3670C INN3647C INN3649C UV/OV Pin Line Overvoltage Hysteresis UV/OV Pin Line Overvoltage Recovery Threshold IOV(H) TJ = 25 °C IOV- TJ = 25 °C VOLTAGE Pin Line Overvoltage Deglitch Filter tOV+ TJ = 25 °C See Note B VOLTAGE Pin Voltage Rating VV TJ = 25 °C µA ms 106 115 118 106 112 118 µA INN36xxC 7 INN3678C INN3670C INN369xC 8 INN3647C INN3649C 7 µA 100 µA Line Fault Protection 3 µs 650 V Circuit Protection Standard Current Limit (BPP) Capacitor = 0.47 mF See Note C ILIMIT di/dt = 138 mA/ms TJ = 25 °C INN3672C 418 450 482 di/dt = 163 mA/ms TJ = 25 °C INN3673C 511 550 589 di/dt = 188 mA/ms TJ = 25 °C INN3674C 697 750 803 di/dt = 213 mA/ms TJ = 25 °C INN3675C 883 950 1017 di/dt = 238 mA/ms TJ = 25 °C INN3676C 1162 1250 1338 di/dt = 300 mA/ms TJ = 25 °C INN3677C 1255 1350 1445 di/dt = 375 mA/ms TJ = 25 °C INN3678C 1581 1700 1819 di/dt = 425 mA/ms TJ = 25 °C INN3679C 1767 1900 2033 di/dt = 525 mA/ms TJ = 25 °C INN3670C 2139 2300 2461 di/dt = 138 mA/ms TJ = 25 °C INN3692C 416 450 483 di/dt = 188 mA/ms TJ = 25 °C INN3694C 693 750 806 di/dt = 238 mA/ms TJ = 25 °C INN3696C 1156 1250 1344 mA 26 www.power.com Rev. S 03/23 InnoSwitch3-EP Parameter Symbol Conditions SOURCE = 0 V TJ = -40 °C to 125 °C (Unless Otherwise Specified) Min Typ Max Units Circuit Protection (cont.) Standard Current Limit (BPP) Capacitor = 0.47 mF See Note C Increased Current Limit (BPP) Capacitor = 4.7 mF See Note C ILIMIT ILIMIT+1 di/dt = 300 mA/ms TJ = 25 °C INN3647C 1488 1600 1712 di/dt = 425 mA/ms TJ = 25 °C INN3649C 1767 1900 2033 di/dt = 325 mA/ms TJ = 25 °C INN3697C TBD 1300 TBD di/dt = 425 mA/ms TJ = 25 °C INN3699C TBD 1900 TBD di/dt = 525 mA/ms TJ = 25 °C INN3690C TBD 2300 TBD di/dt = 138 mA/ms TJ = 25 °C INN3672C 500 550 600 di/dt = 163 mA/ms TJ = 25 °C INN3673C 591 650 709 di/dt = 188 mA/ms TJ = 25 °C INN3674C 864 950 1036 di/dt = 213 mA/ms TJ = 25 °C INN3675C 1046 1150 1254 di/dt = 238 mA/ms TJ = 25 °C INN3676C 1319 1450 1581 di/dt = 300 mA/ms TJ = 25 °C INN3677C 1410 1550 1689 di/dt = 375 mA/ms TJ = 25 °C INN3678C 1767 1900 2033 di/dt = 425 mA/ms TJ = 25 °C INN3679C 1980 2130 2279 di/dt = 525 mA/ms TJ = 25 °C INN3670C 2395 2576 2756 di/dt = 138 mA/ms TJ = 25 °C INN3692C 495 550 605 di/dt = 188 mA/ms TJ = 25 °C INN3694C 855 950 1045 di/dt = 238 mA/ms TJ = 25 °C INN3696C 1305 1450 1595 di/dt = 300 mA/ms TJ = 25 °C INN3647C 1674 1800 1926 di/dt = 425 mA/ms TJ = 25 °C INN3649C 1980 2130 2279 di/dt = 325 mA/ms TJ = 25 °C INN3697C TBD 1460 TBD di/dt = 425 mA/ms TJ = 25 °C INN3699C TBD 2130 TBD di/dt = 525 mA/ms TJ = 25 °C INN3690C TBD 2576 TBD mA mA 27 www.power.com Rev. S 03/23 InnoSwitch3-EP Symbol Conditions SOURCE = 0 V TJ = -40 °C to 125 °C (Unless Otherwise Specified) Min Typ Max Units Overload Detection Frequency fOVL TJ = 25 °C 102 110 118 kHz BYPASS Pin Latching Shutdown Threshold Current ISD TJ = 25 °C 6.0 7.5 11.3 mA Auto-Restart On-Time t AR TJ = 25 °C 75 82 89 ms t AR(SK) TJ = 25 °C See Note A t AR(OFF) TJ = 25 °C Parameter Circuit Protection (cont.) Auto-Restart Trigger Skip Time 1.3 sec Output Auto-Restart Off-Time Short Auto-Restart Off-Time t AR(OFF)SH TJ = 25 °C See Note B INN3672C ID = ILIMIT+1 0.17 0.20 0.23 INN3647C INN3649C 0.20 TJ = 25 °C 6.30 7.25 TJ = 100 °C 9.77 11.24 TJ = 25 °C 4.42 5.08 TJ = 100 °C 6.85 7.88 INN3674C ID = ILIMIT+1 TJ = 25 °C 3.22 3.70 TJ = 100 °C 4.99 5.74 TJ = 25 °C 1.95 2.24 TJ = 100 °C 3.02 3.47 TJ = 25 °C 1.34 1.54 TJ = 100 °C 2.08 2.39 TJ = 25 °C 1.20 1.38 TJ = 100 °C 1.86 2.14 TJ = 25 °C 0.52 0.68 TJ = 100 °C 0.78 1.02 TJ = 25 °C 0.35 0.44 TJ = 100 °C 0.49 0.62 TJ = 25 °C 0.29 0.39 TJ = 100 °C 0.41 0.54 TJ = 25 °C 6.0 7.2 TJ = 100 °C 9.5 11.2 TJ = 25 °C 3.5 4.1 TJ = 100 °C 5.2 6.0 TJ = 25 °C 2.35 2.8 TJ = 100 °C 3.4 4.2 TJ = 25 °C 1.20 1.53 TJ = 100 °C 1.98 2.52 INN3676C ID = ILIMIT+1 INN3677C ID = ILIMIT+1 RDS(ON) INN36xxC 2.11 INN3673C ID = ILIMIT+1 INN3675C ID = ILIMIT+1 ON-State Resistance 1.7 INN3678C ID = ILIMIT+1 INN3679C ID = ILIMIT+1 INN3670C ID = ILIMIT+1 INN3692C ID = ILIMIT+1 INN3694C ID = ILIMIT+1 INN3696C ID = ILIMIT+1 INN3647C ID = ILIMIT+1 sec sec W 28 www.power.com Rev. S 03/23 InnoSwitch3-EP Parameter Symbol Conditions SOURCE = 0 V TJ = -40 °C to 125 °C (Unless Otherwise Specified) Min Typ Max TJ = 25 °C 0.45 0.62 TJ = 100 °C 0.74 1.02 TJ = 25 °C 0.85 TBD TJ = 100 °C TBD TBD TJ = 25 °C 0.35 TBD TJ = 100 °C TBD TBD TJ = 25 °C 0.29 TBD TJ = 100 °C TBD TBD Units Output (cont.) INN3649C ID = ILIMIT+1 ON-State Resistance INN3697C ID = ILIMIT+1 RDS(ON) INN3699C ID = ILIMIT+1 INN3690C ID = ILIMIT+1 OFF-State Drain Leakage Current IDSS1 VBPP = VBPP + 0.1 V VDSS = 80% Peak Drain Voltage TJ = 125 °C IDSS2 VBPP = VBPP + 0.1 V VDSS = 325 V TJ = 25 °C Drain Supply Voltage Thermal Shutdown TSD Thermal Shutdown Hysteresis TSD(H) 200 15 See Note A 30 See Note A 135 See Note A W mA mA V 142 INN367x INN369x 70 INN364x 30 150 °C °C Secondary FEEDBACK Pin Voltage VFB TJ = 25 °C 1.25 1.265 1.280 V Maximum Switching Frequency fSREQ TJ = 25 °C 118 132 145 kHz FEEDBACK Pin Auto-Restart Threshold VFB(AR) FEEDBACK and IS Pin Auto-Restart Timer tFB(AR) tIS(AR) BPS Pin Current at No-Load ISNL BPS Pin Voltage VBPS BPS Pin Undervoltage Threshold VBPS(UVLO)(TH) BPS Pin Undervoltage Hysteresis VBPS(UVLO)(H) 90 % TJ = 25 °C 49.5 ms TJ = 25 °C 325 485 mA 4.20 4.40 4.60 V 3.60 3.80 4.00 V 0.65 Current Limit Voltage Threshold ISV(TH) FWD Pin Breakdown Voltage VFWD 150 Minimum Off-Time tOFF(MIN) 2.48 Set By External Resistor TJ = 25 °C 35.17 35.90 V 36.62 mV V 3.38 4.37 ms 29 www.power.com Rev. S 03/23 InnoSwitch3-EP Symbol Conditions SOURCE = 0 V TJ = -40 °C to 125 °C (Unless Otherwise Specified) Min Typ Max Units Soft-Start Frequency Ramp Time tSS(RAMP) TJ = 25 °C 7.5 11.8 19.0 ms BPS Pin Latch/ Auto-Restart Command Shutdown Threshold Current IBPS(SD) 5.2 8.9 12 mA FEEDBACK Pin Short-Circuit VFB(OFF) 112 135 mV 4.4 4.6 V -2.5 0 mV Parameter Secondary (cont.) TJ = 25 °C Synchronous Rectifier @ TJ = 25 °C SR Pin Drive Voltage 4.2 VSR SR Pin Voltage Threshold VSR(TH) SR Pin Pull-Up Current ISR(PU) TJ = 25 °C CLOAD = 2 nF, fSW = 100 kHz INN367x, INN369x 125 165 195 INN364x 135 165 195 SR Pin Pull-Down Current ISR(PD) TJ = 25 °C CLOAD = 2 nF, fSW = 100 kHz INN367x, INN369x 87 97 115 INN364x 260 298 336 tR TJ = 25 °C CLOAD = 2 nF See Note B Rise Time Fall Time tF Output Pull-Up Resistance RPU Output Pull-Down Resistance RPD TJ = 25 °C CLOAD = 2 nF See Note B TJ = 25 °C VBPS = 4.4 V ISR = 10 mA TJ = 25 °C VBPS = 4.4 V ISR = 10 mA 10-90% 90-10% INN367x INN369x 50 INN364x 40 INN367x INN369x 80 INN364x 15 mA mA ns ns INN367x INN369x 7.2 8.3 12 INN364x 7.2 8.5 9.6 INN367x INN369x 10.0 12.1 15 INN364x 3.52 3.95 4.39 W W NOTES: A. This parameter is derived from characterization. B. This parameter is guaranteed by design. C. To ensure correct current limit it is recommended that nominal 0.47 mF / 4.7 mF capacitors are used. In addition, the BPP capacitor value tolerance should be equal or better than indicated below across the ambient temperature range of the target application. The minimum and maximum capacitor values are guaranteed by characterization. Nominal BPP Pin Capacitor Value BPP Capacitor Value Tolerance Minimum Maximum 0.47 mF -60% +100% 4.7 mF -50% N/A Recommended to use at least 10 V / 0805 / X7R SMD MLCC. 30 www.power.com Rev. S 03/23 InnoSwitch3-EP 0.75 0.50 0.25 1.0 0.8 0.6 0.4 TCASE = 25 °C TCASE = 100 °C 0.2 0 0 100 200 300 400 500 600 700 800 Drain Voltage (V) Figure 25. Maximum Allowable Drain Current vs. Drain Voltage (INN3672-INN3677). 1000 100 100 4 6 Drain Voltage (V) 8 10 Scaling Factors: INN3672 1.00 INN3673 1.40 INN3674 1.95 INN3675 3.20 INN3676 4.60 INN3677 5.20 75 Power (mW) Scaling Factors: INN3672 1.00 INN3673 1.40 INN3674 1.95 INN3675 3.20 INN3676 4.60 INN3677 5.20 2 Figure 26. Output Characteristics. PI-8426-090117 10000 0 PI-8428-090117 0.0 Drain Capacitance (pF) Scaling Factors: INN3672 1.00 INN3673 1.40 INN3674 1.95 INN3675 3.20 INN3676 4.60 INN3677 5.20 1.2 Drain Current (A) 1.0 PI-8427-121418 1.4 PI-8966-042919 Drain Current (A) (Normalized to Absolute Maximum Current Rating) Typical Performance Curves 50 10 25 1 0 Switching Frequency = 100 kHz 1 100 200 300 400 500 600 0 100 -1.8 Time (ns) Figure 29. SYNCHRONOUS RECTIFIER DRIVE Pin Negative Voltage. 600 1.2 1.0 0.8 0.6 Normalized di/dt = 1 0.4 0.2 0 500 ns 500 PI-8432-090717 -0.3 400 1.4 Normalized Current Limit -0.0 300 Figure 28. Drain Capacitance Power. PI-7474-011215 SYNCHRONOUS RECTIFIER DRIVE Pin Voltage Limits (V) Figure 27. COSS vs. Drain Voltage. VSR(t) 200 Drain Voltage (V) Drain Voltage (V) 1 2 Note: For the normalized current limit value, use the typical current limit specified for the appropriate BP/M capacitor. 3 4 Normalized di/dt Figure 30. Standard Current Limit vs. di/dt. 31 www.power.com Rev. S 03/23 InnoSwitch3-EP Drain Current (A) 1.0 0.75 0.50 0.25 Scaling Factors: INN3692 0.5 INN3694 1.0 INN3696 1.5 2 1.5 1 0.5 0 0 100 200 300 400 500 600 700 800 900 1000 Drain Voltage (V) 1 2 3 4 5 6 7 8 9 10 Figure 32. Output Characteristics. 300 PI-8960-040519 Scaling Factors: INN3692 0.5 INN3694 1.0 INN3696 1.5 Scaling Factors: INN3692 0.5 INN3694 1.0 INN3696 1.5 250 Power (mW) 1000 0 Drain Voltage (V) Figure 31. Maximum Allowable Drain Current vs. Drain Voltage (INN369x). 10000 T = 25 °C T = 100 °C 100 10 PI-8961-030223 0.0 Drain Capacitance (pF) PI-8959-040519 2.5 PI-8900-042919 Drain Current (A) (Normalized to Absolute Maximum Current Rating) Typical Performance Curves 200 150 100 50 Switching Frequency = 100 kHz 1 1 100 200 300 400 500 0 600 Drain Voltage (V) 0 100 200 300 400 Drain Voltage (V) 500 600 Figure 34. Drain Capacitance Power. Figure 33. COSS vs. Drain Voltage. Breakdown Voltage (Normalized to 25 °C) PI-2213-021518 1.1 1.0 0.9 -50 -25 0 25 50 75 100 125 150 Junction Temperature (°C) Figure 35. Breakdown vs. Temperature (Exclude INN3678C / INN3679C / INN3670C / INN3647C / INN3649C). 32 www.power.com Rev. S 03/23 InnoSwitch3-EP 20 15 10 5 Scaling Factors: INN3678C 0.62 INN3679C 1.0 INN3670C 1.4 1000 100 10 0 2 4 6 8 0 50 10 150 100 50 0 10 100 200 300 400 Drain Voltage (V) Figure 38. Drain Capacitance Power. 500 Scaling Factors: INN3678C 0.65 INN3679C 1.0 INN3670C 1.4 1 450 550 0.1 0.01 0.001 0 350 100 Drian Current (A) Power (mW) PI-8854l-110719 Scaling Factors: INN3678C 0.62 INN3679C 1.0 INN3670C 1.4 200 250 Figure 37. COSS vs. Drain Voltage. Figure 36. Output Characteristics. 250 150 Drain Voltage (V) Drain Voltage VDS (V) PI-8851m-012720 0 TCASE = 25 °C TCASE = 100 °C 10000 PI-8852l-110719 Scaling Factors: INN3678C 0.62 INN3679C 1.0 INN3670C 1.4 Drain Capacitance (pF) Drain Current IDS (A) 25 PI-8853l-110719 Typical Performance Curves 10 100 Drain Voltage (V) 1000 Figure 39. Maximum Allowable Drain Current vs. Drain Voltage (PowiGaN Devices INN3678C / INN3679C / INN3670C). 33 www.power.com Rev. S 03/23 InnoSwitch3-EP 15 10 5 0 TCASE = 25 °C TCASE = 100 °C 0 2 4 6 8 1000 100 10 1 10 Scaling Factors: INN3697C 0.32 INN3699C 1.0 INN3690C 1.4 0 Drain Voltage VDS (V) Power (mW) 350 Drain Voltage (V) 300 250 200 150 100 100 Drain Current (A) 400 PI-8854ee-030223 Scaling Factors: INN3697C 0.32 INN3699C 1.0 INN3690C 1.4 100 200 300 400 500 600 700 800 Figure 41. COSS vs. Drain Voltage. Figure 40. Output Characteristics. 450 PI-8852ff-030223 20 10000 PI-8851ii-030223 Scaling Factors: INN3697C 0.32 INN3699C 1.0 INN3690C 1.4 Drain Capacitance (pF) Drain Current IDS (A) 25 PI-8853gg-030223 Typical Performance Curves 10 Scaling Factors: INN3697C 0.32 INN3699C 1.0 INN3690C 1.4 1 0.1 0.01 50 0 0 100 200 300 400 500 600 700 800 Drain Voltage (V) Figure 42. Drain Capacitance Power. 0.001 10 100 Drain Voltage (V) 1000 Figure 43. Maximum Allowable Drain Current vs. Drain Voltage (PowiGaN Devices INN3697C / INN3699C / INN3690C). 34 www.power.com Rev. S 03/23 InnoSwitch3-EP 400 300 200 Freq: 100 kHz 100 0 0 100 300 500 700 Drain Voltage (V) 900 Drain Current (A) PI-9410b-012622 Scaling Factors: INN3647 1.0 INN3649 3.0 5 4 3 2 0 1 2 3 4 5 6 7 Drain Voltage (V) Figure 46. Output Characteristics. 300 500 700 Drain Voltage (V) 900 1100 1.0 Pulse Width: 1 µs Scaling Factors: INN3647C 7: 1.0 INN3649C 9: 2.0 0.1 0.01 0 100 10 TCASE = 100 °C TCASE = 25 °C 1 0 30 Figure 45. COSS vs. Drain Voltage. Figure 44. Drain Capacitance Power. 6 300 3 1100 PI-9400b-012622 500 INN3647 COSS INN3649 COSS PI-9411b-010422 Power (mW) 600 3000 Drain Capacitance (pF) INN3647C INN3649C Drain Current (A) 700 PI-9399a-010422 Typical Performance Curves 8 9 10 1 10 100 1000 10000 Drain-Source Voltage, VDS (V) Figure 47. Maximum Allowable Drain Current vs. Drain Voltage. 35 www.power.com Rev. S 03/23 www.power.com 0.057 0.049 Body Thickness 1.45 1.25 2 1 0.75 [0.030] C B 24 Coplanarity: 17 Leads C Seating Plane C A B 16X 3 A 4 2X C A 2 3 Detail A 0.30 0.18 0.41 [0.016] 8.25 [0.325] 0.75 [0.030] 0.032 0.020 1.58 [0.062] Standoff 0.010 0.004 6. Datums A & B to be determined at Datum H. 5. Controlling dimensions in millimeters [inches]. 4. Does not include inter-lead flash or protrusions. 3. Dimensions noted are inclusive of plating thickness. PI-8106-052620 POD-InSOP-24D Rev B 2.81 [0.111] 8.25 [0.325] 7.50 [0.295] 6.75 [0.266] 4.80 [0.189] 0.45 [0.018] Ref. PCB PAD LAYOUT 1.58 [0.062] C 0.25 0.10 12.72 [0.501] DETAIL A Seating Plane H 2. Dimensions noted are determined at the outermost extremes of the plastic body exculsive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. Maximum mold protrusion is 0.18 [0.007] per side. 17X 0.012 0.007 0.25 [0.010] 0° – 8° 0.81 0.51 Gauge Plane 0.20 [0.008] Ref. BOTTOM VIEW 0.10 [0.004] 9.40 [0.370] END VIEW 0.107 0.102 1.32 [0.052] Ref. C C 2.71 2.59 Notes: 1. Dimensioning and Tolerancing per ASME Y14.5M – 1994. SIDE VIEW 0.012 0.008 4 12 Lead Tips 0.15 [0.006] 13.43 [0.529] 0.15 [0.006] 5 Lead Tips 0.25 [0.010] M 3 0.30 0.20 12 13 0.10 [0.004] C TOP VIEW 0.50 [0.020] Ref. 1.60 [0.063] Max. Total Mounting Height Pin #1 I.D. 10.80 [0.425] 0.10 [0.004] 2X 3.35 [0.132] Ref. InSOP-24D InnoSwitch3-EP Rev. S 03/23 36 InnoSwitch3-EP PACKAGE MARKING InSOP-24D INN3676C M6J542A A A. B. C. D. E. 1738 1 Hxxx C D B E Power Integrations Registered Trademark Assembly Date Code (last two digits of year followed by 2-digit work week) Product Identification (Part #/Package Type) Lot Identification Code Test Sublot and Feature Code PI-8727-050418 37 www.power.com Rev. S 03/23 InnoSwitch3-EP Parameter Conditions Rating Units Current from pin (16-19) to pin 24 1.5 A TAMB = 25 °C (Device mounted in socket resulting in TCASE = 120 °C) 1.35 W TAMB = 25 °C (Device mounted in socket) 0.125 W Ratings for UL1577 Primary-Side Current Rating Primary-Side Power Rating Secondary-Side Power Rating 38 www.power.com Rev. S 03/23 InnoSwitch3-EP Parameter Symbol Conditions Rating Units Package Characteristics Clearance CLR 11.4 mm (min) Creepage CPG 11.4 mm (min) Distance Through Insulation DTI 0.4 mm Comparative Tracking Index CTI >600 V Isolation Resistance, Input to Output R IO Isolation Capacitance, Input to Output CIO VIO = 500 V, TJ = 25 °C (See Note 1) 1012 VIO = 500 V, 100 °C ≤ TJ ≤ 125 °C (See Note 1) 1011 (See Note 1) 1 INN3672C to INN3677C 512 INN3678C to INN3670C 530 INN3692C to INN3690C 636 INN3672C to INN3277C 725 INN3678C to INN3670C 750 INN3692C to INN3690C 900 INN3647C to INN3649C 1700 W (min) pF Package Insulation Characteristics (See Note 2) Maximum RMS Working Isolation Voltage Maximum Repetitive Peak Isolation Voltage Maximum Transient Peak Isolation Voltage Maximum Surge Isolation Voltage VIORM(RMS) VIORM(PK) Climatic Category INN369xC 6.6 INN367xC 8 INN369xC 8 INN367xC 10.4 INN369xC 10.4 INN3672C to INN3677C 1160 INN3678C to INN3670C 1200 INN3692C to INN3690C 140 INN3672C to INN3677C 870 INN3678C to INN3670C 900 INN3692C to INN3690C 1080 INN3672C to INN3677C 1360 INN3678C to INN3670C 1406 INN3692C to INN3690C 1688 INN3647C to INN3649C 3188 t=1s (100% Production) VIOSM Surge Test 1.2/50 usec Table 2 IEC 60747-17 VPD Method A, After Input / Output Safety Test Subgroup 2/3, VPD = 1.2 × VIORM, t = 10 s, (qualification) Partial Discharge < 5 pC Method B1, 100% Production Test, VPD = 1.875 × VIORM, t = 1 s Partial Discharge < 5 pC Insulation Resistance 6.6 VIOTM Method A, After Environmental Tests Subgroup 1, VPD = 1.6 × VIORM, t = 10 s (qualification) Partial Discharge < 5 pC Input to Output Test Peak Voltage INN367xC Test Voltage = VIOTM, t = 60 s (Qualification) RS VIO = 500 V at TJ = 150 ºC >109 VRMS (max) VPK (max) kVPK (max) kVPK (max) VPEAK(min) W 40/125/21 39 www.power.com Rev. S 03/23 InnoSwitch3-EP Parameter Conditions Specifications Material Group I Rated Mains RMS voltage ≤ 150 V I - IV Rated Mains RMS voltage ≤ 300 V I - IV Rated Mains RMS voltage ≤ 600V I - IV Rated Mains RMS voltage ≤ 1000 V I - III IEC 60664-1 Rating Table Basic Isolation Group Insulation Classification Note 1: All pins on each side of the barrier tied together creating a two-terminal device Note 2: VDE 0884-17 (IEC/EN 60747-17) Only applies to devices with following H-Codes: -H608, -H609, -H610, -H611 and –H612 Note 3: VDE 0884-17 certification is pending for INN3697C, INN3699C, INN3690C and INN364xC devices. 40 www.power.com Rev. S 03/23 InnoSwitch3-EP Feature Code Table1 Features H6012 H6022 H6053 H606 Feedback Resistors External External External External IS Sense Resistor External External External External ILIM Selectable Yes Yes Yes Yes Primary Fault Response Auto-Restart Auto-Restart Auto-Restart Auto-Restart Secondary Fault Response Auto-Restart Auto-Restart Auto-Restart Auto-Restart Auto-Restart VFB(AR) = 90% x VFB VFB(AR) = Overload VFB(AR) = 90% × VFB VFB(AR) = Overload Over-Temperature Protection Hysteretic Hysteretic Hysteretic Hysteretic Line OV/UV Enabled Enabled OV Disabled UV Enabled Enabled UV Timer tUV- = 35 ms (Typ) tUV- = 35 ms (Typ) tUV- = 35 ms (Typ) tUV- = 35 ms (Typ) Secondary Switch/Diode Short-Circuit Protection Enabled Enabled Disabled Disabled Integrated VOUT OVP Enabled Enabled Enabled Enabled Peak Power Delivery No Yes No Yes For the latest updates, please visit www.power.com InnoSwitch Family page to Build Your Own InnoSwitch. Available only on INN3672C – INN3677C. 3 Available only on INN3674C – INN3677C and PowiGaN devices. 1 2 MSL Table Part Number MSL Rating INN36xxC 3 ESD and Latch-Up Table Test Conditions Results Latch-up at 125 °C JESD78D Human Body Model ESD ANSI/ESDA/JEDEC JS-001-2014 > ±2000 V on all pins Charge Device Model ESD ANSI/ESDA/JEDEC JS-002-2014 > ±500 V on all pins > ±100 mA or > 1.5 × VMAX on all pins Part Ordering Information • InnoSwitch3 Product Family • EP Series Number • Switch Rating 7 725 V / 750 V 9 900 V 4 1700 V • Package Identifier C InSOP-24D • Features Code • Tape & Reel and Other Options INN 3672 C - H601 - TL TL Tape & Reel, 2 k pcs per reel. 41 www.power.com Rev. S 03/23 InnoSwitch3-EP Revision Notes Date A Preliminary release. 02/17 B Introduction release. 05/17 C Production release. 09/17 D Added InSOP-24D package marking and made minor text edits. 06/18 D Updated Full Safety and Regulatory Compliance section on page 1 and added CTI to the parameter table. 08/18 E Added INN369x series. 04/19 F Updated page 1 Advanced Protection / Safety Features section. 06/19 G Added GaN-based INN3679C and INN3670C parts. Updated IDSS1 and IDSS2 parameters. 08/19 H Added ‘PowiGaN’ trademark name. 09/19 I PCN-19281 – Updated Figure 17. Updated parameters: VBPP(H), IUV-, IOV(H), IOV-, VV, tSS(RAMP), ISR(PU), tR, tF, RPU, VSR and IBPS(SD). 10/19 J Added INN3678C part for introduction release. 11/19 K Production release. Added new application design example. 02/20 L Updated IDSS1 parameter to read VDS = 80% Peak Drain Voltage. 03/20 M Updated safety information on page 1 and corrected typo in Package drawing on page 33. 06/20 N Update Package Characteristics Table and VDE 0884-11 device list. 07/21 O Updated Package Characteristics Table and VDE-0884-17 device list. 09/21 P Production release of 1700 V part numbers. 06/22 Q Updated IUV+, IUV-, IOV+ and IOV(H) parameters. 09/22 R Updated isolation voltage on page 1. Updated VIOTM and deleted VISO parameters. 11/22 S Introduction release of INN3697C, INN3699C, INN3690C part numbers. 03/23 42 www.power.com Rev. S 03/23 For the latest updates, visit our website: www.power.com Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. Patent Information The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set forth at www.power.com/ip.htm. Life Support Policy POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein: 1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or death to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Power Integrations, the Power Integrations logo, CAPZero, ChiPhy, CHY, DPA-Switch, EcoSmart, E-Shield, eSIP, eSOP, HiperLCS, HiperPLC, HiperPFS, HiperTFS, InnoSwitch, Innovation in Power Conversion, InSOP, LinkSwitch, LinkZero, LYTSwitch, SENZero, TinySwitch, TOPSwitch, PI, PI Expert, PowiGaN, SCALE, SCALE-1, SCALE-2, SCALE-3 and SCALE-iDriver, are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©2023, Power Integrations, Inc. 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Phone: +886-2-2659-4570 e-mail: taiwansales@power.com UK Building 5, Suite 21 The Westbrook Centre Milton Road Cambridge CB4 1YG Phone: +44 (0) 7823-557484 e-mail: eurosales@power.com Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Power Integrations: INN3672C-H601-TL INN3672C-H602-TL INN3673C-H601-TL INN3673C-H602-TL INN3674C-H601-TL INN3674CH602-TL INN3675C-H601-TL INN3675C-H602-TL INN3676C-H601-TL INN3676C-H602-TL INN3677C-H601-TL INN3677C-H602-TL INN3672C-H606-TL INN3673C-H606-TL INN3674C-H606-TL INN3675C-H603-TL INN3676CH606-TL INN3677C-H604-TL INN3677C-H605-TL INN3677C-H606-TL INN3675C-H604-TL INN3675C-H605-TL INN3675C-H606-TL INN3676C-H603-TL INN3676C-H604-TL INN3676C-H605-TL INN3692C-H606-TL INN3694CH606-TL INN3696C-H606-TL INN3677C-H603-TL INN3679C-H605-TL INN3670C-H605-TL INN3679C-H606-TL INN3670C-H606-TL INN3678C-H606-TL INN3678C-H605-TL INN3670C-H615-TL INN3647C-H606-TL INN3649CH606-TL