LCS700HG

LCS700-708 HiperLCS™ Family Integrated LLC Controller, High-Voltage Power MOSFETs and Drivers Product Highlights Features • LLC half-bridge power stage incorporating controller, high and low-side gate drives, and high-voltage power MOSFETs • Eliminates up to 30 external components • High maximum operating frequency of 1 MHz • Nominal steady-state operation up to 500 kHz • Dramatically reduces magnetics size and allows use of SMD ceramic output capacitors • Precise duty symmetry balances output rectifier current, improving efficiency • 50% ±0.3% typical at 300 kHz • Comprehensive fault handling and current limiting • Programmable brown-in/out thresholds and hysteresis • Undervoltage (UV) and overvoltage (OV) protection • Programmable over-current protection (OCP) • Short-circuit protection (SCP) • Over-temperature protection (OTP) • Programmable dead-time for optimized design • Programmable burst mode maintains regulation at no-load and improves light load efficiency • Programmable soft-start time and delay before soft-start • Accurate programmable minimum and maximum frequency limits • Single package designed for high-power and high-frequency • Reduces assembly cost and reduces PCB layout loop areas • Simple single clip attachment to heat sink • Exposed thermal pad connected to ground potential – no insulators required between package and heat sink • Staggered pin arrangement for simple PC board routing and high-voltage creepage requirements • Paired with HiperPFS PFC product gives complete, high efficiency, low part count PSU solutions Applications • High-efficiency power supplies (80 PLUS Silver, Gold and Platinum) • LCD TV power supplies • LED street and area lighting • Printer power supplies • Audio amplifier Description The HiperLCS is an integrated LLC power stage incorporating a multi-function controller, high-side and low-side gate drivers, plus two power MOSFETs in a half-bridge configuration. Figure 1 shows a simplified schematic of a HiperLCS based power stage where the LLC resonant inductor is integrated into the transformer. The variable frequency controller provides high efficiency by switching the power MOSFETs at zero voltage (ZVS), eliminating switching losses. B+ VCCH D Standby Supply VCC CONTROL HB +V HV DC Input OV/UV VREF RFMAX DT/BF IS RTN RBURST FB G S1/S2 HiperLCS B- LLC Feedback Circuit PI-6159-060211 Figure 1. Typical Application Circuit – LCD TV and PC Main Power Supply. Output Power Table Product LCS700HG LCS701HG LCS702HG LCS703HG LCS705HG LCS708HG Maximum Practical Power1 110 W 170 W 220 W 275 W 350 W 440 W Table 1. Output Power Table. Notes: 1. Maximum practical power is the power the part can deliver when properly mounted to a heat sink and a maximum heat sink temperature of 90 °C. www.powerint.com June 2011 LCS700-708 VCC VREF 3.4 V REGULATOR UVLO DRAIN (D) VCCH + LLC_ON UVLO SOFT-START DELAY 131,072 LLC CLOCK CYCLES OV/UV VSDH/ VSDL + VOVH/ VOVL + DEBOUNCE 3 LLC CLOCK CYCLES OVERTEMPERATURE PROTECTION IS VISF LEVEL SHIFT + HB VISS VREF 7 CONSECUTIVE LLC CLOCK CYCLES LLC_CLK FEEDBACK (FB) DT/BF LLC CLOCK DEAD-TIME GENERATOR OUTPUT CONTROL LOGIC + DEBOUNCE 3 LLC CLOCK CYCLES Bursting Thresholds Control DT/BF RESISTOR SENSOR GROUND (G) PI-5755-060111 SOURCE (S1/S2) Figure 2. Block Diagram. 2 Rev. B 062011 www.powerint.com LCS700-708 Pin Functional Description VCC Pin IC power pin. In a typical application, VCC is connected to the 12 V system standby supply via a 5 W resistor. This resistor helps provide filtering and improves noise immunity. Note: The system standby supply return should be connected to the B- bus and not to the GROUND pin. VREF Pin 3.4 VREF pin. An internal voltage reference network used as a voltage source for FEEDBACK pin and DT/BF pin pull-up resistor. GROUND (G) Pin G is the return node for all analog small signals. All small signal pin bypass capacitors must be returned to this pin through short traces, with the exception of the D-S high-voltage bypass capacitor, and the VCCH bypass capacitor. It is internally connected to the SOURCE pins to provide a star connection. Do not connect the GROUND pin to the SOURCE pins, nor to the B- bus, in the PCB layout. OV/UV Pin Overvoltage/Undervoltage pin. B+ is sensed by this pin through a resistor divider. The OV/UV pin implements brown-in, brown-out, and overvoltage lockout with hysteresis. Pulling this pin down to ground will implement a remote-off function. FEEDBACK (FB) Pin Current fed into this pin determines LLC switching frequency; higher current programs higher switching frequency. The pin V-I characteristic resembles a diode to ground during normal switching. An RC network between the VREF pin and FEEDBACK pin determines the minimum operating frequency, start-up frequency, soft-start time, and delay before start-up. DEAD-TIME/BURST FREQUENCY (DT/BF) Pin A resistor divider from VREF to ground programs dead-time, maximum switching frequency at start-up, and burst-mode threshold frequencies. CURRENT-SENSE (IS) Pin The CURRENT-SENSE pin is used for sensing transformer primary current, to detect overload and fault conditions, through a current sense resistor or a capacitive divider plus sense resistor circuit. It resembles a reverse diode to ground, and does not require a rectifier circuit for preventing negative pulses from reaching the pin, provided the reverse current is limited to 0.9 V. Both will invoke a 131,072 cycle restart cycle. VCC can also be pulled down to shut the device off, but when it is pulled up, the FEEDBACK pin is pulled up to the VREF pin to discharge the soft-start capacitor for only 1024 fMAX clock cycles. If this scheme is used, the designer must ensure that the time the VCC is pulled down, plus 1024 cycles, is sufficient to discharge the soft-start capacitor, or if not, that the resulting lower starting frequency is high enough so as not to cause excessive primary currents that may cause the over-current protection to trip. Current Sense The IS pin senses the primary current. It resembles a reverse diode to the GROUND pin. It is tolerant of negative voltages provided the negative current is limited to 220 W. Thus it can accept an AC waveform and does not need a rectifier or peak detector circuit. If the IS pin senses a nominal positive peak voltage of 0.5 V for 7 consecutive cycles, an auto-restart will be invoked. The IS pin also has a second, higher threshold at nominally 0.9 V, which will invoke an auto-restart with a single pulse. The minimum 5 www.powerint.com Rev. B 062011 LCS700-708 pulse width requirement for detection of both voltage thresholds is nominally 30 ns. i.e. the thresholds have to be exceeded for >30 ns for proper detection. Over-Temperature Shutdown The HiperLCS has latching OTP. VCCH must be cycled to resume operation once the unit drops down below the OTP threshold. entering the two most sensitive pins on the list, namely the FEEDBACK and DT/BF pins, will cause duty cycle, and deadtime imbalance, respectively. Figure 5 and Figure 6 show two alternate schemes for routing ground traces for optimum performance. Figure 5 shows a layout footprint for the LCS with oval pads. These allow a trace to be passed between pins 3 and 5, directly connecting the ground systems for the bypass capacitors located on each side of the IC. Figure 6 shows an LCS layout footprint with round pads that do not allow traces to be routed between them due to insufficient space. In this case, a jumper (JP1, a 1206 size 0 W resistor) is used to connect the ground systems together and allow a connection for pin 3 to be routed under JP1 to the optocoupler. Transformer T1 is a source of both high di/dt signals and dv/dt noise. The first can couple magnetically to sensitive circuitry, while the second can inject noise via electrostatic coupling. Electrostatic noise coupling can be reduced by grounding the transformer core, but it is not economically feasible to reduce the stray magnetic field around the transformer without drastically reducing its efficiency. Sensitive traces and components (such as the optocoupler) should be located away from the transformer to avoid noise pickup. Notes Increase value proportionally for lower nominal frequency (e.g. 10 nF at 100 kHz). Forms a pole with FEEDBACK pin input impedance which is part of feedback loop characteristic. Must not introduce excessive phase shift at expected gain crossover frequency. Noise entering FEEDBACK pin will cause duty cycle imbalance. Basic Layout Guidelines The HiperLCS is a high-frequency power device and requires careful attention to circuit board layout in order to achieve maximum performance. The bypass capacitors need to be positioned and laid out carefully to minimize trace lengths to the pins they serve. SMD components are recommended for minimum component and trace stray inductance. Table 2 describes the recommended bypass capacitor values for pins that require filtering/bypassing. The table lists the pins in the order of most to least sensitive. The bypass capacitor of the pin at the top of the list being the most sensitive, receives higher priority in bypass capacitor positioning to minimize trace lengths, than the bypass capacitor of the pin below it. Noise Pin FEEDBACK (FB) Returned to Pin GROUND Recommended Value 4.7 nF (at 250 kHz) DEAD-TIME/BURST FREQUENCY (DT/BF) GROUND 4.7 nF Time constant of this capacitor and the source impedance of the resistors connected to DT/BF pin must be 300 kHz start to lose significant efficiency due to increased eddy current losses in the copper, and due to the fact that a more significant percentage of time is spent on the primary slew time (ZVS transition time) which erodes the percentage of time that power is transferred to the secondary. Resonant Tank and Transformer Design Please refer to the Application Note AN-55 for guidance on using the PIXls HiperLCS spreadsheet which assists in the entire design process. Primary Inductance The optimal powertrain design for the HiperLCS uses a primary inductance that results in minimal loss of ZVS at any steadystate condition. Some loss of ZVS during non-steady-state conditions is acceptable. Reducing primary inductance produces higher magnetizing current which increases the range of ZVS operation, but the increased magnetizing current increases losses and reduces efficiency. The calculation of the primary inductance to be used for a first-pass design is based on device size, rated load, minimum input voltage, and desired operating frequency. It is provided in the PIXls spreadsheet. LPRI is the primary inductance of an integrated transformer (high leakage inductance), or in the case of the use of an external series inductance, the sum of this inductance and the transformer primary inductance. Leakage Inductance The parameter KRATIO is a function of leakage inductance: K RATIO = L PRI - 1 L RES The recommended KRATIO is from 2.5 - 7. This determines the acceptable range of leakage inductance. LRES is the leakage inductance in an integrated transformer; if a separate series inductor is used, it is the sum of this inductance and the leakage inductance of the transformer. A low KRATIO (high leakage inductance) may not be capable of regulation at the minimum input voltage, and may show increased transformer copper losses due to the leakage flux. A high KRATIO (low leakage inductance) will have high peak and RMS currents at low-line, and require a lower primary inductance to achieve ZVS operation over a suitably wide range, which increases the resonant circulating current, reducing efficiency. The core and bobbin designs available to the designer may limit the adjustability of leakage inductance. Fortunately, excellent performance can be achieved over a relatively wide range of leakage inductance values. The KRATIO directly affects the frequency range that the LLC needs to operate in order to maintain regulation over the input voltage range. Increasing KRATIO increases this frequency range, lowering fMIN. A low fMIN is only a potential problem for low frequency designs which typically run at higher nominal BAC. This may allow the core to reach saturation when operating at fMIN. Operating at fMIN occurs when the input voltage is at a minimal (input brown-out). For a design with a separate resonant inductor, running the inductance on the low side of the range (KRATIO = 7), minimizes the size and cost of the inductor. Adjusting Leakage Inductance Sectioned bobbins (separated primary and secondary) are commonly used for LLC converters. Increasing or decreasing both primary and secondary turns (while maintaining turns ratio) will change the leakage inductance proportionally to the square of primary turns. If the leakage inductance is too high, one possible solution is to use a 3-section bobbin, where the secondary is in the middle section, and the primary winding is split into 2 halves connected in series. Lastly, if the leakage inductance is too low an external inductor may be added. 11 www.powerint.com Rev. B 062011 LCS700-708 Resonant Frequency The series resonant frequency is a function of LRES and CRES, the resonant capacitor. For any given value of LRES, the value of CRES can be adjusted for the desired series resonant frequency fRES. For best efficiency the resonant frequency is set close to the target operating frequency at nominal input voltage. Operating Frequency and Frequency Ratio The operating to resonant frequency ratio fRATIO is defined as: recommended fRATIO ≈ 0.95 at nominal input voltage, VINPUT(RESONANCE) will be slightly higher than the nominal voltage. For a design with a variable nominal input voltage (e.g. no PFC pre-regulator), it is recommended that the initial turns ratio be set so that VINPUT(RESONANCE) is at about halfway between maximum and minimum input voltage. For a design with a variable output voltage (e.g. constant current regulated output), it is recommended that the initial turns ratio be set to operate the LLC at resonance at a point halfway between minimum and maximum output voltages. Dead-Time Selection The vast majority of designs using HiperLCS, regardless of power and operating frequency, work very well with a dead-time of between 290 and 360 ns. Designs that require a low VBROWNOUT tend to require shorter dead-times. The dead-time setting is a compromise between low-line / full load (low frequency), and minimum-load / high-line (highfrequency) conditions. Low-line / full load operation has short optimal dead-times, while minimum load / high-line has long optimal dead-times. A dead-time setting that is longer than optimal for low-line / full load operation, exhibiting partial loss of ZVS, is acceptable if the condition does not occur during steady-state operation – i.e. appears only during transient conditions, such as hold-up time. Operation with loss of ZVS during steady-state operation leads to high internal power dissipation and should be avoided. A dead-time setting that is shorter than optimal for high-line / minimum-load operation, will tend to cause the feedback sign to invert and force the HiperLCS to enter burst mode. This is acceptable if the resulting burst mode operation is acceptable (i.e. repetition rate does not produce audible noise and if the large signal transients, wherein the HiperLCS enters and exits burst mode, is acceptable). Note that with a PFC pre-regulated front end, a load dump (e.g. 100% to 1% load step) will exhibit a transient input voltage condition only temporarily (e.g. Input voltage to LLC stage will increase from 380 V to 410 V and relatively slowly return to 380 V). Note also that the Burst Threshold frequency setting is another variable available to the designer to tune burst mode. OV/UV Pin The HiperLCS OV/UV pin which monitors the input (B+) voltage, has a brown-out shutdown threshold (VSD(L)) of nominally 79% of the brown-in (turn-on) threshold (VSD(H)), which in turn, is nominally 2.4 V. The overvoltage (OV) lockout shutdown threshold (VOV(H)) is nominally 131% of the brown-in start-up threshold, and the OV restart point (VOV(L)) at nominally 126%. The ratios of these thresholds are fixed and selected for maximum utility in a design with a PFC pre-regulator front-end with a fixed output voltage set-point. The resistor divider ratio has to be selected so that brown-in point is always below the PFC output set-point, and so that the OV restart (lower) threshold, is always above it, including component tolerances. During hold-up time, the voltage will drop from the nominal value, down to the brown-out threshold, whereby the HiperLCS will stop switching. fRATIO = fSW fRES fRATIO = 1 signifies the converter is operating at the series resonant frequency. The main determinant of fRATIO is the transformer turns ratio. Increasing primary turns lowers fRATIO for a given input and output voltage. The recommended fRATIO at nominal input voltage is 0.92 – 0.97. Operating at resonance often yields the highest efficiency for the resonant powertrain if output rectifier selection is ignored. However, operating slightly below resonance (which puts the rectifiers in discontinuous conduction mode), allows the use of lower voltage diodes or synchronous MOSFETs, which have lower losses, increasing overall efficiency. This is because at high-line, when the converter needs to operate above resonance, the rectifiers operate less deeply in continuous mode, reducing the magnitude of their current commutation, reducing their stray inductance voltage spikes. (The stray inductance is comprised of the leakage inductance between secondary phases and the stray inductance in the connections to the rectifiers and output capacitors). Conversely, operating at a very low fRATIO (fSTOP. fMAX is the frequency at which the internal counters run when the HiperLCS is in the off-state of the auto-restart cycle, or in the power-up delay before switching. The minimum recommended dead-time is 275 ns, and thus the maximum fMAX setting is 1 MHz. To simplify the selection of RFMAX, see the selection curves in Figure 17. 12.0 11.0 BT1 BT2 BT3 PI-6458-051911 The fSTOP to fSTART ratio is fixed, and dependent on the Burst Threshold setting (see Table 5). Burst Threshold Setting 1 2 3 Table 5. Ratio of fSTOP /fSTART vs. Burst Threshold Selection. fSTOP / fSTART 1.14 1.17 1.20 As a first approximation, during burst mode, the frequency ramps from fSTART to fSTOP; then switching stops, and then the cycle repeats. FEEDBACK Pin The FEEDBACK pin is the voltage regulation FEEDBACK pin. It has a nominal Thevenin equivalent circuit of 0.65 V and 2.5 kW. In normal operation, it sinks current. During the off-period of auto-restart, and during the clocked delay before start-up, it pulls up internally to VREF in order to discharge the soft-start capacitor. The current entering the pin determines switching frequency. Higher current yields higher frequency and thus reduces LLC output voltage. In a typical application an optocoupler connected to the VREF pin pulls up on the FEEDBACK pin, via a resistor network. The optocoupler is configured to source increasing FEEDBACK pin current, as the output rises. The resistor network between the optocoupler, FEEDBACK pin, and VREF pin, determine the minimum and maximum FEEDBACK pin current (and thus the minimum and maximum operating frequency), that the optocoupler can command as it goes from cutoff to saturation. This network also contains the soft-start timing capacitor, CSTART (Figure 19). The minimum frequency as set by this network must be lower than the frequency required by the powertrain at minimum input voltage. In Figure 19 this is determined by the sum of RFMIN and RSTART. The FEEDBACK pin current is determined by these two resistors when the optocoupler is cut off. CSTART can be ignored during normal operation. Do not confuse RSTART, which determines 13.0 RFMAX (kΩ) 10.0 9.0 8.0 7.0 6.0 5.0 250 300 350 400 450 500 Dead-Time (ns) Figure 17. RFMAX vs. Dead-Time, for the 3 Different Burst Threshold Settings. 14 Rev. B 062011 www.powerint.com PI-6457-051911 450 500 LCS700-708 Bursting Duty ≈ 50% VREF CSTART RFMIN 3.4 V 10 s / div RSTART D1 FB CFB 4.7 nF GND PI-6118-051711 U1B IPRI VHB 850 ns / div ROPTO RLOAD ~850 kHz Severe Loss of ZVS Figure 20. Bursting at fMAX Causes High Internal Dissipation Due to Loss of ZVS and Should be Avoided. Figure 19. Feedback Network Shown with Additional Load Resistor. The FEEDBACK pin current at start-up is determined by the value of RSTART because the voltage on CSTART will be zero. For minimum start-up peak currents, this current should match or slightly exceed the DT/BF pin current so that start-up switching frequency begins at fMAX. The resulting value of RSTART will be approximately 10% lower than the value of the pull-up resistor on the DT/BF pin. The frequency will slide down as CSTART charges. If RSTART is smaller than that which provides start-up at fMAX, it will create an additional delay before start-up switching. Please see the PIXls HiperLCS spreadsheet. Resistor RLOAD provides a load on the optocoupler, and speeds up the large signal transient response during burst mode. The recommended value is ~4.7 kW. Diode D1 prevents RLOAD from loading RFMIN when the optocoupler is cut off. Diode D1 can be omitted and a combination of resistor values found to achieve the desired fMIN but the resulting tolerances will be poor. Resistor ROPTO will improve the ESD and surge immunity of the PSU. It also improves burst mode output ripple voltage. Its maximum value must be such that the FEEDBACK pin current is equal to the DT/BF pin current when the optocoupler is in saturation and the FEEDBACK pin is at 2.0 V (please see PIXls HiperLCS spreadsheet). This is to ensure that if the HiperLCS does not exit start-up mode, because the feedback loop did not allow the switching frequency to drop below fSTOP, then it can regulate at light load by bursting at fMAX. Note however bursting at fMAX can lead to high internal dissipation due to loss of ZVS and should be avoided. See Figure 20. Capacitor CSTART should be sized at the minimum possible value that exhibits a 7 consecutive-cycle peak current at start-up that is just below the peak current measured at brown-out and full load. A larger value will slow down start-up and will make it more likely that fSTOP is not reached. This can prevent exiting start-up mode when the HiperLCS is powered up at high-line and minimum load, and may subsequently cause the HiperLCS to burst at fMAX instead of between fSTART and fSTOP. 100 RFB (k ) 50 20 10 4 20 50 100 200 500 1000 Frequency (kHz) Figure 21. VREF to FB External Resistance vs. Frequency. In order to calculate RFMIN and RSTART, use the following equation which describes nominal resistance from FEEDBACK pin to VREF pin, vs. frequency: R FB = 3574 f ^0.6041 + 0.1193 # LOG^ f hh Where RFB is in kW and f is in kHz. To calculate the minimum RSTART, which produces start-up at fMAX, use the above equation with f = fMAX from the equation relating dead-time and fMAX. To set fMIN, use the above equation with f = fMIN × 0.93. Where 0.93 is to ensure that, despite the worst case frequency tolerance of -7%, the frequency can go below fMIN, guaranteeing regulation at VBROWNOUT. Using the resulting calculated value for RFB, calculate RFMIN: R FMIN = R FB - R START The sum of RFMIN and RSTART determines fMIN. 15 www.powerint.com Rev. B 062011 PI-6151-060911 start-up frequency, and fSTART, which is the burst mode start (lower) threshold frequency. 300 PI-6463-060711 LCS700-708 It should be noted that the 4.7 nF decoupling capacitor, CFB (see Figure 19), in conjunction with the 2.5 kW input resistance presented by the FEEDBACK pin, form a pole in the LLC transfer function. This can add significant phase lag to the feedback loop. A typical value for a 250 kHz design with a 3 kHz crossover frequency is 4.7 nF. To prevent loop instability, the value of the 4.7 nF capacitor should not be increased arbitrarily. At the other extreme, insufficient FEEDBACK pin bypass capacitance or poor layout may cause duty cycle asymmetry. Start-Up and Auto-Restart At start-up and during the off-state of the auto-restart cycle, the FEEDBACK pin is internally pulled up to the VREF pin. This keeps the output MOSFETs off and discharges the soft-start capacitor, in preparation for soft-start. At start-up, this state remains for 1024 clock cycles at frequency fMAX. During the off-state of auto-restart, or if the OV/UV or IS pin is triggered while the VCC remains above its UVLO threshold, this state remains for 131,072 clock cycles. After 1024 or 131,072 cycles (as the case may be), the HiperLCS turns off the internal pull-up transistor, the soft-start capacitor begins to charge, the output MOSFETs switch at fMAX, current in the FEEDBACK pin diminishes, the frequency begins to drop, and the PSU output rises. For example, for fMAX = 800 kHz, the start-up delay after VCC power-up is 1.3 ms. If IS, or the OV/UV pin are tripped, autorestart is invoked, with a restart delay of 164 ms. The FEEDBACK pin has a current limit equal to the current flowing into the DT/BF pin. This limits the maximum current that charges the soft-start capacitor at start-up. If RSTART is smaller than that which allows the FEEDBACK pin current to match the DT/BF pin current at start-up, an additional delay is introduced. CSTART will charge at the current limit, and switching will only commence when the FEEDBACK pin voltage drops below 2.0 V. Thus the designer can add an additional start-up delay if desired. As the soft-start capacitor continues to charge, the current through RSTART and thus the FEEDBACK pin decreases, reducing switching frequency. The output voltage climbs; and when the feedback loop closes, the optocoupler conducts and starts controlling the switching frequency thus the output voltage. Remote-Off Remote-off can be invoked by pulling down the OV/UV pin to ground, or by pulling up the IS pin to >0.9 V. Both will invoke a 131,072 cycle restart cycle. VCC can also be pulled down to shut the device off, but when it is pulled up, the FEEDBACK pin is pulled up to the VREF pin to discharge the soft-start capacitor for only 1024 fMAX clock cycles. If this scheme is used, the designer must ensure that the time the VCC is pulled down, plus 1024 cycles, is sufficient to discharge the soft-start capacitor, or if not, that the resulting lower starting frequency is high enough so as not to cause excessive primary currents that may cause the over-current protection to trip. 6 4 2 PI-6471-052411 A B 80 70 60 Amps (A) -2 -4 -6 -8 Output Voltage 40 30 20 10 0 0 0.5 1 1.5 2 -10 Time (ms) 2.5 3 3.5 4 4.5 5 Figure 22. Typical Start-up Waveform. Observe Initial Current Spike ‘A’ to Ensure it is Below the 1-Cycle Current Limit. A Higher fMAX Reduces it. Size the Soft-Start Capacitor so that the Peak of ‘B’ is just Below the Peak Current at VBROWNOUT at Full Load. IS Pin The IS pin has 2 thresholds: nominally 0.5 V and 0.9 V. The IS pin can tolerate small negative voltages and currents, and thus does not need a peak detector or rectifier circuit. The pin has a reverse-biased diode to ground equivalent circuit, and can tolerate a maximum negative current of 5 mA. The primary current is sampled by a primary, B- referenced current sense resistor, or by a capacitor current divider + current sense resistor combination circuit. In order to limit the negative current to 5 mA, a current limiting resistor between the sense resistor and the IS pin is necessary, with a minimum value of 220 W. Using the minimum value maximizes the IS pin bypass capacitor value and thus pin noise rejection, for a given RC pole frequency. The IS pin will invoke a restart if it sees 7 consecutive pulses >0.5 V. It will also invoke a restart if a single pulse exceeds 0.9 V. The minimum pulse detection time is nominally 30 ns – i.e. the pulses must be higher than the threshold voltage for >30 ns. The “capacitive divider” circuit in Figure 23 reduces power dissipation and improves efficiency over a simple current sense resistor circuit. The two capacitors, main resonant capacitor C11, and sense capacitor C12, form a current divider. The portion of the primary current routed through C12 is C12 . C11 + C12 Consequently, the voltage at the IS pin is equal to IP # C12 C11 + C12 # R11, where IP is the primary current flowing from the HB pin through the transformer primary. The current in the sense capacitor passes through sense resistor R11. Resistor R11 is the main means for tuning current limit. The signal on R11, an AC voltage, passes through low-pass filter R12 and C7, to the IS pin. Note that R11 is returned to the GROUND pin and not to SOURCE pin. 16 Rev. B 062011 www.powerint.com Volts (V) 0 Primary Current 50 LCS700-708 The recommended series resistor value of 220 W and the bypass capacitor form a low-pass filter, and its time constant must not cause significant attenuation of the current sense signal at the nominal operating frequency. The effect of the attenuation is greatest for the first pulse in the start-up current waveform, and can also affect proper shutdown during short-circuit testing, which typically trips the 7-cycle current limit. Place a closecoupled probe across the IS pin bypass capacitor and compare the waveform to the primary current. Burst Mode Operation and Tuning Burst mode will produce a typical waveform such as in Figure 24. During the burst pulse train, the switching frequency rises from fSTART to fSTOP. LLC Transformer HB Pin PI-6469-062811 24.1 24.0 Output Ripple Voltage (V) HB Voltage (V) 400 300 23.9 200 100 0 0 Time ( s) 25 50 Figure 25. Zoom in of First Few Switching Cycles of Burst Pulse Train of Figure 24. The First 2 Cycles Show That the High-Side Driver has not Turned on yet. The Switching Frequency of the First Few Cycles is fSTART, 335 kHz in This Case. The Ringing on the Output is from the Output Filter. C12 47 pF 1 kV IS Pin GROUND Pin S Pin C7 1 nF R12 220 Ω R11 24 Ω C11 6.8 nF 1 kV PI-6161-051711 If the initial output ripple spike at the beginning of the burst pulse train is ignored, the output ripple somewhat resembles a sawtooth. See the output ripple waveform in Figure 24. When the HiperLCS is switching, the output rises. When it stops switching, the output falls. The top of the sawtooth is where the burst pulse train ends, because the feedback loop has commanded a frequency = fSTOP. The bottom of the sawtooth is where the burst pulse train begins, because the feedback loop has commanded a frequency = fSTART. As such, the burst mode control resembles a hysteretic controller, where the top and bottom of the sawtooth are fixed by the feedback loop gain. The downward slope of the sawtooth is merely the output capacitors discharging into the load, with dv/dt: Figure 23. Capacitive Divider Current Sense Circuit. PI-6468-062811 I = C # dv dt Where I = load current. C is the total output capacitance. 24.1 24.0 HB Voltage (V) 400 300 23.9 The upward slope of the sawtooth is dependent on the difference between the current delivered by the powertrain, and the current drawn by the load. For a given design, the upward slope increases with input voltage. The burst repetition rate (frequency) then increases with load. When the load reaches a point where the powertrain can regulate at a frequency 30 N applied to the center of the package. 3. Junction to case thermal resistance is based on hottest junction, case temperature measured at center of package back surface. 4. Temperature difference between hottest junction and overtemperature sensor. 5. Thermal resistance values are preliminary and subject to change. Parameter Half-Bridge Symbol Conditions SOURCE = 0 V; TJ = 0 to 100 °C (Unless Otherwise Specified) LCS700 LCS701 LCS702 LCS703 LCS705 LCS708 LCS700, I = 0.8 A LCS701, I = 1.2 A LCS702, I = 1.6 A LSC703, I = 2.0 A LCS705, I = 3.0 A LCS708, I = 4.8 A VCC = 12 V, VCCH = 12 V Min Typ Max Units OFF-State Current IDSS Measured from D to HB or from HB to S TJ = 100 °C, VCC = 12 V, VCCH = 12 V, VD = 424 V ON-State Resistance RDS(ON) Measured from D to HB or from HB to S VCC = 12 V, VCCH = 12 V, TJ = 25 °C 1.53 1.00 0.74 0.60 0.40 0.26 60 60 65 80 120 200 1.82 1.24 0.92 0.73 0.49 0.31 mA W 19 www.powerint.com Rev. B 062011 LCS700-708 Conditions SOURCE = 0 V; TJ = 0 to 100 °C (Unless Otherwise Specified) Half-Bridge (cont.) Measured from D to HB or from HB to S VCC = 12 V, VCCH = 12 V, TJ = 100 °C LCS700, I = 0.8 A LCS701, I = 1.2 A LCS702, I = 1.6 A LCS703, I = 2.0 A LCS705, I = 3.0 A LCS708, I = 4.8 A LCS700 LCS701 LCS702 LCS703 LCS705 LCS708 LCS700, I = 0.8 A LCS701, I = 1.2 A LCS702, I = 1.6 A LSC703, I = 2.0 A LCS705, I = 3.0 A LCS708, I = 4.8 A Power Supply VCC Supply Voltage Range VCCH Supply Voltage Range Start-Up Current Inhibit Current VCC VCCH ICC(OFF) ICC(INHIBIT) See Note C See Note C Undervoltage lockout state: VCC = 8 V VCC = 12 V, OV/UV < VSD(L) Typical at VCC = 12 V Maximum at VCC = 15 V Measured at 300 kHz, HB Open and VD = 15 V LCS700 LCS701 LCS702 LCS703 LCS705 LCS708 LCS700 LCS701 LCS702 LSC703 LCS705 LCS708 11.4 11.4 12 12 0.85 1.35 4.0 4.4 4.9 5.4 6.6 8.8 3.4 3.9 4.3 4.7 5.8 7.8 15 15 1 1.7 5.2 5.8 6.5 7.1 8.8 11.8 4.6 5.2 5.8 6.4 7.9 10.7 V V mA mA 2.15 1.42 1.05 0.85 0.58 0.36 134 201 268 335 503 804 1.15 1.15 1.15 1.15 1.15 1.15 2.63 1.78 1.33 1.06 0.71 0.45 VCC = 12 V, VCCH = 12 V Parameter Symbol Min Typ Max Units ON-State Resistance RDS(ON) W Half-Bridge Capacitance CHB Effective half-bridge capacitance. VHB swinging from 0 V to 400 V or 400 V to 0 V, See Note A pF Diode Forward Voltage VFWD Measured from HB to D or from S to HB TJ = 125 °C V VCC Operating Current ICC(ON) mA VCCH Operating Current ICCH(ON) Typical at VCCH = 12 V Maximum at VCCH = 15 V Measured at 300 kHz, HB Open and VD = 15 V mA VCC Supply Undervoltage Lockout VCC Start Threshold VCC Shutdown Threshold VCC Start-Up/Shutdown Hysteresis 20 Rev. B 062011 VUVLO(+) VUVLO(-) VUVLO(HYST) Device exits UVLO state when VCC exceeds UVLO+ Device enters UVLO state when VCC falls below UVLO+ 10 9.1 0.70 10.7 9.8 0.90 11.4 10.5 1.20 V V V www.powerint.com LCS700-708 Conditions SOURCE = 0 V; TJ = 0 to 100 °C (Unless Otherwise Specified) VCCH Supply Undervoltage Lockout VCCH Start Threshold VCCH Shutdown Threshold VCCH Start-Up/ Shutdown Hysteresis OV/UV Overvoltage Shutdown Threshold OV/UV Overvoltage Recovery Threshold OV/UV Undervoltage Start Threshold OV/UV Undervoltage Shutdown Threshold OV/UV Pin Input Resistance Reference Reference Voltage Current Source Capability of VREF Pin VREF Capacitance LLC Oscillator Frequency Range Accuracy of Minimum Frequency Limit Accuracy of Maximum Frequency Limit Duty Balance Dead-TimeB DT/BF Control Current Range FRANGE FMIN(ACC) FMIN(ACL) FMAX(ACC) DLLC tD IDT/BF ISTOP1 IFB Threshold to Stop LLC Switching ISTOP2 ISTOP3 Threshold applies after exiting soft-start mode for burst setting BT1 Threshold applies after exiting soft-start mode for burst setting BT2 Threshold applies after exiting soft-start mode for burst setting BT3 RFB = 37.9 kW to VREF , 180 kHz RFB = 154 kW to VREF , 50 kHz IFB = IDT/BF, RFMAX = 12.5 kW, FMAX = 510 kHz Duty symmetry of the half-bridge waveform, CFB = 4.7 nF, CDT/BF = 4.7 nF, 250 kHz. Use recommended layout RFMAX = 7 kW, RBURST = 39.6 kW 30 49.8 43.9 37.1 % of IDT/BF 25 -5.0 -7.5 -7.5 1000 5.0 7.5 7.5 kHz % % VREF IREF CREF Required external coupling on VREF pin 1 IREF = 4 mA 3.25 3.40 3.50 4 V mA mF VUVLO(H+) VUVLO(H-) VUVLO(H)HYST Driver exits UVLO state when VCCH exceeds UVLOH+ Driver enters UVLO state when VCCH falls below UVLOH8.2 7.4 0.65 8.5 7.5 0.75 8.9 8.1 1.00 V V V VCC = 12 V, VCCH = 12 V Parameter Symbol Min Typ Max Units High-Voltage Supply Undervoltage/Overvoltage Enable VOV(H) VOV(L) VSD(H) VSD(L) RIN(OVUV) Overvoltage assertion threshold Overvoltage de-assertion threshold Undervoltage de-assertion threshold Undervoltage assertion threshold OV/UV pin resistance to G 129 124 2.35 77 3.0 131 126 2.40 79 5.0 133 128 2.45 81 6.6 % of VSD(H) % of VSD(H) V % of VSD(H) MW 49 330 51 % ns 430 mA 21 www.powerint.com Rev. B 062011 LCS700-708 Conditions SOURCE = 0 V; TJ = 0 to 100 °C (Unless Otherwise Specified) LLC Oscillator (cont.) IFB Threshold Hysteresis IBURST(HYST) VBT1 DT/BF Voltage to Program Burst Setting VBT2 VBT3 Time Constant for the Combination of RFMAX, RBURST and the Decoupling Cap on DT/BF FB Current Maximum FB Control Current Range FB Virtual Voltage FB Input Resistance FB Input Resistance During Soft-Start Over-Current Protection Fast Over-Current Fault Voltage Threshold4 Slow Over-Current Fault Voltage Threshold Over-Current Fault Pulse Width Over-Temperature Shutdown ThresholdA VIS(F) 0.855 0.905 0.955 V ISTART is IBURST(HYST) below ISTOP Required VDT/BF at start-up to enable burst setting BT1 Required VDT/BF at start-up to enable burst setting BT2 Required VDT/BF at start-up to enable burst setting BT3 This time constant must be less than the specified maximum to ensure correct setting of burst mode. Determines the maximum control frequency that can be set by IFB. IFB is limited by the current into DT/BF FB input appears as RIN(FB) in series with VFB. 30 mA < IFB < IDT/BF FB input appears as RIN(FB) in series with VFB. 30 mA < IFB < IDT/BF FB input appears as RFB(SS) in series with VREF during the soft-start delay interval or when OV/UV < VSD or OV/UV > VOV 15 0.65 2.5 100 430 5 93.5 88.5 83.5 6.25 95 90 85 8 96.3 91.3 86.3 % of VREF % of IDT/BF VCC = 12 V, VCCH = 12 V Parameter Symbol Min Typ Max Units RCDT/BF 100 ms IFB IFB VFB RIN(FB) RFB(SS) %IDT/BF mA V kW 750 W VIS(S) tIS 7 LLC clock cycle debounce Minimum time VIS exceeds VIS(F)/VIS(S) per cycle to trigger fault protection 0.455 0.505 0.555 V 30 ns Over-Temperature Protection TOT 140 °C NOTES: A. Guaranteed by design. B. Typical apparent dead-time at the HB pin under resonant ZVS conditions. C. VCC/VCCH operating range to achieve power capabilities specified in data sheet power table. 22 Rev. B 062011 www.powerint.com LCS700-708 PI-6181-112910 PI-6182-112910 18 16 14 16 14 12 Current (mA) 10 8 6 4 2 0 0 100 20 300 400 500 600 700 800 LCS700 LCS701 LCS702 LCS703 LCS705 LCS708 Current (mA) 12 10 8 6 4 2 0 0 100 20 300 400 500 600 700 800 LCS700 LCS701 LCS702 LCS703 LCS705 LCS708 Frequency (kHz) Figure 27. VCC Current vs. Frequency. Frequency (kHz) Figure 28. VCCH Current vs. Frequency. PI-6183-112910 800 700 1000 Power (mW) 600 500 400 300 200 100 0 0 100 20 300 400 500 600 700 800 LCS700 LCS701 LCS702 LCS703 LCS705 LCS708 Capacitance (pF) 800 600 400 200 0 0 50 100 150 200 250 LCS700 LCS701 LCS702 LCS703 LCS705 LCS708 300 350 400 Frequency (kHz) Figure 29. Control Power vs. Frequency. Half-Bridge Voltage (V) Figure 30. Half-Bridge Small Signal Capacitance vs. Half-Bridge Voltage. 23 www.powerint.com Rev. B 062011 PI-6184-112910 900 1200 24 C Rev. B 062011 eSIP-16C (H Package) 0.214 (5.44) Ref. 2 A 0.653 (16.59) 0.647 (16.43) 0.081 (2.06) 0.077 (1.96) B LCS700-708 2 Detail A 0.290 (7.37) Ref. 0.519 (13.18) Ref. 0.016 (0.41) Ref. Pin 1 I.D. 0.325 (8.25) 0.320 (8.13) 0.210 (5.33) Ref. 0.140 (3.56) 0.120 (3.05) 13 14 16 0.207 (5.26) 0.187 (4.75) 1 34 5 6 78 9 10 11 3 0.038 (0.97) 0.118 (3.00) SIDE VIEW 0.056 (1.42) Ref. 0.016 (0.41) 13× 0.011 (0.28) 0.020 M 0.51 M C 0.047 (1.19) 0.076 (1.93) 0.012 (0.30) Ref. 0.024 (0.61) 13× 0.019 (0.48) 0.010 M 0.25 M C A B BACK VIEW 0.038 (0.97) 3 4 FRONT VIEW 0.029 Dia Hole 0.062 Dia Pad 0.118 (3.00) 0.019 (0.48) Ref. 10° Ref. All Around 0.021 (0.53) 0.019 (0.48) 0.060 (1.52) Ref. 0.020 (0.50) 0.076 (1.93) PCB FOOT PRINT Dimensions in inches, (mm). All dimensions are for reference. 0.023 (0.58) 0.027 (0.70) Detail A (Scale = 9×) 0.048 (1.22) 0.046 (1.17) 0.628 (15.95) Ref. www.powerint.com END VIEW Notes: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. Maximum mold protrusion is 0.007 [0.18] per side. 3. Dimensions noted are inclusive of plating thickness. 4. Does not include interlead flash or protrusions. 5. Controlling dimensions in inches (mm). PI-5639-031011 LCS700-708 Part Ordering Information • Hiper Product Family • LCS Series Number • Package Identifier H G LCS 700 H G - TL Blank Plastic eSIP-16C Halogen Free and RoHS Compliant Standard Configurations • Pin Finish • Tape & Reel and Other Options 25 www.powerint.com Rev. B 062011 Revision B Notes Initial Release Date 06/20/11 For the latest updates, visit our website: www.powerint.com Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. Patent Information The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations patents may be found at www.powerint.com. Power Integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm. Life Support Policy POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein: 1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or death to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, CAPZero, SENZero, LinkZero, HiperPFS, HiperTFS, HiperLCS, Qspeed, EcoSmart, Clampless, E-Shield, Filterfuse, StakFET, PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©2011, Power Integrations, Inc. Power Integrations Worldwide Sales Support Locations World Headquarters 5245 Hellyer Avenue San Jose, CA 95138, USA. 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