LNK562-564
LinkSwitch-LP
®
Energy Efficient Off-Line Switcher IC for
Linear Transformer Replacement
Product Highlights
Lowest System Cost and Advanced Safety Features
• Lowest component count switcher
• Very tight parameter tolerances using proprietary IC
trimming technology and transformer construction
techniques enable Clampless™designs – decreases
component count/system cost and increases efficiency
• Meets industry standard requirements for thermal overload
protection – eliminates the thermal fuse used with linear
transformers or additional components in RCC designs
• Frequency jittering greatly reduces EMI – enables low cost
input filter configuration
• Meets HV creepage requirements between DRAIN and all
other pins, both on the PCB and at the package
• Proprietary E-Shield™ transformer eliminates Y-capacitor
Superior Performance over Linear and RCC
• Hysteretic thermal shutdown protection – automatic
recovery improves field reliability
• Universal input range allows worldwide operation
• Auto-restart reduces delivered power by >85% during
short circuit and open loop fault conditions
• Simple ON/OFF control, no loop compensation needed
• High bandwidth provides fast turn on with no overshoot
and excellent transient load response
EcoSmart – Energy Efficiency Technology
• Easily meets all global energy efficiency regulations with
no added components
• No-load consumption 1).
6. A suitably sized core to allow a practical transformer design
(see Table 2).
7. The part is board mounted with SOURCE pins soldered
to a sufficient area of copper to keep the SOURCE pin
temperature at or below 100 °C.
8. Ambient temperature of 50 °C for open frame designs and an
internal enclosure temperature of 60 °C for adapter designs.
LinkSwitch-LP Device
Core Size
LNK562
LNK563
LNK564
EE13
1.1 W
1.4 W
1.7 W
EE16
1.3 W
1.7 W
2W
EE19
1.9 W
2.5 W
3W
Table 2. Estimate of Transformer Power Capability vs.
LinkSwitch-LP Device and Core Size at a Flux Density of
1500 Gauss (150 mT).
Below a value of 1, KP is the ratio of ripple to peak primary
current. Above a value of 1, KP is the ratio of primary MOSFET
OFF time to the secondary diode conduction time. Due to
the flux density requirements described below, typically a
LinkSwitch-LP design will be discontinuous, which also has
the benefit of allowing lower-cost fast (vs. ultra-fast) output
diodes and reducing EMI.
Clampless Designs
Clampless designs rely solely on the drain node capacitance
to limit the leakage inductance induced peak drain-to-source
voltage. Therefore the maximum AC input line voltage, the
value of VOR, the leakage inductance energy, (a function of
leakage inductance and peak primary current), and the primary
winding capacitance determine the peak drain voltage. With no
significant dissipative element present, as is the case with an
external clamp, the longer duration of the leakage inductance
ringing can increase EMI.
The following requirements are recommended for a universal
input or 230 VAC only Clampless design:
1. Clampless designs should only be used for PO ≤ 2.5 W using
a VOR of ≤ 90 V
2. For designs with PO ≤ 2 W, a two-layer primary must be
used to ensure adequate primary intra-winding capacitance
in the range of 25 pF to 50 pF.
3. For designs with 2 < PO ≤ 2.5 W, a bias winding must be added
to the transformer using a standard recovery rectifier diode
(1N4003– 1N4007) to act as a clamp. This bias winding may
also be used to externally power the device by connecting
a resistor from the bias winding capacitor to the BYPASS
pin. This inhibits the internal high-voltage current source,
reducing device dissipation and no-load consumption.
4. For designs with PO >2.5 W, Clampless designs are not practical
and an external RCD or Zener clamp should be used.
5. Ensure that worst-case, high line, peak drain voltage is below
the BVDSS specification of the internal MOSFET and ideally
≤ 650 V to allow margin for design variation.
VOR (Reflected Output Voltage), is the secondary output plus
output diode forward voltage drop that is reflected to the
primary via the turns ratio of the transformer during the diode
conduction time. The VOR adds to the DC bus voltage and the
leakage spike to determine the peak drain voltage.
Audible Noise
The cycle skipping mode of operation used in LinkSwitch-LP
can generate audio frequency components in the transformer.
To limit this audible noise generation, the transformer should
be designed such that the peak core flux density is below
1500 Gauss (150 mT). Following this guideline and using the
standard transformer production technique of dip varnishing,
practically eliminates audible noise. Vacuum impregnation
of the transformer is not recommended, as it does not provide
any better reduction of audible noise than dip varnishing. And
although vacuum impregnation has the benefit of increased
transformer capacitance (which helps in Clampless designs),
it can also upset the mechanical design of the transformer,
especially if shield windings are used. Higher flux densities are
possible, increasing the power capability of the transformers
above what is shown in Table 2. However careful evaluation of
the audible noise performance should be made using production
transformer samples before approving the design.
Ceramic capacitors that use dielectrics such as Z5U, when used
in clamp circuits, may also generate audio noise. If this is the
case, try replacing them with a capacitor having a different
dielectric or construction, for example a film type.
Bias Winding Feedback
To give the best output regulation in bias winding designs, a
slow diode such as the 1N400x series should be used as the
rectifier. This effectively filters the leakage inductance spike
and reduces the error that this would give when using fast
recovery time diodes. The use of a slow diode is a requirement
in Clampless designs.
5
Rev. H 11/08
LNK562-564
TOP VIEW
S
S
Tr a n s f o r m e r
FB
LinkSwitch-LP
Y1Capacitor
D
CBP
BP
Input Filter
Capacitor
S
S
-
HV DC +
INPUT
+
DC
OUT
-
Output Filter
Capacitor
Maximize hatched copper
areas (
) for optimum
heatsinking
PI-4157-101305
Figure 6. Recommended Circuit Board Layout for LinkSwitch-LP using P Package (Assumes a HVDC Input Stage).
LinkSwitch-LP Layout Considerations
Layout
See Figure 6 for a recommended circuit board layout for
LinkSwitch-LP (P & G package).
Single Point Grounding
Use a single point ground connection from the input filter
capacitor to the area of copper connected to the SOURCE pins.
Bypass Capacitor (CBP)
The BYPASS pin capacitor should be located as near as possible
to the BYPASS and SOURCE pins.
Primary Loop Area
The area of the primary loop that connects the input filter
capacitor, transformer primary and LinkSwitch-LP together
should be kept as small as possible.
Primary Clamp Circuit
An external clamp may be used to limit peak voltage on the
6
Rev. H 11/08
DRAIN pin at turn off. This can be achieved by using an RCD
clamp or a Zener (~200 V) and diode clamp across the primary
winding. In all cases, to minimize EMI, care should be taken
to minimize the circuit path from the clamp components to the
transformer and LinkSwitch-LP.
Thermal Considerations
The copper area underneath the LinkSwitch-LP acts not only as
a single point ground, but also as a heatsink. As it is connected
to the quiet source node, this area should be maximized for
good heat sinking of LinkSwitch-LP. The same applies to the
cathode of the output diode.
Y-Capacitor
The placement of the Y-type cap should be directly from the
primary input filter capacitor positive terminal to the common/
return terminal of the transformer secondary. Such a placement
will route high magnitude common-mode surge currents away
from the LinkSwitch-LP device. Note: If an input pi (C, L, C)
EMI filter is used, then the inductor in the filter should be placed
between the negative terminals on the input filter capacitors.
LNK562-564
TOP VIEW
FB
Tr a n s f o r m e r
S
S
Input Filter
Capacitor
S
S
Y1Capacitor
BP
LinkSwitch-LP
D
CBP
-
+
DC
OUT
HV DC
INPUT
+
-
Maximize hatched copper
areas (
) for optimum
heatsinking
Output Filter
Capacitor
PI-4582-021407
Figure 7. Recommended Circuit Board Layout for LinkSwitch-LP using D Package (Assumes a HVDC Input Stage).
Output Diode
For best performance, the area of the loop connecting the
secondary winding, the output diode and the output filter
capacitor should be minimized. In addition, sufficient copper
area should be provided at the anode and cathode terminals
of the diode for heat sinking. A larger area is preferred at the
quiet cathode terminal. A large anode area can increase highfrequency radiated EMI.
Quick Design Checklist
As with any power supply design, all LinkSwitch-LP designs
should be verified on the bench to make sure that component
specifications are not exceeded under worst-case conditions. The
following minimum set of tests is strongly recommended:
1. Maximum drain voltage – Verify that VDS does not exceed
650 V at the highest input voltage and peak (overload) output
power. A 50 V margin to the 700 V BVDSS specification gives
margin for design variation, especially in Clampless designs.
2. Maximum drain current – At maximum ambient
temperature, maximum input voltage and peak output
(overload) power, verify drain current waveforms for any
signs of transformer saturation and excessive leading-edge
current spikes at startup. Repeat under steady state conditions
and verify that the leading-edge current spike event is below
ILIMIT(MIN) at the end of the tLEB(MIN). Under all conditions, the
maximum DRAIN current should be below the specified
absolute maximum ratings.
3. Thermal Check – At specified maximum output
power, minimum input voltage and maximum ambient
temperature, verify that the temperature specifications
are not exceeded for LinkSwitch-LP, transformer, output
diode and output capacitors. Enough thermal margin
should be allowed for part-to-part variation of the RDS(ON) of
LinkSwitch-LP as specified in the data sheet. Under low line
andmaximumpower,amaximumLinkSwitch-LPSOURCEpin
temperature of 100 °C is recommended to allow for
these variations.
Design Tools
Up-to-date information on design tools can be found at the
Power Integrations web site: www.powerint.com.
7
Rev. H 11/08
LNK562-564
ABSOLUTE MAXIMUM RATINGS(1,6)
DRAIN Voltage ..................................................700 V
Peak DRAIN Current...................................200 mA (375 mA)(2)
Peak Negative Pulsed Drain Current (see Fig. 11) ... 100 mA(3)
FEEDBACK Voltage .........................................-0.3 V to 9 V
FEEDBACK Current.............................................100 mA
BYPASS Voltage ..........................................-0.3 V to 9 V
Storage Temperature .......................................... -65 °C to 150 °C
Operating Junction Temperature(4) ..................... -40 °C to 150 °C
Lead Temperature(5) ........................................................260 °C
Notes:
1. All voltages referenced to SOURCE, TA = 25 °C.
2. The higher peak DRAIN current is allowed while the
DRAIN voltage is simultaneously less than 400 V.
3. Duration not to exceed 2 μs.
4. Normally limited by internal circuitry.
5. 1/16 in. from case for 5 seconds.
6. Maximum ratings specified may be applied, one at a time,
without causing permanent damage to the product.
Exposure to Absolute Maximum Rating conditions for
extended periods of time may affect product reliability.
THERMAL IMPEDANCE
Thermal Impedance: P or G Package:
(θJA) ........................... 70 °C/W(3); 60 °C/W(4)
(θJC)(1) ............................................... 11 °C/W
D Package:
(θJA) ..................... .... 100 °C/W(3); 80 °C/W(4)
(θJC)(2) ............................................... 30 °C/W
Notes:
1. Measured on pin 2 (SOURCE) close to plastic interface.
2. Measured on pin 8 (SOURCE) close to plastic interface.
3. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad.
4. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad.
Conditions
Parameter
Symbol
SOURCE = 0 V; TJ = -40 to 125 °C
See Figure 8
(Unless Otherwise Specified)
Min
Typ
Max
Units
61
77
93
66
83
100
71
89
107
kHz
CONTROL FUNCTIONS
Output
Frequency
Ratio of Output
Frequency At AutoRestart to fOSC
Frequency Jitter
Maximum Duty
Cycle
FEEDBACK Pin
Turnoff Threshold
Current
FEEDBACK Pin
Voltage at Turnoff
Threshold
DRAIN Supply
Current
8
Rev. H 11/08
fOSC
fOSC(AR)
TJ = 25 °C
Average
VFB =1.69 V
LNK562
LNK563
LNK564
TJ = 25 °C, VFB = VFB(AR)
48
%
Peak-Peak Jitter, TJ = 25 °C
5
%
%
DCMAX
S2 Open
66
70
IFB
TJ = 25 °C
See Note A
56
70
84
μA
VFB
TJ = 0 to 125 °C
See Note A
1.60
1.69
1.78
V
IS1
VFB ≥ 2 V
(MOSFET Not Switching)
See Note B
160
220
μA
IS2
FEEDBACK Open
(MOSFET Switching)
See Notes B, C
220
260
μA
LNK562-564
Conditions
Parameter
Symbol
SOURCE = 0 V; TJ = -40 to 125 °C
See Figure 8
(Unless Otherwise Specified)
Min
Typ
Max
Units
CONTROL FUNCTIONS (cont.)
BYPASS Pin
Charge Current
ICH1
VBP = 0 V, TJ = 25 °C, See Note D
-5.5
-3.3
-1.8
ICH2
VBP = 4 V, TJ = 25 °C, See Note D
-3.8
-2.3
-1.0
mA
BYPASS Pin
Voltage
VBP
5.55
5.8
6.10
V
BYPASS Pin
Voltage Hysteresis
VBPH
0.8
0.95
1.2
V
BYPASS Pin
Supply Current
IBPSC
See Note E
84
di/dt = 40 mA/μs
TJ = 25 °C
124
136
148
LNK562
1099
1221
1380
LNK563
1381
1535
1735
LNK564
1665
1850
2091
220
265
135
142
μA
CIRCUIT PROTECTION
Current Limit
Power Coefficient
ILIMIT
2
If
Leading Edge
Blanking Time
tLEB
Thermal Shutdown
Temperature
TSD
Thermal Shutdown
Hysteresis
TSHD
di/dt = 40 mA/μs
TJ = 25 °C
TJ = 25 °C
See Note F
See Note G
mA
A2Hz
ns
150
75
°C
°C
OUTPUT
ON-State
Resistance
OFF-State Drain
Leakage Current
Breakdown Voltage
RDS(ON)
ID = 13 mA
TJ = 25 °C
48
55
TJ = 100 °C
76
88
IDSS
VBP = 6.2 V, VFB ≥2 V, VDS = 560 V,
TJ = 25 °C
BVDSS
VBP = 6.2 V, VFB ≥2 V,
See Note H, TJ = 25 °C
DRAIN Supply
Voltage
Output Enable
Delay
tEN
Output Disable
Setup Time
tDST
50
Ω
μA
700
V
50
V
See Figure 10
17
0.5
μs
μs
9
Rev. H 11/08
LNK562-564
Conditions
Parameter
Symbol
SOURCE = 0 V; TJ = -40 to 125 °C
See Figure 8
(Unless Otherwise Specified)
VFB(AR)
TJ = 25 °C
0.8
V
VFB = VFB(AR)
TJ = 25 °C
100
ms
12
%
Min
Typ
Max
Units
OUTPUT (cont.)
FEEDBACK Pin
Auto-Restart
Threshold Voltage
Auto-Restart
ON-Time
Auto-Restart
Duty Cycle
DCAR
NOTES:
A. In a scheme using a resistor divider network at the FB pin, where RU is the resistor from the FB pin to the rectified
bias voltage and RL is the resistor from the FB pin to the SOURCE pin, the output voltage variation is influenced
by VFB and IFB variations. To determine the contribution from the VFB variation in percent, the following equation
can be used:
J
N
RU + R L m
+
I
KVFB(MAX) c
O
FB(TYP) RU
RL
- 1O
x = 100 # K
KK VFB(TYP) c RU + R L m + I FB(TYP) RU
OO
RL
L
P
To determine the contribution from IFB variation in percent, the following equation can be used:
J
N
RU + R L m
+
I
KVFB(TYP) c
O
FB(MAX) RU
RL
- 1O
y = 100 # K
KK VFB(TYP) c RU + R L m + I FB(TYP) RU
OO
RL
L
P
Since IFB and VFB are independent parameters, the composite variation in percent would be ! x 2 + y 2 .
B. Total current consumption is the sum of IS1 and IDSS when FEEDBACK pin voltage is ≥2 V (MOSFET not
switching) and the sum of IS2 and IDSS when FEEDBACK pin is shorted to SOURCE (MOSFET switching).
C Since the output MOSFET is switching, it is difficult to isolate the switching current from the supply current at the
DRAIN. An alternative is to measure the BYPASS pin current at 6 V.
D. See Typical Performance Characteristics section Figure 16 for BYPASS pin startup charging waveform.
E. This current is only intended to supply an optional optocoupler connected between the BYPASS and FEEDBACK
pins and not any other external circuitry.
F. This parameter is guaranteed by design.
G. This parameter is derived from characterization.
H. Breakdown voltage may be checked against minimum BVDSS by ramping the DRAIN pin voltage up to but not
exceeding minimum BVDSS.
10
Rev. H 11/08
LNK562-564
470 Ω
5W
470 kΩ
D
S1
FB
S2
BP
50 V
S
S
S
S
50 V
0.1 μF
PI-3490-060204
Figure 8. General Test Circuit.
DCMAX
(internal signal)
tP
FB
tEN
VDRAIN
tP =
1
fOSC
PI-3707-112503
Figure 10. Output Enable Timing.
PI-4021-101305
DRAIN Current (mA)
Figure 9. Duty Cycle Measurement.
100
2 μs
0
-100
Time (μs)
Figure 11. Peak Negative Pulsed DRAIN Current
Waveform.
11
Rev. H 11/08
LNK562-564
Typical Performance Characteristics
1.0
PI-2680-012301
1.2
Output Frequency
(Normalized to 25 °C)
PI-2213-012301
1.0
0.8
0.6
0.4
0.2
0.9
0
-50 -25
0
25
50
75 100 125 150
-50
Junction Temperature (°C)
50
75
0.8
100 125
PI-4057-071905
1.1
FEEDBACK Pin Voltage
(Normalized to 25 °C)
1.0
1.0
0.6
0.4
0.2
0
0.9
-50
0
50
100
150
-50 -25
0
Temperature (°C)
25
50
75 100 125 150
Temperature (°C)
Figure 15. FEEDBACK Pin Voltage vs. Temperature.
PI-2240-012301
7
6
5
4
3
2
1
200
175
DRAIN Current (mA)
Figure 14. Current Limit vs. Temperature.
BYPASS Pin Voltage (V)
25
Figure 13. Frequency vs. Temperature.
PI-4164-100505
Current Limit
(Normalized to 25 °C)
1.2
0
Junction Temperature (°C)
Figure 12. Breakdown vs. Temperature.
1.4
-25
PI-3927-083104
Breakdown Voltage
(Normalized to 25 °C)
1.1
25 °C
150
100 °C
125
100
75
50
25
0
0
0
0.2
0.4
0.6
0.8
Time (ms)
Figure 16. BYPASS Pin Startup Waveform.
12
Rev. H 11/08
1.0
0
2
4
6
8 10 12 14 16 18 20
DRAIN Voltage (V)
Figure 17. Output Characteristics.
LNK562-564
Typical Performance Characteristics (cont.)
PI-3928-083104
Drain Capacitance (pF)
1000
100
10
1
0
100
200
300
400
500
600
Drain Voltage (V)
Figure 18. COSS vs. Drain Voltage.
PART ORDERING INFORMATION
LinkSwitch Product Family
LP Series Number
Package Identifier
G
Plastic Surface Mount DIP
P
Plastic DIP
D
Plastic SO-8
Lead Finish
N
Pure Matte Tin (RoHS Compliant)
G
RoHS Compliant and Halogen Free (P and D Package
only)
Tape & Reel and Other Options
Blank Standard Configurations
LNK 562 D N - TL
TL
Tape & Reel, 1 k pcs minimum for G Package. 2.5 k pcs
for D Package. Not available for P Package.
13
Rev. H 11/08
LNK562-564
DIP-8B
⊕ D S .004 (.10)
-E-
Notes:
1. Package dimensions conform to JEDEC specification
MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP)
package with .300 inch row spacing.
2. Controlling dimensions are inches. Millimeter sizes are
shown in parentheses.
3. Dimensions shown do not include mold flash or other
protrusions. Mold flash or protrusions shall not exceed
.006 (.15) on any side.
4. Pin locations start with Pin 1, and continue counter-clockwise to Pin 8 when viewed from the top. The notch and/or
dimple are aids in locating Pin 1. Pin 6 is omitted.
5. Minimum metal to metal spacing at the package body for
the omitted lead location is .137 inch (3.48 mm).
6. Lead width measured at package body.
7. Lead spacing measured with the leads constrained to be
perpendicular to plane T.
.137 (3.48)
MINIMUM
.240 (6.10)
.260 (6.60)
Pin 1
-D-
.367 (9.32)
.387 (9.83)
.125 (3.18)
.145 (3.68)
.057 (1.45)
.068 (1.73)
(NOTE 6)
.015 (.38)
MINIMUM
-TSEATING
PLANE
.100 (2.54) BSC
.008 (.20)
.015 (.38)
.120 (3.05)
.140 (3.56)
.300 (7.62) BSC
(NOTE 7)
.300 (7.62)
.390 (9.91)
.048 (1.22)
.053 (1.35)
.014 (.36)
.022 (.56) ⊕ T E D S .010 (.25) M
P08B
PI-2551-121504
SMD-8B
⊕ D S .004 (.10)
.137 (3.48)
MINIMUM
-E-
.372 (9.45)
.388 (9.86)
⊕ E S .010 (.25)
.240 (6.10)
.260 (6.60)
Pin 1
.100 (2.54) (BSC)
-D-
.367 (9.32)
.387 (9.83)
.057 (1.45)
.068 (1.73)
(NOTE 5)
.125 (3.18)
.145 (3.68)
.032 (.81)
.037 (.94)
.048 (1.22)
.053 (1.35)
Notes:
1. Controlling dimensions are
inches. Millimeter sizes are
shown in parentheses.
2. Dimensions shown do not
include mold flash or other
protrusions. Mold flash or
protrusions shall not exceed
.006 (.15) on any side.
.420
3. Pin locations start with Pin 1,
and continue counter-clock.046 .060 .060 .046
wise to Pin 8 when viewed
from the top. Pin 6 is omitted.
4. Minimum metal to metal
.080
spacing at the package body
Pin 1
for the omitted lead location
is .137 inch (3.48 mm).
.086
5. Lead width measured at
.186
package body.
.286
6. D and E are referenced
Solder Pad Dimensions
datums on the package
body.
.004 (.10)
.009 (.23)
.004 (.10)
.012 (.30)
.036 (0.91)
.044 (1.12)
0°- 8°
G08B
PI-2546-121504
14
Rev. H 11/08
LNK562-564
SO-8C
4
B
0.10 (0.004) C A-B 2X
2
DETAIL A
4.90 (0.193) BSC
A
4
8
D
5
GAUGE
PLANE
2 3.90 (0.154) BSC
SEATING
PLANE
6.00 (0.236) BSC
0-8
C
1.04 (0.041) REF
0.10 (0.004) C D
2X
Pin 1 ID
1
4
0.25 (0.010)
BSC
0.40 (0.016)
1.27 (0.050)
0.20 (0.008) C
2X
7X 0.31 - 0.51 (0.012 - 0.020)
0.25 (0.010) M C A-B D
1.27 (0.050) BSC
1.25 - 1.65
(0.049 - 0.065)
1.35 (0.053)
1.75 (0.069)
o
DETAIL A
0.10 (0.004)
0.25 (0.010)
0.10 (0.004) C
H
7X
SEATING PLANE
0.17 (0.007)
0.25 (0.010)
C
Reference
Solder Pad
Dimensions
+
2.00 (0.079)
+
D07C
4.90 (0.193)
+
1.27 (0.050)
+
Notes:
1. JEDEC reference: MS-012.
2. Package outline exclusive of mold flash and metal burr.
3. Package outline inclusive of plating thickness.
4. Datums A and B to be determined at datum plane H.
5. Controlling dimensions are in millimeters. Inch dimensions
are shown in parenthesis. Angles in degrees.
0.60 (0.024)
PI-4526-040207
Revision Notes
Date
E
1) Final Release Data Sheet
10/05
F
1) Revision of PI-3924
10/05
G
1) Added SO-8C Package
2/07
H
1) Updated Part Ordering Information section with Halogen Free
11/08
15
Rev. H 11/08
LNK562-564
For the latest updates, visit our website: www.powerint.com
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power
Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES
NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered
by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A
complete list of Power Integrations patents may be found at www.powerint.com. Power Integrations grants its customers a license under
certain patent rights as set forth at http://www.powerint.com/ip.htm.
Life Support Policy
POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:
1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii)
whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant
injury or death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or effectiveness.
The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, EcoSmart, Clampless, E-Shield, Filterfuse, StakFET, PI Expert
and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies.
©2007, Power Integrations, Inc.
Power Integrations Worldwide Sales Support Locations
World Headquarters
5245 Hellyer Avenue
San Jose, CA 95138, USA.
Main: +1-408-414-9200
Customer Service:
Phone: +1-408-414-9665
Fax: +1-408-414-9765
e-mail: usasales@powerint.com
China (Shanghai)
Room 1601/1610, Tower 1
Kerry Everbright City
No. 218 Tianmu Road West
Shanghai, P.R.C. 200070
Phone: +86-21-6354-6323
Fax: +86-21-6354-6325
e-mail: chinasales@powerint.com
China (Shenzhen)
Rm A, B & C 4th Floor, Block C,
Electronics Science and
Technology Bldg., 2070
Shennan Zhong Rd,
Shenzhen, Guangdong,
China, 518031
Phone: +86-755-8379-3243
Fax: +86-755-8379-5828
e-mail: chinasales@powerint.com
16
Rev. H 11/08
Germany
Rueckertstrasse 3
D-80336, Munich
Germany
Phone: +49-89-5527-3910
Fax: +49-89-5527-3920
e-mail: eurosales@powerint.com
India
#1, 14th Main Road
Vasanthanagar
Bangalore-560052 India
Phone: +91-80-4113-8020
Fax: +91-80-4113-8023
e-mail: indiasales@powerint.com
Italy
Via De Amicis 2
20091 Bresso MI
Italy
Phone: +39-028-928-6000
Fax: +39-028-928-6009
e-mail: eurosales@powerint.com
Japan
Kosei Dai-3 Bldg.
2-12-11, Shin-Yokomana,
Kohoku-ku
Yokohama-shi Kanagwan
222-0033 Japan
Phone: +81-45-471-1021
Fax: +81-45-471-3717
e-mail: japansales@powerint.com
Korea
RM 602, 6FL
Korea City Air Terminal B/D, 159-6
Samsung-Dong, Kangnam-Gu,
Seoul, 135-728, Korea
Phone: +82-2-2016-6610
Fax: +82-2-2016-6630
e-mail: koreasales@powerint.com
Taiwan
5F, No. 318, Nei Hu Rd., Sec. 1
Nei Hu Dist.
Taipei, Taiwan 114, R.O.C.
Phone: +886-2-2659-4570
Fax: +886-2-2659-4550
e-mail: taiwansales@powerint.com
Europe HQ
1st Floor, St. James’s House
East Street, Farnham
Surrey GU9 7TJ
United Kingdom
Phone: +44 (0) 1252-730-141
Fax: +44 (0) 1252-727-689
e-mail: eurosales@powerint.com
Applications Hotline
World Wide +1-408-414-9660
Singapore
Applications Fax
51 Newton Road
World Wide +1-408-414-9760
#15-08/10 Goldhill Plaza
Singapore, 308900
Phone: +65-6358-2160
Fax: +65-6358-2015
e-mail: singaporesales@powerint.com
工商网监
湘ICP备2023018690号
