LinkSwitch-HP Family
Energy Efficient, High-Power Off-Line Switcher
with Accurate Primary-Side Regulation (PSR)
Product Highlights
EcoSmart™- Energy Efficient
• Multi-mode control maximizes efficiency over full load range
• No-load consumption below 30 mW at 230 VAC (LNK67xx)
• >75% efficiency with 1 W input at 230 VAC
• >50% efficiency with 0.1 W input at 230 VAC
High Design Flexibility for Low System Cost
• Dramatically simplifies power supply designs
• Eliminates optocoupler and all secondary control circuitry
• ±5% or better output voltage tolerance
• 132 kHz operation reduces transformer and power supply size
• Accurate programmable current limit
• Compensation over line limits overload power
• Frequency jittering reduces EMI filter cost
• Fully integrated soft-start for minimum start-up stress
• 725 V MOSFET simplifies meeting derating requirements
(LNK677x)
• 650 V MOSFET for lowest system cost (LNK676x/LNK666x)
• Fast transient response family option (LNK666x)
Extensive Protection Features
• Auto-restart limits power delivery to 3% during overload faults
• Output short-circuit protection (SCP)
• Output overload/over-current protection (OPP, OCP)
• Optional extended shutdown delay time
• Output overvoltage protection (OVP), auto-restart or latching
• Line brown-in/out protection (line UV)
• Line overvoltage (OV) shutdown extends line surge withstand
• Accurate thermal shutdown (OTP), hysteretic or latching
Advanced Green Package Options
• eSIP™-7C package:
• Vertical orientation for minimum PCB footprint
• Simple heat sink mounting using clip or adhesive pad
• eSOP™-12B package:
• Low profile surface mounted for ultra-slim designs
• Heat transfer to PCB via exposed pad and SOURCE pins
• Supports either wave or IR reflow soldering
• eDIP™-12B package:
• Low profile through-hole mounted for ultra-slim designs
• Heat transfer to PCB via exposed pad or optional metal heat sink
• Extended creepage to DRAIN pin
• Heat sink is connected to SOURCE for low EMI
• Halogen free and RoHS compliant
Typical Applications
• LCD Monitor and TV
• Adapter
• Appliances
• Embedded power supplies (DVD, set-top box)
• Industrial
CONTROL
Figure 1.
Typical Application Schematic.
Exposed
Pad
Exposed
Pad
eSIP-7C (E Package)
Figure 2.
eSOP-12B (K Package)
eDIP-12B (V Package)
Package Options.
Output Power Table
230 VAC ±15%
Product4
Heat Sink
LNK6xx3K/V
LNK6xx3K
LNK6xx3E
LNK6xx4K/V
LNK6xx4K
LNK6xx4E
LNK6xx5K/V
LNK6xx5K
LNK6xx5E
LNK6xx6K/V
LNK6xx6K
LNK6xx6E
LNK6xx7K/V
LNK6xx7K
LNK6xx7E
LNK6xx8K/V
LNK6xx8K
LNK6xx8E
LNK6xx9K/V
LNK6xx9K
LNK6xx9E
PCB-W1
PCB-R2
Metal
PCB-W1
PCB-R2
Metal
PCB-W1
PCB-R2
Metal
PCB-W1
PCB-R2
Metal
PCB-W1
PCB-R2
Metal
PCB-W1
PCB-R2
Metal
PCB-W1
PCB-R2
Metal
Adapter
15 W
21 W
21 W
16 W
22 W
30 W
19 W
26 W
40 W
21 W
30 W
60 W
25 W
36 W
853 W
29 W
41 W
983 W
33 W
47 W
1113 W
Open
Frame
25 W
35 W
35 W
28 W
39 W
47 W
30 W
42 W
593 W
34 W
48 W
883 W
41 W
59 W
1173 W
47 W
68 W
1353 W
54 W
77 W
1533 W
85-265 VAC
Adapter
9W
12 W
13 W
11 W
15 W
20 W
13 W
18 W
26 W
15 W
22 W
40 W
19 W
27 W
55 W
21 W
30 W
633 W
25 W
36 W
723 W
Open
Frame
15 W
21 W
27 W
20 W
28 W
36 W
22 W
31 W
45 W
26 W
37 W
683 W
30 W
43 W
903 W
34 W
48 W
1043 W
39 W
56 W
1183 W
Table 1. Output Power Table.
Notes:
1. PCB heat sink with wave soldering.
2. PCB heat sink with IR reflow soldering (exposed pad thermally connected to PCB).
3. Maximum power specified based on proper thermal dissipation.
4. Packages: E: eSIP-7C, K: eSOP-12B, V: eDIP-12B. See Table 2 for all device options.
www.power.com
February 2021
This Product is Covered by Patents and/or Pending Patent Applications.
LinkSwitch-HP
BYPASS
(BP)
LATCH/HYSTERETIC
5.75 V
REGULATOR
THERMAL
SHUTDOWN
FAULT FILTER
BYPASS
PROGRAM
+
5.75 V
4.9 V
MULTI-CYCLE
MODE CONTROL
COMPENSATION
(CP)
DRAIN
(D)
-
MCM
2V
REFERENCE
VOLTAGE
OV
AUTORESTART
SOFTSTART
+
FEEDBACK
(FB)
HIGH GAIN
TRANSCONDUCTANCE
AMPLIFIER
OUTPUT
OVERVOLTAGE
AUTO-RESTART
ERROR
VOLTAGE
+
AMP
S/H
LINE OVERVOLTAGE/
UNDERVOLTAGE
DETECTION
CLOCK
OSC
DCMAX
LUV
LOV
OSCILLATOR
LINE
COMP
PROGRAM/
DELAY
(PD)
GATE
DRIVER
LINE
COMPENSATION
S
Q
R
Q
LEB
+
CUSTOM
SHUTDOWN
DELAY
CURRENT LIMIT
COMPARATOR
PROGRAM
ILIM
CURRENT
LIMIT
SETTING
PI-6565-072012
40% ~ 100%
Figure 3.
SOURCE
(S)
Block Diagram.
LNK
Part Number
LNK6663E/K/V
LNK6664E/K/V
LNK6665E/K/V
LNK6666E/K/V
LNK6667E/K/V
LNK6668E/K/V
LNK6669E/K/V
LNK6763E/K/V
LNK6764E/K/V
LNK6765E/K/V
LNK6766E/K/V
LNK6767E/K/V
LNK6768E/K/V
LNK6769E/K/V
LNK6773E/K/V
LNK6774E/K/V
LNK6775E/K/V
LNK6776E/K/V
LNK6777E/K/V
LNK6778E/K/V
LNK6779E/K/V
6
X
Series
TMCM(OFF) , 6 = 0.5 ms
7 = 4.0 ms
6
0.5 ms
0.5 ms
0.5 ms
0.5 ms
0.5 ms
0.5 ms
0.5 ms
4.0 ms
4.0 ms
4.0 ms
4.0 ms
4.0 ms
4.0 ms
4.0 ms
4.0 ms
4.0 ms
4.0 ms
4.0 ms
4.0 ms
4.0 ms
4.0 ms
2
X
BV
, 6 = 650 V
7 = 725 V
1
DSS
650 V
650 V
650 V
650 V
650 V
650 V
650 V
650 V
650 V
650 V
650 V
650 V
650 V
650 V
725 V
725 V
725 V
725 V
725 V
725 V
725 V
X
E/V/K
Power
Packages
Device
Size
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
eSIP-7C (E), eSOP-12B (K), eDIP-12B (V)
Table 2. Device Part Numbers and Options.
Notes:
1. Minimum breakdown voltage at TJ = +25 °C.
2. TMCM(OFF) = 0.5 ms for fastest transient response, TMCM(OFF) = 4 ms for -250 µA)
Yes
4. Start Switching
(With 15 ms
Soft-Start)
5. Line OV?
(IFB > -1.15 mA
for 2 Cycles)
No
Yes
No
Yes
11. AC
Present?
(IFB > -250 µA)
6. Brown-Out?
(IFB < -100 µA
for 8 Cycles)
No
No
27. Pause 150 ms
(Auto-Restart Off
Period tAR(OFF)1)
7. Regulation
Lost? (VFB < 1.85 V
for 35 ms)
Yes
14. Line OV?
(IFB > -1.15 mA
for 2 Cycles)
12. Start Switching
(With 15 ms
Soft-Start)
No
No
Yes
Yes
20. Start Switching
(With 15 ms
Soft-Start)
8. Stop Switching
15. Brown-Out?
(IFB < -100 µA
for 8 Cycles)
No
No
Yes
16. Regulation
Lost? (VFB < 1.85 V
for 35 ms)
21. Line OV?
(IFB > 1.15 mA
for 2 Cycles)
9. Latch Reset?
(VPD > 3.4 V)
No
Yes
Yes
No
10. Reset Latch
Yes
22. Brown-Out?
(IFB < -100 µA
for 8 Cycles)
PI-6838-101812
17. Stop Switching
No
23. Regulation
Lost? (VFB < 1.85 V
for 35 ms)
No
18. Pause 150 ms
(Auto-Restart Off
Period tAR(OFF)1)
Yes
24. Stop Switching
19. AC Present?
(IFB > -250 µA)
No
Yes
25. Pause 1500 ms
(Auto-Restart Off
Period tAR(OFF)2)
Figure 9.
Line Sensing and Auto-Restart Flow Chart.
6
Rev. F 02/21
www.power.com
LinkSwitch-HP
SW
VFB
Fast AC Reset
VPDTHACR 3.40 V
VPDI
VPDTHRM 1.35 V
VPDTHPDH 1.25 V
tPD Programmable
Shutdown Delay
ID ILIMIT
Remote On/Off
tPDST
VPDTHPDL 0.535 V
t1 t2
t3
t4
t5
t6
t7
t8
t9
t10
PI-6692-101713
Figure 10. PROGRAM (PD) Pin Timing Diagram.
OSC
This is an adjustable frequency oscillator. Based on error
voltage, the frequency will adjust from 32 kHz at light load to
132 kHz at heavy load. The oscillator employes ±5 kHz
frequency jitter to reduce EMI levels.
Current Limit Comparator
This is a high-speed current limit comparator. It compares the
current from the power MOSFET to the internal current reference.
Once the current reaches the threshold the MOSFET on-cycle
is terminated.
Multi-Cycle Modulation (MCM)
When voltage on COMPENSATION pin reaches VC(MCM) (about
1.25 V) the peak drain current is reduced to 25% of programmed
value and the switching frequency approaches fMCM = 32 kHz
(typical). During MCM operation the controller intelligently
maintains a relatively high output sampling rate while reducing
the average switching frequency to keep the output voltage in
regulation. Switching at 25% of the set current limit reduces the
transformer core flux density significantly. This and the intelligent
MCM operation reduce audible noise well below acceptable levels.
LNK666x has a maximum MCM off-time TMCM(OFF) = 0.5 ms (typ.).
The high minimum output sampling rate provides excellent
transient load response from 0% to 50% or 100% of nominal
load while offering typically below 100 mW no-load input power.
LNK67xx has a maximum MCM off-time TMCM(OFF) = 4 ms (typ.).
The lower minimum output sampling rate enables designs
below 30 mW no-load input power while providing fair transient
load performance for load steps from 0% to 50% or 100% of
nominal load.
7
www.power.com
Rev. F 02/21
LinkSwitch-HP
Applications Example
the FEEDBACK pin. This sensing is accomplished by periodically
turning on the power MOSFET to sense input voltage condition
with very short low frequency sampling pulses. During the
forward pulse sampling time the FEEDBACK pin is held to zero
volts by an internal clamp. When negative forward pulse current
exceeds 250 mA, LinkSwitch-HP for two consecutive switching
cycles will initiate start-up with a soft-start sequence that reduces
component stress and allows the output to rise in a smooth
monotonic manner. The desired input voltage for start-up is
determined by the turns ratio of primary winding to feedback
winding and the value of R19.
30 W, 12 V Universal Adapter
The circuit shown in Figure 11 is a high efficiency universal input
30 W, 12 V output adapter using the LNK6766E.
The supply uses primary winding coupled sensing for the
following features: output regulation, line undervoltage lockout,
input and output OVP. With primary winding sense there is no
need for an external secondary referenced error amplifier such
as a TL431 and optocoupler. The winding sense of bus voltage
also eliminates the need for direct input voltage sensing which
requires more components and is more dissipative than winding
sense method.
Regulation is accomplished by sampling the feedback winding
during flyback period through the resistor divider R19 and R20
through FEEDBACK pin. This sampled voltage is compared to
an internal error amplifier threshold of 2 V. The value of R19 is
already determined by the line undervoltage function so the
output regulation point is determined by setting the proper
value for R20.
Output regulation is ±5%, active-on efficiency is 86% and
no-load input power is less than 30 mW.
The rectified and filtered input voltage is applied to the primary
winding of T1. The other side of the primary is driven by the
integrated power MOSFET in U1. Diode D1, C3, R2, R3 and
VR1 comprise the clamp circuit, limiting the leakage inductance
turn-off voltage spike to safe value. Zener diode VR1 also helps
to reduce input power consumption during no-load conditions.
The loop compensation is provided by the network from
COMPENSATION pin to ground. In the case above, a low
frequency to mid frequency gain of 20 dB for the error amplifier
is established by R7 and C7. Capacitor C8 functions essentially
as a noise filter and is typically 100 pF. There is also an internal
16 kHz filter within the device. It is advised to limit R7 to no
greater than 260 kW to avoid stability and noise sensitivity.
Start-up of the power supply is initiated by sensing the forward
negative pulse current from feedback winding through R19 into
C18
2.2 nF
250 VAC
9
C12
1000 µF
16 V
VR1
BZG03C130
130 V
R29
R30
3.3 MΩ 3.3 MΩ
F1
2A
J1
90 - 265
VAC
D
6
RTN
D2
BAV21WS7-F
8
C6
22 µF
16 V
R9
4.3 kΩ
1%
1/8 W
T1
RM8
R19
41.2 kΩ
1%
BP
CONTROL
S
J2
C22
10 µF
16 V
J4
D1
DL4937
LinkSwitch-HP
U1
LNK6766E
R28
27 kΩ
FL2
7
C2
68 µF
400 V
C14
150 nF
275 VAC
12 V, 2.5 A
J3
C3
10 nF
630 V
R2
100 Ω
1/2 W
L4
10 mH
L5
100 µH
FL1
D8
STPS30100ST
R3
3 kΩ
BR2
DF206ST-G
600 V
C13 R13
680 pF 20 Ω
100 V 1/8 W
PD
C20
4.7 nF
50 V
R8
23.2 kΩ
1%
1/8 W
FB
CP
R7
100 kΩ
1/8 W
C7
100 nF
25 V
C23
10 pF
50 V
C8
100 pF
50 V
R20
10.2 kΩ
1%
C5
470 nF
50 V
PI-6844-120312
Figure 11. Schematic of a Universal Input 30 W, 12 V, 2.5 A Adapter.
8
Rev. F 02/21
www.power.com
LinkSwitch-HP
The transient load response is dependent on the loop gain and
minimum switching frequency. The values of R7 and C7 shown
here typically give good transient response for most designs.
When the supply is at no-load, the minimum switching frequency
at no-load will create a delay to respond to any step load event
during the off-time. In the case above, the minimum frequency
is 250 Hz so there is a potential 4 ms delay to response. If a
faster response is desired from no-load initial condition there is
the option to use the LNK666x which has a minimum frequency
of 2 kHz. There is a trade-off in using this family as no-load
input power will be slightly higher and a smaller pre-load resistor
will be required.
BYPASS pin to provide external bias. The external bias current
should set via R9 to be at least 500 mA to guarantee the internal
current source of LinkSwitch-HP is turned off as this will allow
the supply to operate more efficiently, especially at light load.
For best no-load performance the external supply voltage
across C6 should be minimized (typically 8-9 V) and the current
into the BYPASS pin set by R9 should be as low as possible.
Input overvoltage protection is done through sensing the
negative forward pulse of feedback winding. When the negative
forward voltage is sufficiently high to produce more than 1.15 mA
current into the FEEDBACK pin, for 2 consecutive on-cycles the
device will stop switching for auto-restart delay period.
In order to have good efficiency, regulation performance and
stability, the transformer leakage inductance should be minimized.
Low leakage will minimize ringing on the sense winding which
can create an error in the feedback sampling. The example
above uses split primary winding technique to lower leakage
inductance. Leakage inductance should not be greater than
2% of nominal primary inductance and 1% is typically the
desirable target value.
Output overvoltage protection is achieved by sensing the flyback
pulse through the FEEDBACK pin. When the FEEDBACK pin
sees 2.5 V or greater for 16 consecutive cycles, the supply will
latch off. If non-latching OVP is desired then changing C5 from
0.47 mF to 4.7 mF will change fault mode accordingly (see Table 3
for details).
Resistor R28 serves as a pre-load resistor to minimize output
voltage rising in no-load condition. The pre-load resistor should
be no smaller than is necessary to maintain output within
specification limits to minimize added dissipation. In this example,
the added pre-load dissipation is only 4.8 mW.
LinkSwitch-HP provides an internal current source to bias the
BYPASS pin which is necessary for start-up. When the supply
is operating and in regulation an external bias is provided from
the rectified flyback voltage from the bias winding (D2 and C6).
Resistor R9 is sourced from the bias voltage across C6 into the
OCP protection is accomplished by sensing when the output
drops below 0.925 of nominal regulation value for a duration
greater than specified delay time. In the example above, the
total delay time is about 50 ms. Capacitor C20 extends the
default internal delay time of 35 ms (see Figure 6 for details).
The latching shut-off option is used in the design above.
The primary current limit of LinkSwitch-HP can be adjusted by
selecting the value for R8 (see Table 4 for details). For this
design 60% of maximum current limit was chosen. A lower
current limit setting is typical for an adapter where lower RDS(ON)
is desirable for higher efficiency and also lower thermal rise of
LinkSwitch-HP.
9
www.power.com
Rev. F 02/21
LinkSwitch-HP
Layout Considerations for eSIP-7C Package
Figure 12 is the layout for a 30 W adapter shown in the schematic
Figure 11. An eSIP-7C package is used as indicated by the
suffix in LNK6766E which allows the use of a stand-up heat
sink. The mounting pin for the heat sink should be electrically
isolated. It can be seen that the primary return trace wraps
around the LinkSwitch-HP device which acts as a shield around
the critical external control related components of LinkSwitch-HP.
These components include R7, R8, R19, R20 and C5, C8, C20.
Of particular importance is placing the bypass capacitor C5 and
COMPENSATION pin noise filter capacitor C8 as close as possible
to SOURCE pin with very short trace lengths to COMPENSATION
and BYPASS pins as shown. If an electrolytic capacitor is
selected as the bypass capacitor (C5) then an additional 100 nF
(C5) ceramic must also be fitted. The ground trace wrap, tight
layout and single point grounding to SOURCE pin of these
components avoids having noise related issues during peak
loads or during line transient such as surge or ESD events.
Another consideration for ESD and line surge is the primaryside termination of the Y capacitor. The Y capacitor C18 should
be tied to the positive terminal of the bulk capacitor C2 in order
to route the potential of high currents away from the more
sensitive primary return traces.
Because of the tight layout common to adapter applications,
this design uses triple insulated wire and flying leads for output
winding termination to avoid secondary arcing to core during
ESD events.
The trace connecting the drain to transformer should be very
short and the primary clamp circuitry should be grouped
together and away from the more sensitive components. The
bias winding return and return of bias capacitor C6 should be
routed separately to the negative terminal of the input capacitor
C2 away from SOURCE pin.
The secondary rectifying loop that includes the secondary
winding, the output diode D8, and the first output capacitor C13
should be as tight as possible to minimize adding series
inductance which can reduce high load efficiency and degrade
the quality of regulation.
Figure 12. Layout for 30 W Adapter using a eSIP-7C Package (View from Bottom Copper Layer).
10
Rev. F 02/21
www.power.com
LinkSwitch-HP
Layout Considerations for eDIP-12B package
The schematic extract in Figure 13 is an example of LinkSwitch-HP
used in a dual output LCD monitor supply using eDIP-12B
package. In this design the exposed metal tab on the topside
of package is left open (no heat sink). The SOURCE pins of
LinkSwitch-HP provide heat sinking through connection to the
source copper pad of PCB. This technique is adequate for
BR1
device dissipation up to 0.85 W (1/2 square inch of copper
area
DF06M
600 V
required). The layout guidelines described for eSIP-7C
are the
same for eDIP-12B with an added consideration about sensitive
component layout. The return referenced components C4, C8,
C16, R9, R7 must be placed directly under the LinkSwitch-HP
package as shown in Figure 14. This requiresL1that these
mH
C2
particular components be SMD type as this 10
allows
an ideal
47 µF
450 V
noise-immune layout.
C1
•
•
•
•
•
•
•
5
F1
RT1
t
12 V output.
5Ω
2A
Schottky rectification.
90 - 265
82% efficiency.
VAC
J1-3
J1-1
VOR = 135 V.
KP = 0.4 for 85-265 VAC input and KP = 0.6 for 195-265 VAC
input.
VMIN = 100 V for 85-265 VAC input and VMIN = 250 V for
195-265 VAC input.
0.85 W device dissipation for open frame designs with PCB
heat sink.
D
O
Quick Design Checklist
C10
1
T1
EF25
100 nF
310 VAC
Output Power Table Assumptions
R10
10 Ω
C9
1 nF
1. Maximum drain voltage –250
Verify
that VDS does
notpFexceed
1% 470
VAC
1/8 W 200 V
675 V for LNK677X series and 600 V for LNK6X6X series.
12
This gives a 50 V margin 6for design
variations.
D3 should be
the
maximum
Drain
current
2. Under allR2conditions,
30BQ100PBF
R3
R1
100
Ω
100
Ω
R12
below
the
specified
absolute
maximum
ratings.
3 kΩ
C15
1%
1%
10 Ω
470 pF minimum
3. Thermal check – At rated maximum output1%
power,
L2
1/8 W 200 V
Ferrite Bead
inputVR1voltage and maximum ambient temperature, verify that
(3.5 × 4.45 mm)
C3
7,8
10allowed
nF
theP6KE130A
maximum
temperature
is not exceeded for any
130
V
630 V
D4
C13
component in the design. Of particular importance
is
B340LB-13-F
820 µF
6.3 V
checking the temperature rise of the major power conversion
R4
9,10
components 20
such
as transformer,
output diodes, input
Ω
1%
3
bridge, primary clamp circuit and
LinkSwitch-HP.
Under the
D2
BAV21WS- C6
stated conditions
tab temperature
22 µF
D1 above, LinkSwitch-HP 7-F
R5
25 V
DL4937
6.98 kΩ
should not exceed 110 °C.
1%
LinkSwitch-HP
U1
LNK6774V
C4*
BP
CONTROL
S
R6
23.2 kΩ
1%
1/16 W
1/8 W
R8
46.4 kΩ
1%
1/16 W
PD
FB
C5
4.7 µF
10 V
CP
R7
100 kΩ
1%
1/16 W
C7
100 nF
25 V
C16
10 pF
50 V
C8
100 pF
50 V
R9
10.5 kΩ
1%
1/16 W
PI-6860-120312
*Optional
PI-6860-120312
Figure 13. 17 W LCD Monitor Supply (+18 V, +5 V).
All LinkSwitch-HP designs should be verified on the bench
particularly for specified worst-case stress conditions. The
following set of tests are strongly recommended:
Figure 14. Layout for LCD Monitor Supply using eDIP-12B Package.
11
www.power.com
Rev. F 02/21
C11
220 µ
35 V
C14
820 µ
6.3 V
LinkSwitch-HP
Absolute Maximum Ratings(3)
DRAIN Pin Voltage.................................... -0.3 V to 725 V (677x)
DRAIN Pin Voltage...........................-0.3 V to 650 V (666x/676x)
DRAIN Pin Peak Current: ……………………........... 1.6 x ILIMIT(TYP)(1)
BYPASS Pin Voltage............................................... -0.3 V to 9 V
BYPASS Pin Current...................................................... 100 mA
FEEDBACK Pin Voltage......................................... -0.3 V to 9 V(2)
COMPENSATION Pin Voltage................................. -0.3 V to 9 V
PROGRAM/DELAY Pin Voltage............................... -0.3 V to 9 V
Storage Temperature....................................... -65 °C to 150 °C
Operating Junction Temperature ................... -40 °C to 150 °C(4)
Notes:
1. Peak DRAIN current is allowed while the DRAIN voltage is
simultaneously less than 400 V.
2. -1 V for current pulses ≤5 mA out of the pin and a duration
of ≤500 ns.
3. Maximum ratings specified may be applied one at a time
without causing permanent damage to the product.
Exposure to Absolute Maximum Rating conditions for
extended periods of time may affect product reliability.
4. Normally limited by internal circuitry.
Thermal Resistance
Thermal Resistance: E Package
(qJA)........................................... 105 °C/W(1)
(qJC)............................................... 2 °C/W(2)
K Package
(qJA) ...........................45 °C/W(3), 38 °C/W(4)
(qJC)............................................... 2 °C/W(2)
V Package
(qJA) ............................74 °C/W(3), 63 °C/W(4)
(qJC)............................................... 2 °C/W(2)
Notes:
1. Free standing with no heat sink.
2. Measured at the back surface of tab.
3. Soldered (including exposed pad for K package) to typical
application PCB with a heat sinking area of 0.36 sq. in.
(232 mm2), 2 oz. (610 g/m2) copper clad.
4. Soldered (including exposed pad for K package) to typical
application PCB with a heat sinking area of 1 sq. in. (645 mm2),
2 oz. (610 g/m2) copper clad.
Symbol
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
(Unless Otherwise Specified)
Min
Typ
Max
Units
Switching Frequency
fOSC
Average value, TJ = +25 °C,
120
132
136
kHz
Switching Frequency
Temperature Variation
ΔfOSC
0 °C ≤ TJ ≤ +100 °C, See Note A
±10
%
Frequency Jitter
Deviation
Δf
fOSC = 128 kHz
Frequency Jitter
Modulation Rate
fM
Parameter
Control Functions
Maximum Duty Cycle
DCMAX
Maximum Duty Cycle
Temperature Variation
∆DCMAX
VFB < VFB(REF)
VFB(REF) = 2 V
TJ = +25 °C
62
±5
kHz
250
Hz
64
See Note A
0 °C ≤ TJ ≤ +100 °C
66
%
±2%
%
Minimum Peak
Current to Set
Current Limit Ratio
kPS
TJ = +25 °C
di/dt(KPS) = di/dt(ILIMIT)
22.5
25
%
Multi-Cycle Modulation
Switching Frequency
fMCM
TJ = +25 °C
25
32
kHz
Multi-Cycle
Modulation Max
Off-Time
TMCM(OFF)
Soft-Start Time
tSOFT
TJ = +25 °C
15
ms
Auto-Restart ShutDown Default Delay
tSD(AR)
TJ = +25 °C
35
ms
tAR(ON)
TJ = +25 °C, tSOFT + tSD(AR)
50
TAR(OFF)1
First switch off-period
150
TAR(OFF)2
Subsequent switch off-periods
1500
Auto-Restart
TJ = +25 °C
LNK666x
0.5
LNK67xx
4
ms
ms
12
Rev. F 02/21
www.power.com
LinkSwitch-HP
Symbol
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
(Unless Otherwise Specified)
Min
Typ
Max
Units
gM
TJ = +25 °C
95
115
125
μA/V
Transconductance
Amplifier Gain
Temperature Variation
ΔgM
0 °C ≤ TJ ≤ +100 °C
See Note A
±20
%
Transconductance
Amplifier Max Output
Current
IGM
TJ = +25 °C
10.0
15.0
μA
COMPENSATION Pin
Input Impedance
ZCP
See Note A
30
Parameter
Control Functions (cont.)
Transconductance
Amplifier Gain
12.5
MW
Bypass (BP) Input
0.47
OVP/UVP/OTP
Programming
Capacitor Value
CBP
BYPASS Pin Voltage
VBP
5.46
BYPASS Pin
Voltage Hysteresis
VBPH
mF
5.75
6.04
V
0.85
0.95
1.1
V
-6.8
-4.8
-2.0
LNK6xx4-5
-9.2
-6.6
-2.8
LNK6xx6-8
-12.0
-8.3
-4.3
LNK6xx9
-14.3
-10.1
-4.2
LNK6xx3
-4.7
-2.7
-1.5
LNK6xx4-5
-7.0
-4.0
-2.2
LNK6xx6-8
-8.8
-5.2
-2.9
LNK6xx9
-11.5
-6.6
-3.7
5.7
8.2
10.7
ICH1
VBP = 0 V
TJ = +25 °C
VDS ≥ 50 V
BYPASS Pin
Charge Current
ICH2
IBPSD
BYPASS Pin
Shutdown Delay
BYPASS Pin
Source Current
BYPASS Pin Charge
Current Temperature
Variation
BYPASS Pin
Shunt Voltage
BYPASS Pin
Supply Current
4.7
47
LNK6xx3
BYPASS Pin Shutdown
Threshold Current
Typ ×
0.7
Typ ×
1.3
TJ = +25 °C
See Table 3 for programming
VBP = 5 V
TJ = +25 °C
VDS ≥ 50 V
TJ = +25 °C
TJ = +25 °C
VBP = 6 V
TJ = +25 °C
ΔIBPSC
See Note A
VBP(SHUNT)
IBP = 2 mA
IBPS1
TJ = +25 °C, See Note B
IBPS2
MOSFET switching
at fOSC
-0.5
0.5
6.1
6.4
mA
mA
Switching
Cycles
8
IBPSC
mA
mA
%/°C
6.7
V
525
mA
LNKxxx3
0.9
1.2
LNKxxx4
1.0
1.3
LNKxxx5
1.1
1.4
LNKxxx6
1.3
1.6
mA
13
www.power.com
Rev. F 02/21
LinkSwitch-HP
Parameter
Symbol
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
(Unless Otherwise Specified)
Min
Typ
Max
LNKxxx7
1.4
1.7
LNKxxx8
1.55
1.85
LNKxxx9
1.65
1.95
2.000
2.026
Units
Bypass (BP) Input (cont.)
BYPASS Pin
Supply Current
IBPS2
MOSFET switching
at fOSC
mA
Voltage Sense (FB) Input
FEEDBACK Pin
Reference Voltage
VFBth
TJ = +25 °C
FEEDBACK Pin
Reference Voltage
Temperature Variation
ΔVFB(th)
0 °C ≤ TJ ≤ +100 °C
See Note A
-0.01
%/°C
Line Undervoltage
Turn-On Threshold
Current
IFB(UV,REF)
TON = 220 ns, TJ = +25 °C
-250
mA
FEEDBACK Pin Bus
Voltage Reference
Current Temperature
Variation
ΔIFB(REF)
TON = 220 ns, 0 °C ≤ TJ ≤ +100 °C
See Note A
Line Undervoltage
Turn-Off Threshold
Current
IFB(UVOFF)
TON = 220 ns,
TJ = +25 °C
Line Undervoltage
Turn-Off Delay
Line Overvoltage
Turn-Off Threshold
Current
-115
TJ = 25 °C
IFB(OV)
Line Overvoltage
Turn-Off Delay
Output Overvoltage
Detection Threshold
Voltage
1.974
Output Overvoltage
Detection Delay
TON = 220 ns, TJ = +25 °C
TJ = +25 °C
TJ = +25 °C
Current Limit
Reduction Onset
Threshold Current
IFB(LIM)
TON = 220 ns, TJ = +25 °C
Current Limit
Reduction Slope
ILIM(LINE)
TSAMP1
TSAMP2
TMFVP
0 °C ≤ TJ ≤ +100 °C
-85
mA
Switching
Cycles
-1150
-1100
2.5
1.794
1.85
2.625
1.906
V
mA
-210
-0.032
IFB < -463 mA
-0.008
IPK = ISET
2.5
2.65
IPK = 0.25 × ISET
1.2
1.3
0.8
V
Switching
Cycles
-463 mA < IFB ≤ IFB(LIM)
TJ = +25 °C
mA
Switching
Cycles
16
VFB(AR)
Missing Feedback
Voltage Protection
Sense Delay Time
-1200
2.375
FEEDBACK Pin
Auto-Restart
Threshold Voltage
FEEDBACK Pin
Sampling Delay Time
%
2
TJ = +25 °C
0 °C ≤ TJ ≤ +100 °C
±10
8
TJ = +25 °C
VFB(OVP)
-100
V
%/mA
ms
ms
14
Rev. F 02/21
www.power.com
LinkSwitch-HP
Parameter
Symbol
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
(Unless Otherwise Specified)
Min
Typ
Max
Units
Voltage Sense (FB) Input (cont.)
Missing Feedback
Voltage Protection
Delay
Switching
Cycles
4
Multi-Function (PD) Input
PROGRAM/DELAY
Pin Voltage
VPD
TJ = +25 °C
1.20
1.25
1.30
V
PROGRAM/DELAY
Pin Time Lower
Voltage Threshold
VPD(DL)
TJ = +25 °C
0.50
0.535
0.57
V
PROGRAM/DELAY
Pin Time Upper
Voltage Threshold
VPD(DU)
TJ = +25 °C
1.20
1.25
1.30
V
3.06
3.4
3.74
V
1.25
1.35
1.45
Fast AC Reset
Threshold
VPDTHACR
Remote On/Off
Threshold
VPDTHRM
TJ = +25 °C
Remote On/Off Delay
Threshold
Hysteresis
0.8
TJ = +25 °C
V
Switching
Cycles
8
Circuit Protection
Self Protection
Current Limit
ILIMIT
LNK6xx3
di/dt = 180 mA/ms
TJ = +25 °C
0.716
0.77
0.824
LNK6xx4
di/dt = 245 mA/ms
TJ = +25 °C
0.967
1.04
1.113
LNK6xx5
di/dt = 305 mA/ms
TJ = +25 °C
1.209
1.30
1.391
LNK6xx6
di/dt = 460 mA/ms
TJ = +25 °C
1.814
1.95
2.087
LNK6xx7
di/dt = 610 mA/ms
TJ = +25 °C
2.418
2.60
2.782
LNK6xx8
di/dt = 705 mA/ms
TJ = +25 °C
2.790
3.00
3.210
LNK6xx9
di/dt = 800 mA/ms
TJ = +25 °C
3.162
3.40
3.638
A
Programmed Current
Limit Variation
ΔILIMIT
See Table 3 for programming
0 °C ≤ TJ ≤ +100 °C, See Note A
±7
%
Operational Peak
Current Variation
ΔIPK(OP)
IPK(OP) = 25 -100% × ILIMIT,
0 °C ≤ TJ ≤ +100 °C, See Note A
±7
%
150
°C
Thermal Shutdown
Temperature
TSD
Thermal Shutdown
Hysteresis
TSDH
CBP = 0.47 μF or CBP = 4.7 μF
Leading Edge
Blanking Time
tLEB
TJ = +25 °C
See Note A
Current Limit
Delay Time
tILD
TJ = +25 °C
135
175
142
75
°C
220
ns
100
ns
15
www.power.com
Rev. F 02/21
LinkSwitch-HP
Parameter
Symbol
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
(Unless Otherwise Specified)
Min
Typ
Max
Units
TON(MIN)
tLEB(MAX) + tILD(MAX)
TJ = +25 °C
325
400
500
ns
TJ = +25 °C
6.9
7.97
TJ = +100 °C
10.5
12.08
TJ = +25 °C
4.6
5.30
TJ = +100 °C
7.0
8.09
TJ = +25 °C
3.5
4.03
TJ = +100 °C
5.4
6.21
TJ = +25 °C
2.3
2.65
TJ = +100 °C
3.6
4.14
TJ = +25 °C
1.8
2.07
TJ = +100 °C
2.7
3.11
TJ = +25 °C
1.5
1.95
TJ = +100 °C
2.3
2.90
TJ = +25 °C
1.3
1.70
TJ = +100 °C
2.0
2.60
Circuit Protection (cont.)
Minimum Switch
ON-Time
Output
LNK6xx3
ID = 100 mA
LNK6xx4
ID = 150 mA
LNK6xx5
ID = 200 mA
ON-State Resistance
RDS(ON)
LNK6xx6
ID = 300 mA
LNK6xx7
ID = 400 mA
LNK6xx8
ID = 500 mA
LNK6xx9
ID = 600 mA
OFF-State Drain
Leakage Current
Breakdown Voltage
IDSS
BVDSS
VPD =
Floating
VDS = 560 V, TJ = 125 °C
470
VDS = 325 V, TJ = 100 °C
10
LNK677x, VPD = Floating,
TJ = +25 °C
725
LNK666x/LNK676x, VPD = Floating,
TJ = +25 °C
650
DRAIN Supply Voltage
tR
Fall Time
TF
Measured in a typical flyback
Converter application
mA
V
50
Rise Time
W
V
100
50
ns
NOTES:
A. Parameter not tested over specified temperature range. Guaranteed by design and characterization.
B. Average device switching frequency below 1 kHz.
16
Rev. F 02/21
www.power.com
LinkSwitch-HP
t2
HV
t1
90%
90%
DRAIN
VOLTAGE
0V
D=
t1
t2
10%
PI-2048-021015
Figure 15. Duty Cycle Measurement.
17
www.power.com
Rev. F 02/21
LinkSwitch-HP
Typical Performance Characteristics
1.0
0
25
50
95
90
85
80
75 100 125 150
Junction Temperature (°C)
400
TCASE=25 °C
TCASE=100 °C
200
40
60
80 100 120
Scaling Factors:
LNK6xx3 1.0
LNK6xx4 1.5
LNK6xx5 2.0
LNK6xx6 3.0
LNK6xx7 4.0
LNK6xx8 4.7
LNK6xx9 5.4
100
10
1
0
0
2
4
6
8
0
10
100
DRAIN Voltage (V)
400
500
600
40
PI-6853-071812
1.2
Output Frequency
(Normalized to 25 °C)
PI-7337-081114
Scaling Factors:
LNK6xx3 1.0
LNK6xx4 1.5
LNK6xx5 2.0
LNK6xx6 3.0
LNK6xx7 4.0
LNK6xx8 4.7
LNK6xx9 5.4
80
300
Figure 19. COSS vs. Drain Voltage.
160
120
200
Drain Voltage (V)
Figure 18. Output Characteristic.
Power (mW)
20
1000
Drain Capacitance (pF)
Drain Current (mA)
PI-67335-081114
Scaling Factors:
LNK6xx3 1.0
LNK6xx4 1.5
LNK6xx5 2.0
LNK6xx6 3.0
LNK6xx7 4.0
LNK6xx8 4.7
LNK6xx9 5.4
600
0
Figure 17. Standard Current Limit vs. Temperature.
1200
800
-40 -20
Temperature (C)
Figure 16. Breakdown vs. Temperature.
1000
PI-6787-021015
1.00
PI-7336-081114
0.9
-50 -25
1.05
Standard Current Limit
(Normalized to 25 °C)
PI-2213-012315
Breakdown Voltage
(Normalized to 25 °C)
1.1
1.0
0.8
0.6
0.4
0.2
0
0
0
100
200
300
400
Drain Voltage (V)
Figure 20. Drain Capacitance Power.
500
600
-50 -25
0
25
50
75 100 125 150
Junction Temperature (°C)
Figure 21. Frequency vs. Temperature.
18
Rev. F 02/21
www.power.com
LinkSwitch-HP
Typical Performance Characteristics
0.8
0.6
0.4
0.2
PI-6854-071812
1.0
1.2
Undervoltage Threshold
(Normalized to 25 °C)
PI-4761-061407
Overvoltage Threshold
(Normalized to 25 °C)
1.2
1.0
0.8
0.6
0.4
0.2
0
0
-50 -25
0
25
50
-50 -25
75 100 125 150
0.6
0.4
0.2
0
0
25
50
1.2
1.0
0.8
0.6
0.4
0.2
0
-50 -25
75 100 125 150
0.6
0.4
0.2
0
100 200 300 400 500 600 700 800
DRAIN Voltage (V)
Figure 26. Maximum Allowable Drain Current vs. Drain Voltage
(LNK6773-6779).
50
75 100 125 150
1.2
PI-6731-040212
DRAIN Current
(Normalized to Absolute Maximum Rating)
PI-6010-060410
DRAIN Current
(Normalized to Absolute Maximum Rating)
0.8
0
25
Figure 25. Undervoltage Threshold vs. Temperature.
Figure 24. Overvoltage Threshold vs. Temperature.
1
0
Junction Temperature (°C)
Junction Temperature (°C)
1.2
75 100 125 150
PI-6856-071812
Undervoltage Turn-Off Threshold
(Normalized to 25 °C)
PI-6855-071812
Undervoltage Turn-On Threshold
(Normalized to 25 °C)
0.8
-50 -25
50
Figure 23. Undervoltage Threshold vs. Temperature.
Figure 22. Overvoltage Threshold vs. Temperature.
1.0
25
Junction Temperature (°C)
Junction Temperature (°C)
1.2
0
1
0.8
0.6
0.4
0.2
0
0
100
200 300 400 500 600
700
DRAIN Voltage (V)
Figure 27. Maximum Allowable Drain Current vs. Drain Voltage
(LNK6763-6769/LNK6663-6669).
19
www.power.com
Rev. F 02/21
LinkSwitch-HP
eSIP-7C (E Package)
C
2
A
0.403 (10.24)
0.397 (10.08)
0.264 (6.70)
Ref.
0.081 (2.06)
0.077 (1.96)
B
Detail A
2
0.290 (7.37)
Ref.
0.519 (13.18)
Ref.
0.325 (8.25)
0.320 (8.13)
Pin #1
I.D.
0.140 (3.56)
0.120 (3.05)
3
0.207 (5.26)
0.187 (4.75)
0.016 (0.41)
Ref.
3
0.047 (1.19)
0.070 (1.78) Ref.
0.050 (1.27)
0.198 (5.04) Ref.
0.016 (0.41) 6×
0.011 (0.28)
0.020 M 0.51 M C
FRONT VIEW
0.118 (3.00)
SIDE VIEW
4
0.033 (0.84) 6×
0.028 (0.71)
0.010 M 0.25 M C A B
0.100 (2.54)
BACK VIEW
0.100 (2.54)
10° Ref.
All Around
0.021 (0.53)
0.019 (0.48)
0.050 (1.27)
0.020 (0.50)
0.060 (1.52)
Ref.
0.050 (1.27)
PIN 1
0.378 (9.60)
Ref.
0.048 (1.22)
0.046 (1.17)
0.019 (0.48) Ref.
0.059 (1.50)
0.155 (3.93)
0.023 (0.58)
END VIEW
PIN 7
0.027 (0.70)
0.059 (1.50)
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions noted are determined at the outermost
extremes of the plastic body exclusive of mold flash,
tie bar burrs, gate burrs, and interlead flash, but including
any mismatch between the top and bottom of the plastic
body. Maximum mold protrusion is 0.007 [0.18] per side.
DETAIL A
0.100 (2.54)
0.100 (2.54)
MOUNTING HOLE PATTERN
(not to scale)
3. Dimensions noted are inclusive of plating thickness.
4. Does not include inter-lead flash or protrusions.
5. Controlling dimensions in inches (mm).
PI-4917-061510
20
Rev. F 02/21
www.power.com
LinkSwitch-HP
eSOP-12B (K Package)
0.356 [9.04]
Ref.
0.004 [0.10] C A 2X
2
0.400 [10.16]
Pin #1 I.D.
(Laser Marked)
0.325 [8.26]
Max. 7
2X
7
0.004 [0.10] C B
0.059 [1.50]
Ref, Typ
0.460 [11.68]
0.059 [1.50]
Ref, Typ
0.008 [0.20] C 1
2X, 5/6 Lead Tips
2
3
4
6
H
4
0.010 [0.25]
12
Gauge Plane
2
Seating Plane
0°- 8°
0.225 [5.72]
Max. 7
6
1
0.120 [3.05] Ref
BOTTOM VIEW
0.020 [0.51]
Ref.
0.092 [2.34]
0.086 [2.18]
0.032 [0.80]
0.029 [0.72]
0.006 [0.15]
0.000 [0.00]
Seating plane to
package bottom
standoff
0.004 [0.10] C
C
Seating
Plane
Detail A
0.217 [5.51]
0.022 [0.56]
Ref.
0.016 [0.41]
0.011 [0.28]
11×
END VIEW
Land Pattern
Dimensions
1
12
2
11
3
10
0.028 [0.71]
0.321 [8.15]
9
4
3
0.019 [0.48]
Ref.
0.306 [7.77]
Ref.
SIDE VIEW
0.067 [1.70]
0.049 [1.23]
0.046 [1.16]
0.028 [0.71]
Ref.
0.070 [1.78]
TOP VIEW
0.098 [2.49]
0.086 [2.18]
C
0.034 [0.85]
0.026 [0.65]
DETAIL A (Scale = 9X)
B
3
0.055 [1.40] Ref.
0.350 [8.89]
0.023 [0.58]
11×
0.018 [0.46]
0.010 (0.25) M C A B
0.010 [0.25]
Ref.
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions noted are determined at the outermost
extremes of the plastic body exclusive of mold flash,
tie bar burrs, gate burrs, and interlead flash, but
including any mismatch between the top and bottom of
the plastic body. Maximum mold protrusion is 0.007
[0.18] per side.
3. Dimensions noted are inclusive of plating thickness.
4. Does not include interlead flash or protrusions.
5. Controlling dimensions in inches [mm].
6
0.429 [10.90]
8
6. Datums A and B to be determined at Datum H.
7
7. Exposed pad is nominally located at the centerline of
Datums A and B. “Max” dimensions noted include both
size and positional tolerances.
PI-5748a-100311
21
www.power.com
Rev. F 02/21
LinkSwitch-HP
eDIP-12B (V Package)
0.004 [0.10] C A
Seating Plane
0.325 [8.26]
Max.
Pin #1 I.D.
(Laser Marked)
10
2X
0.004 [0.10] C B
1
2 3 4
0.010 [0.25] Ref.
0.120 [3.05]
Ref.
6
0.412 [10.46]
Ref.
0.306 [7.77]
Ref.
10
2
0.225 [5.72]
Max.
0.350 [8.89]
B
2
C
12 11 10 9 8
0.016 [0.41]
11×
0.011 [0.28]
6
TOP VIEW
0.104 [2.65] Ref.
5 °± 4°
0.059 [1.50]
Ref, typ.
12
3 4
0.023 [0.58]
11×
0.018 [0.46]
BOTTOM VIEW
0.092 [2.34]
0.086 [2.18]
0.049 [1.23]
0.046 [1.16]
0.022 [0.56]
Ref.
0.020 [0.51]
Ref.
0.070 [1.78]
SIDE VIEW
0.07 [1.78]
8
0.192 [4.87]
Ref.
H
0.031 [0.80]
0.028 [0.72]
0.059 [1.50]
Ref, typ.
0.010 [0.25] M C A B
END VIEW
0.019 [0.48]
Ref.
1
0.436 [11.08]
0.406 [10.32]
7
Detail A
A
7
0.400 [10.16]
7
0.356 [9.04]
Ref.
0.400 [10.16]
0.03 [0.76]
0.028 [0.71]
Ref.
DETAIL A (Scale = 9X)
Mounting
Hole Pattern
Dimensions
0.400 [10.16]
Drill Hole
0.03 [0.76]
Round Pad 0.05 [1.27]
Solder Mask 0.056 [1.42]
Notes:
1. Dimensioning and tolerancing per
ASME Y14.5M-1994.
2. Dimensions noted are determined at the outermost extremes of the plastic body exclusive of
mold flash, tie bar burrs, gate burrs, and interlead
flash, but including any mismatch between the
top and bottom of the plastic body. Maximum
mold protrusion is 0.007 [0.18] per side.
3. Dimensions noted are inclusive of plating
thickness.
4. Does not include inter-lead flash or protrusions.
5. Controlling dimensions in inches [mm].
6. Datums A and B to be determined at Datum H.
7. Measured with the leads constrained to be
perpendicular to Datum C.
8. Measured with the leads unconstrained.
9. Lead numbering per JEDEC SPP-012.
10. Exposed pad is nominally located at the centerline of Datums A and B. “Max” dimensions
noted include both size and positional tolerances.
PI-5556a-100311
22
Rev. F 02/21
www.power.com
LinkSwitch-HP
Revision Notes
Date
A
Initial Release.
08/12
A
Updated Table 2.
08/23/12
10/24/12
A
Updated page 5.
B
Formatting changes. KPS Min value updated.
12/04/12
B
Fixed Table references.
02/26/13
C
Released K package parts. Updated ΔVFB(th) Typ value on page 14.
03/14
D
Added part size 8 and 9.
08/14
E
Updated with new logo Brand Style.
06/15
F
Added Min and Max values for CBP.
02/21
Part Ordering Information
• LinkSwitch Product Family
• HP Series Number
• Package Identifier
E
eSIP-7C
K
eSOP-12B
V
eDIP-12B
• Tape & Reel and Other Options
Blank
LNK 6xx9 E TL
TL
Standard Configurations
Tape & Reel
23
www.power.com
Rev. F 02/21
For the latest updates, visit our website: www.power.com
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations
does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY
HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one
or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of
Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set
forth at www.power.com/ip.htm.
Life Support Policy
POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:
1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose
failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or
death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness.
Power Integrations, the Power Integrations logo, CAPZero, ChiPhy, CHY, DPA-Switch, EcoSmart, E-Shield, eSIP, eSOP, HiperPLC, HiperPFS,
HiperTFS, InnoSwitch, Innovation in Power Conversion, InSOP, LinkSwitch, LinkZero, LYTSwitch, SENZero, TinySwitch, TOPSwitch, PI, PI Expert,
PowiGaN, SCALE, SCALE-1, SCALE-2, SCALE-3 and SCALE-iDriver, are trademarks of Power Integrations, Inc. Other trademarks are property of
their respective companies. ©2021, Power Integrations, Inc.
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