PFS7523-7529/7533-7539
HiperPFS-3 Family
PFC Controller with Integrated High-Voltage MOSFET and Qspeed
Diode Optimized for High PF and Efficiency Across Load Range
Key Benefits
D
• High efficiency and power factor across load range
• >95% efficiency from 10% load to full load
• 0.92 easily achievable at 20% load
• EN61000-3-2 Class C and D compliant
• Highly integrated for smallest boost PFC form factor
• Integrated controller, MOSFET and ultra-low reverse recovery loss
diode (Qspeed)
+
•
•
•
•
Applications
•
•
•
•
•
PC
Printer
LCD TV
Video game consoles
80 Plus™ Platinum
designs
•
•
•
•
VCC
CONTROL
DC
OUT
PGT
HiperPFS-3
S
V
G
REF
PI-7224-061615
Figure 1. Typical Application Schematic.
Output Power Table
Universal Input Devices
Product
Maximum Continuous
Output Power Rating at
90 VAC (Full Power Mode)
Peak Output Power
(Full Power Mode)
PFS7523L/H
110 W
120 W
PFS7524L/H
130 W
150 W
PFS7525L/H
185 W
205 W
PFS7526H
230 W
260 W
PFS7527H
290 W
320 W
PFS7528H
350 W
385 W
405 W
450 W
PFS7529H
High-Line Only Input Devices
Product
Maximum Continuous
Peak Output Power
Output Power Rating at
(Full Power Mode)
180 VAC (Full Power Mode)
PFS7533H
255 W
PFS7534H
315 W
350 W
PFS7535H
435 W
480 W
PFS7536H
550 W
610 W
280 W
PFS7537H
675 W
750 W
PFS7538H
810 W
900 W
PFS7539H
900 W
1000 W
Table 1.
eSIP-16D (H Package)
FB
C
AC
IN
High-power adaptors
High-power LED lighting
Industrial and appliance
Generic PFC converters
VCC
PG
• Packaging optimized for high volume production
• Eliminates insulating pad/heat-spreader
• Enhanced features
• Programmable Power Good (PG) signal
• User selectable power limit: Enables different HiperPFS-3 family
members to be tested in the same design for optimum device
selection
• Integrated non-linear amplifier for fast output OV and UV
protection and transient response
• Digital line peak detection that provides robust performance even
with distorted input voltage from UPS or generators
• Digital power factor enhancer compensates for EMI filter and
bridge distortion, providing high-line PF >0.92 @ 20% load
Frequency adjusted over line voltage and each line cycle
• Spread-spectrum across >60 kHz window simplifies EMI filtering
requirements
• Lower boost inductance
Provides up to 450 W peak output power for universal
applications, 1 kW for high-line only applications
Protection features include: UVLO, UV, OV, OTP, brown-in/out,
cycle-by-cycle current limit and power limiting for overload
protection
Halogen free and RoHS compliant
K
Output Power Table (See Table 2 on page 11 for Maximum Continuous
Output Power Ratings.)
eSIP-16G (L Package)
Figure 2. Package Options.
www.power.com
June 2015
This Product is Covered by Patents and/or Pending Patent Applications.
PFS7523-7529/7533-7539
Description
The HiperPFS -3 devices incorporate a continuous conduction mode
(CCM) boost PFC controller, gate driver, ultra-low reverse recovery
(Qspeed™) diode and high-voltage power MOSFET in a single,
low-profile (GROUND pin connected) power package. HiperPFS-3
devices eliminate the PFC converter’s need for external current sense
resistors and the associated power loss, and use an innovative control
technique that adjusts the switching frequency over output load,
input line voltage, and even input line cycle.
™
This control technique maximizes efficiency over the entire load range
of the converter, particularly at light loads. Additionally, it significantly minimizes the EMI filtering requirements due to its wide bandwidth
spread spectrum effect. The HiperPFS-3 uses advanced digital
techniques for line monitoring functions, line feed-forward scaling, and
power factor enhancement, while using analog techniques for the
core controller in order to maintain extremely low no-load power
consumption. The HiperPFS-3 also features an integrated non-linear
error amplifier for enhanced load transient response, a user programmable Power Good (PG) signal as well as user selectable power limit
functionality. HiperPFS-3 includes Power Integrations’ standard set of
comprehensive protection features, such as integrated UV, OV,
brown-in/out, and hysteretic thermal shutdown. HiperPFS-3 also
provides cycle-by-cycle current limit and Safe Operating Area (SOA)
protection of the power MOSFET, power limiting of the output for
overload protection, and pin-to-pin short-circuit protection.
HiperPFS-3’s innovative variable frequency continuous conduction
mode operation (VF-CCM) minimizes switching losses by maintaining
a low average switching frequency, while modulating the switching
frequency in order to suppress EMI, the traditional challenge with
continuous conduction mode solutions. Systems using HiperPFS-3
typically reduce the total X and Y capacitance requirements of the
converter, the inductance of both the boost choke and EMI noise
suppression chokes, thereby reducing overall system size and cost.
Additionally, HiperPFS-3 devices dramatically reduce component count
and board footprint while simplifying system design and enhancing
reliability, when compared with designs that use discrete MOSFETs
and controllers. The innovative variable frequency, continuous
conduction mode controller enables the HiperPFS-3 to realize all of
the benefits of continuous conduction mode operation while leveraging low-cost, small, simple EMI filters.
Many regions mandate high power factor for many electronic
products with high power requirements. These rules are combined
with numerous application-specific standards that require high power
supply efficiency across the entire load range, from full load to as low
as 10% load. High efficiency at light load is a challenge for traditional
PFC solutions in which fixed MOSFET switching frequencies cause
fixed switching losses on each cycle, even at light loads. In addition
to featuring relatively flat efficiency across the load range, HiperPFS-3
also enables high power factor of >0.92 at 20% load. HiperPFS-3
simplifies compliance with new and emerging energy-efficiency
standards over a broad market space in applications such as PCs, LCD
TVs, notebooks, appliances, pumps, motors, fans, printers and LED
lighting.
HiperPFS-3’s advanced power packaging technology and high
efficiency simplify the complexity of mounting the IC and thermal
management, while providing very high power capabilities in a single
compact package; these devices are suitable for PFC applications
from 75 W to 900 W.
Product Highlights
Protected Power Factor Correction Solution
• Incorporates high-voltage power MOSFET, ultra-low reverse
recovery loss Qspeed diode, controller and gate driver.
• EN61000-3-2 Class C and Class D compliance.
• Integrated protection features reduce external component count.
• Accurate built-in brown-in/out protection.
• Accurate built-in undervoltage (UV) protection.
• Accurate built-in overvoltage (OV) protection.
• Hysteretic thermal shutdown (OTP).
• Internal power limiting function for overload protection.
• Cycle-by-cycle power switch current limit.
• Internal non-linear error amplifier for enhanced load transient
response.
• No external current sense resistor required.
• Provides ‘lossless’ internal sensing via sense-FET.
• Reduces component count and system losses.
• Minimizes high current gate drive loop area.
• Minimizes output overshoot and stresses during start-up
• Integrated power limit.
• Improved dynamic response.
• Digitally controlled input line feed-forward gain adjustment for
flattened loop gain across entire input voltage range.
• Eliminates up to 40 discrete components for higher reliability and
lower cost.
Solution for High Efficiency, Low EMI and High PF
• Continuous conduction mode PFC uses novel constant amp-second
[on-time] volt-second [off-time] control engine.
• High efficiency across load.
• High power factor across load.
• Low cost EMI filter.
• Frequency sliding technique for light load efficiency improvements.
• >95% efficiency from 10% load to full load achievable at
nominal input voltages.
• Variable switching frequency to simplify EMI filter design.
• Varies over line input voltage to maximize efficiency and
minimize EMI filter requirements.
• Varies with input line cycle voltage by >60 kHz to maximize
spread spectrum effect.
Advanced Package for High Power Applications
• Up to 450 W [universal], 1 kW [high-line only] peak output power
capability in a highly compact package.
• Simple adhesive or clip mounting to heat sink.
• No insulation pad required and can be directly connected to heat
sink.
• Staggered pin arrangement for simple routing of board traces and
high-voltage creepage requirements.
• Single package solution for PFC converter reduces assembly costs
and layout size.
2
Rev. A 06/15
www.power.com
PFS7523-7529/7533-7539
Pin Functional Description
BIAS POWER (VCC) Pin:
This is a 10.2-15 VDC [operating, 12 V typical] bias supply used to
power the IC. The bias voltage must be externally clamped to
prevent the BIAS POWER pin from exceeding 15 VDC to ensure
long-term reliability.
REFERENCE (REF) Pin:
This pin is connected to an external bypass capacitor and is used to
program the IC for either FULL or EFFICIENCY power mode. The
external capacitor is connected between the REFERENCE and SIGNAL
GROUND [G] pins. Note: the return trace to G must not be shared with
other return traces with a potential for large return currents during
surge events. The REFERENCE pin has two valid capacitor values to
select ‘Full’ (1.0 µF ±20%) and ‘Efficiency’ (0.1 µF ±20%) power
modes.
After start-up, the output voltage threshold at which the PG signal
becomes high-impedance depends on the threshold programmed by
the POWER GOOD THRESHOLD pin resistor. When not in use, the
POWER GOOD pin is left unconnected.
POWER GOOD THRESHOLD (PGT) Pin:
This pin is used to program the output voltage threshold at which the
PG signal becomes high-impedance representing the PFC stage falling
out of regulation. The low threshold for the PG signal is programmed
with a resistor between the POWER GOOD THRESHOLD and SIGNAL
GROUND pins. Tying POWER GOOD THRESHOLD to the REFERENCE
pin disables the power good function (i.e. POWER GOOD pin remains
high impedance).
SOURCE (S) Pins:
These pins are the source connection of the power switch as well as
the negative bulk capacitor terminal connection.
SIGNAL GROUND (G) Pin:
Discrete components used in the feedback circuit, including loop
compensation, decoupling capacitors for the BIAS POWER (VCC),
REFERENCE (REF) and VOLTAGE MONITOR (V) must be referenced to
the SIGNAL GROUND (G) pin. The SIGNAL GROUND pin is also
connected to the tab of the device. The SIGNAL GROUND pin should
not be tied directly to the SOURCE pin external to the IC.
H Package (eSIP-16D)
(Front View)
Pin 1 I.D.
K
NC
D
Exposed Pad (Backside)
Internally Connected to
GROUND (G) Pin
G
H Package
(eSIP-16D)
(Back View)
1
VCC
REF
G
V
C
FB
PG
PGT
S
S
16 1413 1110 9 8 7 6 5 4 3
L Package (eSIP-16G)
(Front View)
Pin 1 I.D.
V
FB
9 11
Exposed Pad
(Backside)
Not Shown
14
NC
7
S
5
PGT
3
S
C
16
REF
13
K
6
G
8 10
D
4
PG
1
VCC
POWER GOOD (PG) Pin:
Use of the PG function is optional. The POWER GOOD pin is an
active low, open-drain connection which sinks current when the
output voltage is in regulation. At start-up, once the FEEDBACK pin
voltage has risen to ~95% of the internal reference voltage, the
POWER GOOD pin is asserted low.
G
D
NC
FEEDBACK (FB) Pin:
This pin is connected to the main voltage regulation feedback resistor
divider network and is also used for fast over and undervoltage
protection. This pin also detects the presence of the feedback
voltage divider network at start-up and during operation. The divider
ratio should be the same as the VOLTAGE MONITOR pin for proper and
optimized power limit and power factor. A large upper resistor
between 8 MW and 16 MΩ ±1% is recommended. A small ceramic
capacitor between FEEDBACK and SIGNAL GROUND, forming a nominal
80 µs time-constant with the bottom resistor, is required.
Exposed Metal (Both H and L
Packages) (On Package Edge)
Internally Connected to G Pin
K
COMPENSATION (C) Pin:
This pin is used for loop pole/zero compensation of the OTA error
amplifier via the connection of a network of capacitors and a resistor
between the COMPENSATION pin and SIGNAL GROUND pin. The
COMPENSATION pin connects internally to the output of the OTA error
amplifier and the input to the on-time and off-time controllers.
3 4 5 6 7 8 91011 1314 16
VCC
This pin also features brown-in/out detection thresholds and
incorporates a weak current source into the IC in order to act as a
pull-down in the event of an open circuit condition.
1
S
S
PGT
PG
FB
C
V
G
REF
VOLTAGE MONITOR (V) Pin:
The VOLTAGE MONITOR pin is tied to the rectified high-voltage DC
rail through a 100:1, 1% high-impedance resistor divider to minimize
power dissipation and standby power consumption. The recommended resistance value is between 8 MΩ and 16 MΩ. Modifying this
divider ratio affects peak power limit, brown-in/out thresholds and
will degrade input current quality (reduce power factor and increase
THD). A small ceramic capacitor forming an 80 µs nominal timeconstant is required from the VOLTAGE MONITOR pin to the SIGNAL
GROUND pin to bypass any switching noise present on the rectified
DC bus.
PI-7225-061615
Figure 3. Pin Configuration.
3
www.power.com
Rev. A 06/15
PFS7523-7529/7533-7539
DRAIN (D)
BOOST DIODE CATHODE (K)
BIAS POWER (VCC)
VOLTAGE MONITOR (V)
INPUT LINE INTERFACE
VV
12 V GATE DRIVER
REF SERIES/SHUNT
REGULATOR
+
-
PEAK
DETECTOR
ADC
BROWN-IN/
OUT DETECT
UVLO
Integrated Qspeed
Ultrafast Diode
BO, BI
HL/LL
MON(PFE)
IOCP
VCC
MOFF × (VFB - VV)
~(VO-VIN)
LOW/HIGH
LINE DETECT
VBRST FBREF VPG(H) FBUV FBOFF FBOV
Off-Time Controller
CINT
PF
ENHANCER
+
REFERENCE
(REF)
IPGT
REFERENCE
AND BAND GAP
PON
VOFF is a function of the error-voltage
(VE) and is used to reduce
the average operating frequency
as a function of output power
Power
MOSFET
ISNS
IOCP
+
VCC
LEB
OCP
Latch
+
VOFF
+
VE
Frequency
Slide
FBOV
-
HL/LL
Non-Linear OTA
VE
+
-
FBREF
FEEDBACK
(FB)
OTA
-
+
-
-
Feedback OV
+
VOFF
senseFET
TIMER
SUPERVISOR
FEEDBACK Pin
OV/UV/OFF
POWER LIMIT
SOA RAMP
Feedback UV
Buffer and
De-Glitch
Filter
-
FBUV
+
+
HL/LL
-
VBRST
Feedback OFF
On-Time Controller
CINT
-
FBOFF
+
PON × MON(PFE) × ISNS
VFB
MON(PFE) is the switch
current sense scale
factor which is a function
of the peak input voltage
+
VPG(H)
REF
-
START-UP,
FMEA CHECKS
SOURCE (S)
SIGNAL GROUND (G)
IPGT
POWER GOOD
THRESHOLD
(PGT)
POWER GOOD
(PG)
COMPENSATION (C)
PI-7226-062215
Figure 4. Functional Block Diagram.
DRAIN (D) Pin:
This is the drain connection of the internal power switch.
BOOST DIODE CATHODE (K) Pin:
This is the cathode connection of the internal Qspeed Diode.
Functional Description
The HiperPFS-3 is a variable switching frequency boost PFC solution.
More specifically, it employs a constant amp-second on-time and
constant volt-second off-time control algorithm. This algorithm is
used to regulate the output voltage and shape the input current to
comply with regulatory harmonic current limits (high power factor).
Integrating the switch current and controlling it to have a constant
amp-sec product over the on-time of the switch allows the average
input current to follow the input voltage. Integrating the difference
between the output and input voltage maintains a constant voltsecond balance dictated by the electro-magnetic properties of the
boost inductor and thus regulates the output voltage and power.
More specifically, the control technique sets constant volt-seconds for
the off-time (tOFF). The off-time is controlled such that:
^ V O - V IN h # t OFF = K 1
(1)
Since the volt-seconds during the on-time must equal the volt-seconds during the off-time, to maintain flux equilibrium in the PFC
choke, the on-time (tON) is controlled such that:
V IN # t ON = K 1
(2)
The controller also sets a constant value of charge during each
on-cycle of the power MOSFET. The charge per cycle is varied
gradually over many switching cycles in response to load changes so
it can be regarded as substantially constant for a half line cycle. With
this constant charge (or amp-second) control, the following relationship is therefore also true:
I IN # t ON = K 2
Substituting tON from (2) into (3) gives:
(3)
K
I IN = V IN # 2
(4)
K1
The relationship of (4) demonstrates that by controlling a constant
amp-second on-time and constant volt-second off-time, the input
current IIN is proportional to the input voltage VIN, therefore providing
the fundamental requirement of power factor correction.
4
Rev. A 06/15
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PFS7523-7529/7533-7539
This control produces a continuous mode power switch current
waveform that varies both in frequency and peak current value across
a line half-cycle to produce an input current proportional to the input
voltage.
Control Engine
The controller features a low bandwidth, high gain OTA error-amplifier of which its non-inverting terminal is connected to an internal
voltage reference of 3.85 V. The inverting terminal of the error-amplifier is available on the external FEEDBACK pin which connects to
the output voltage divider network with a divider ratio of 1:100 to
regulate the output voltage to 385 V nominally. The FEEDBACK pin
connects directly to the divider network for fast transient load
response.
The internally sensed FET switch current is scaled by the input
voltage peak detector current sense gain (MON) then integrated and
compared with the error-amplifier signal (VE) to determine the cycle
on-time. Internally the difference between the input and output
voltage is derived and the resultant is scaled, integrated, and
compared to a voltage reference (VOFF) to determine the cycle
off-time. Careful selection of the internal scaling factors produces
input current waveforms with very low distortion and high power
factor.
Line Feed-Forward Scaling Factor (MON) and PF Enhancer
The VOLTAGE MONITOR (V) pin voltage is sampled and converted by
a Δ-Σ ADC to a quantized digital value. A digital line cycle peak detector, with dynamic time constants and multi-cycle filtering, derives and
smooths the peak of the input line voltage. This peak is used
internally to scale the gain of the current sense signal through the
MON variable. This contribution is required to reduce the dynamic
range of the control feedback signal as well as flatten the loop gain
over the operating input line range. The line-sense feed-forward gain
adjustment is proportional to the square of the peak rectified AC line
voltage and is adjusted as a function of the VOLTAGE MONITOR pin
voltage.
VE
Latch
RESET
IS dt
VOFF
Latch
SET
(VOUT-VIN)dt
Gate
Drive (Q)
Maximum
ON-time
Minimum
OFF-time
Timing
Supervisor
PI-5335-061615
At high-line and light load, the feed-forward MON variable is dynamically adjusted throughout the line cycle in order to compensate for
the line current distortion through the EMI filter and full bridge
network, thereby improving power factor.
The line-sense feed-forward gain is also important in providing a
switch power limit over the input line range.
This characteristic is optimized to maintain a relatively constant
internal error-voltage level at full load from an input line of 90 to
230 VAC.
Beyond the specified peak power rating of the device, the internal
power limit feature will regulate the output voltage below the set
regulation threshold as a function of output overload to maintain a
constant output power. Figure 6 illustrates the typical regulation
characteristic as a function of load.
Below the brown-in threshold (VBR+) the power limit is reduced when
the device is operated in the ‘Full’ power mode as shown in Figure 7.
As the input line voltage is reduced toward the brown-out threshold
(VBR-) and if the load exceeds the power limit derating, the boost
output voltage will drop out of regulation in accordance with Figure 6.
The rated peak power shown in Table 1 is not derated for voltages
below the brown-in threshold when the device is operated in the
‘Efficiency’ mode.
Start-Up with Pin-to-Pin Short-Circuit Protection
At start-up, the engine performs a sequence of operational checks
and pin short/open evaluations, as illustrated in Figure 8, prior to the
commencement of switching. When the input voltage peak is above
brown-in, the engine enables switching.
The OTA error amplifier provides a non-linear amplifier (NLA)
mechanism to overcome the inherently slow feedback loop response
when the sensed output voltage on the FEEDBACK pin is outside its
regulation window. This allows the error amplifier function to limit
the maximum overshoot and undershoot during load transient events.
To reduce switch and output diode current stress at start-up, the
HiperPFS-3 calculates off-time based upon output voltage (VOUT) during
start-up, resulting in a relatively soft controlled start-up.
Once the applied VCC is above the VCCUVLO+ threshold, and the output
of the on-chip VREF regulator is above REFUV+, the value of the
REFERENCE pin capacitor is detected and the full or efficiency power
mode is latched. The pin open/short tests are performed, and if the
FEEDBACK pin voltage is valid the over-temperature OTP is checked
to be false. Once the preceding checks are satisfied the input voltage
is monitored via the VOLTAGE MONITOR pin until it exceeds the VBR+
threshold [but the peak detector is not saturated]. It is at this point
that switching is enabled.
Timing Supervisor and Operating Frequency Range
Since the controller is expected to operate with a variable switching
frequency over the line frequency half-cycle, typically spanning a
range of 22 – 123 kHz when operating in CCM, the controller also
features a timing supervisor function which monitors and limits the
maximum switch on-time and off-time as well as ensures a minimum
cycle on-time. Figure 9(a) shows the typical half-line frequency
profile of the device switching frequency as a function of input
voltage at peak load conditions. Figure 9(b) shows for a given line
condition of 115 VAC, the effect of EcoSmart™ on the switching
frequency as a function of load. The switching frequency is not a
function of boost choke inductance in CCM (continuous conduction
mode) operation.
Figure 5. Idealized Converter Waveforms.
5
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Rev. A 06/15
0.8
0.6
0.4
0.2
0.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Normalized to Peak Output Power Rating
Figure 6. Typical Normalized Output Voltage Characteristics as Function of
Normalized Peak Load Rating.
1.2
PI-7544-061615
1.0
Normalized Minimum Power Limit
1.2
PI-7227-061615
Normalized to Set Output Voltage
Regulation Threshold
PFS7523-7529/7533-7539
1.0
0.8
0.6
0.4
0.2
0
PFS7523-29
PFS7533-39
Figure 7.
70
160
75
80
170
85
90
180
95
Input Voltage (VAC)
100
190
Normalized Minimum Power Limit as Function of Input Voltage.
Start
NO
YES
NO
Apply Current to
C Pin for 65 µs
VCC > UVLO+
and
REF > REFUV+?
YES
Reference
Capacitor Valid?
(C > 2.5 V) or
Feedback < FBOFF
NO
Remove Current
Source on
C Pin, Short C to G
YES
Capacitor Reset:
Short C to G
for 230 µs
YES
NO
Feedback > FBOFF
YES
Remove Short
on C Pin
OTP Fault
NO
NO
Peak Valid and
Peak > VBR+
YES
Remove C to G
Short, Start
Switching
PI-7249-061615
Figure 8. Start-Up Flow Chart.
6
Rev. A 06/15
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PFS7523-7529/7533-7539
EcoSmart
The HiperPFS-3 includes an EcoSmart function wherein the internal
error signal (VE) is used to detect the converter output power. Since
the internal error-signal is related to the output power, this signal
level is used to set the average switching frequency as a function of
output power.
switching in bursts in order to maintain regulation when leakage
currents constitute the majority of the load. Higher output voltage
ripple at light load is an artifact of efficient burst mode operation.
Power Good Signal (PG)
The HiperPFS-3 features a ‘power good’ (PG) circuit which comprises
an internal comparator that turns ‘on’ an open-drain switch during
start-up when the sensed output voltage on the FEEDBACK pin rises
to ~95% (VPG+) of the set output voltage threshold. During start-up,
prior to the output voltage reaching VPG+, the PG signal is in a
high-impedance state (internal switch is in ‘off’ state).
As shown in Figure 10, the off-time integrator control reference (VOFF)
is controlled with respect to the internal error-voltage level (output
power) to allow the converter to maintain output voltage regulation
and relatively flat conversion efficiency from 20% to 100% of rated
load, which is essential to meet many efficiency directives. The
degree of frequency slide is also controlled as a function of input line
voltage. The lower VOFF slope as a function of input voltage reduces
the average frequency extremes for high input line operation.
135 VAC
230 VAC
PI-7231-061615
130
120
110
100
90
80
70
60
50
40
30
20
10
0
Frequency (kHz)
Frequency (kHz)
Burst-Mode for No-Load Power Consumption Reduction
Under no-load conditions the HiperPFS-3 engine is architected to
enter a burst mode which gates the power switch on and off between
fixed error voltage levels. This ensures low power consumption by
180 VAC 90 VAC
115 VAC
Peak Load
45
0
90
135
180
130
120
110
100
90
80
70
60
50
40
30
20
10
0
VIN = 115 VAC
100% Peak Load
d
Expected Frequency
Range at Peak
Rated Load
P k Load
L d
75% Peak
50% Peak
a Load
25% Peak Load
45
0
Line Conduction Angle (°)
90
135
180
Line Conduction Angle (°)
Figure 9. (a) Frequency Variation over Line Half-Cycle as a Function of Input Voltage (b) Frequency Variation over Line Half-Cycle as a Function of Load.
Note: Frequency Profiles Shown were Analytically Derived and Reflect CCM Operation Across the Entire Line Cycle.
VA
VB
VOFF(MAX)
VOFF
VA
VIN < 140 VAC
VB
VIN > 170 VAC
4.0 V
(Full Power)
VE
4 V 5.2 V
140 VAC
VIN
170 VAC
PI-7228-061615
Figure 10. EcoSmart Frequency Slide VOFF vs. VE and VOFF(MAX) vs. Input Voltage.
7
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PI-7232-0616154
The power good signal transitions from ‘on’ to ‘off’ state when the
sensed output voltage on the FEEDBACK pin falls to a user selected
threshold, programmed with a resistor on the POWER GOOD
THRESHOLD (PGT) pin. The POWER GOOD THRESHOLD pin sources a
fixed current IPGT. This current combined with the power good threshold resistor sets the threshold when the power good signal transitions
from the ‘on’ state to the high-impedance ‘off’ state as the PFC
output falls out of regulation.
Rev. A 06/15
PFS7523-7529/7533-7539
The power good comparator has an internal 81 µs de-glitch filter
(tPGD) to prevent noise events from falsely triggering the programmed
VPG- threshold.
In the event a load fault prevents the boost from achieving regulation
(above ~95% of the set output voltage threshold) the PG function will
remain in the high-impedance state and will not indicate when an
output voltage has fallen below the user programmed VPG- threshold.
The VPG- user programmed threshold is enabled once the VPG+
threshold has been reached.
If the POWER GOOD THRESHOLD programming pin is tied to
REFERENCE pin, the power good function is disabled and PG remains
in the high-impedance (‘off’) state. This is the preferred configuration
when PG is not in use. If the POWER GOOD THRESHOLD pin is shorted
to the SIGNAL GROUND pin, the PG signal will transition to the ‘on’
state at VPG+ and remain low (‘on’) until the PFC output voltage has
fallen below the VFB_UV threshold for greater than tFB_UV seconds.
Similar to the disable condition described above, if the value of the
PGT resistor is such that the VPG- threshold is greater than the VPG+
threshold, the PG signal will latch off and remain in the high-impedance off-state.
The Power Good function is not valid under the following conditions:
A. VCC or VREF are not in a valid range of operation. VCC below
UVLO- or VREF below REFUV- the power good function is not valid
with the POWER GOOD pin in a high-impedance state.
B. Power Good will go to high-impedance state when a soft- shutdown is initiated by an over-temperature fault to provide early
indication to secondary circuits of an OT fault.
C. PGT is outside the valid programming range of between 225 V and
360 V. PGT voltages above this range, including PGT floating, will
prevent PG from transitioning to active pull-down. PGT voltages
below this range result in PG deassertion at the output undervoltage (VFB_UV) threshold.
D. Once the start-up sequence check has passed and the converter
goes into start-up, if PGT is opened, then the PG signal will
remain latched in the high-impedance state until the controller is
reset.
Selectable Power Limit
The capacitor on the REFERENCE pin allows user selection between
’full’ and ‘efficiency’ power limit for each device. The ‘efficiency’
power mode will permit user selection of a larger device for a given
output power requirement for increased conversion efficiency.
In ‘full’ power mode the REFERENCE pin capacitor is 1.0 µF ±20%
and the ‘efficiency’ power limit mode is selected with a 0.1 µF ±20%
capacitor.
If the REFERENCE pin is accidentally shorted to ground, the IC will
disable switching and remain disabled until all conditions for the
start-up sequence are satisfied.
If the REFERENCE pin is open-circuit, the absence of a bypass
capacitor will prevent start-up. During operation, an open-circuit may
result in enough REFERENCE pin noise to result in a VREF REFUV- shutdown.
Protection Modes
Brown-In Protection (VBR+)
The VOLTAGE MONITOR pin features an input line under-voltage
detection to limit the minimum start-up voltage. This detection
threshold will inhibit the device from starting at input AC voltages
below brown-in and above input peak voltages of 400 VPK.
Brown-Out Protection (VBR-)
The VOLTAGE MONITOR pin features a brown-out protection mode
wherein the HiperPFS-3 will turn-off when the VOLTAGE MONITOR
pin voltage is below the line undervoltage threshold (VBR-) for a period
exceeding tBRWN_OUT (brown-out debounce period). In the event a
single half-line cycle is missing (normal operating line frequency is
47 Hz to 63 Hz) the brown-out detection will not be initiated. Once
brown-out has been triggered, the HiperPFS-3 soft-shutdown
gradually reduces the internal error-voltage to zero volts over a period
of 1 ms to ramp the power MOSFET on-time to zero. The onset of
this soft-shutdown is aligned to the next line cycle zero crossing to
minimize reactive component di/dt transients and allow time for the
energy stored within the boost choke as well as the input EMI filter to
dissipate. This helps minimize voltage transients after the bridge
rectifier, which helps to prevent false restarts. The device will
Set internally
by VPG+
100% VOUT (385 V)
95% VOUT (365 V)
Output Voltage
Rising
87.5% VOUT (337 V)
Set externally
by RPGT
R PG = 0.875 # 3.85 = 3.37 V = 337 kX
I PG
10 nA
tPGD
tPGD
PG = High Impedance
PG = On-State
tPG
Output Voltage
Falling
PG = High Impedance
PI-7229-061615
Figure 11. Power Good Function Description.
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PFS7523-7529/7533-7539
After a brown-in event, until after the tSTARTUP timer has expired, the line
voltage brown-out threshold is reduced to VBR-NTC and the brown-out
timer is extended to tBRWN_OUT_NTC to allow for the detected drop in line
voltage due to an in-rush limiting negative temperature coefficient
(NTC) thermistor in series with the input line.
If the tBRWN_OUT_NTC debounce timer is triggered by the sensed line
voltage dropping below the VBR-NTC threshold but the line voltage
recovers to above the VBR-NTC threshold before the tBRWN_OUT_NTC expires,
then the tSTARTUP timer will be re-started. If the line does not recover
above the VBR-NTC threshold before the tBRWN_OUT_NTC debounce timer
expires a shutdown will occur.
After the tSTARTUP timer has expired, if the VOLTAGE MONITOR pin
voltage is qualified above VBR-NTC, the brown-out debounce timer will
switch to normal period (tBRWN_OUT) and the brown-out threshold will
switch to VBR-. If the VOLTAGE MONITOR pin voltage is not qualified
above VBR- after the subsequent tBRWN_OUT timer has expired then a
brown-out shutdown will occur.
HiperPFS-3 incorporates input waveform discrimination to determine
if the line signal peak-to-average ratio is more representative of a
sinewave or a high duty cycle square wave. The brown-out threshold
is reduced to VBR_SQ when a high duty cycle (UPS) square wave is
detected.
VCC Undervoltage Protection (UVLO)
The BIAS POWER (VCC) pin has an undervoltage lock-out protection
which inhibits the IC from starting unless the applied VCC voltage is
above the VCCUVLO+ threshold. The IC initiates a start-up once the
BIAS POWER pin voltage exceeds the VCCUVLO+ threshold. After
start-up the IC will continue to operate until the BIAS POWER pin
voltage has fallen below the VCCUVLO- level. The absolute maximum
voltage of the BIAS POWER pin is 17.5 V which must be externally
limited to prevent long term damage to the IC.
Line Dependent Over Current Protection (OCP) limit
The device includes a cycle-by-cycle over-current protection mechanism which protects the device in the event of a fault. The intent of
OCP protection in this device is protection of the internal power
MOSFET and is not specifically intended to protect the converter from
output short-circuit or overload fault conditions.
For universal line input parts, the OCP limit is set as a function of the
input line voltage, one setting for low-line voltages and another
setting for high-line voltages. This helps to bound power limit into
short-circuits as well as helps to minimize the stress on the switch
due to current overloads at higher input line conditions. Figure 12
illustrates the hysteretic adjustment of the OCP levels as a function
of VOLTAGE MONITOR pin line-sensing. This equates to selecting the
low-line OCP (the greater of the two settings) when the peak of the
input line voltage drops below 140 VAC for 3 consecutive half-cycles
and selecting the high-line OCP level (the lesser of the two settings)
when the input line voltage rises above 170 VAC for 1 half-cycle,
(except in follower mode, as described in the subsequent sections).
The HiperPFS-3 utilizes a high input line OCP after detecting the
VOLTAGE MONITOR pin above the high-line threshold, VHIGH+. The
controller reverts back to low-line OCP (as well as low-line frequency
slide) only after 3 consecutive half-line cycle peak values that are
IOCP(LL)
IOCP
perform an auto-restart, including FMEA pin fault checks and other
start-up qualifications prior to checking for the line voltage being
above the brown-in voltage by virtue of the VOLTAGE MONITOR pin
being above VBR+.
IOCP(HL)
~140 VAC
VIN
~170 VAC
PI-7255-061615
Figure 12. Line Dependent OCP.
below the low-line threshold VHIGH-. In the event of a line drop-out,
the controller may revert from high-line to low-line parameters if the
drop-out exceeds 37 ms (nominal). High-line only input parts use a
single fixed OCP threshold.
A follower-mode feature updates the controller to high-line status
rapidly, as soon as the input voltage exceeds VHIGH+. This feature has
particular benefit for high-line hard-start conditions after a long AC
line drop-out where the peak detector may initially indicate a low
input line condition.
A leading edge blanking circuit inhibits the current limit comparator
for a short time (tLEB) after the power MOSFET is turned on. This
leading edge blanking time is set so that switch current spikes caused
by drain capacitance and rectifier reverse recovery time will not cause
premature termination of the MOSFET conduction period.
Safe Operating Area (SOA) Mode
Since the cycle-by-cycle OCP mechanism described above does not
prevent the possibility of inductor current ‘stair-casing’, an SOA mode
is also featured. Rapid build-up of the switch current can occur in the
event of inductor saturation or when the input and output voltage
differential is small combined with too little inductor reset time.
The SOA mode is triggered whenever the switch current reaches
current limit (IOCP) and the on-time is less than tSOA. The SOA mode
forces an off-time equal to tOFF(SOA) and pulls the internal error-voltage
(VE) down by 1/2 of its maximum value in order to ensure the switch
remains within its SOA.
Fast Output Voltage Overvoltage Protection (FBOV)
The HiperPFS-3 features a voltage feedback threshold comparator on
the FEEDBACK pin which detects an output voltage overvoltage
condition to allow rapid response, independent of the COMPENSATION pin response, to prevent hazardous voltage conditions from
occurring. The overvoltage protection is hysteretic – the voltage on
the FEEDBACK pin must drop by 0.1 V (equating to an output voltage
drop of 10 V) before switching is re-started.
FEEDBACK to COMPENSATION Pin Short Detection Safeguard
The PFC controller continuously monitors the FEEDBACK and
COMPENSATION pins to ensure that there are no potential short
conditions between the adjacent FEEDBACK and COMPENSATION
pins, which could result in output overvoltage conditions if not
detected. In the event a potential short is detected, a rapid short
check is performed and a shutdown is executed in the event that a
suspected short is validated.
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Open FEEDBACK Pin Protection
The FEEDBACK pin continuously sinks a static current of IFBPD [VCC >
VCCUVLO+] to protect against a fault related to an open FEEDBACK pin
or incomplete feedback divider network. The internal current sink
introduces a small static offset to the output regulation which can be
accounted for in selecting the output feedback regulation components
(FEEDBACK pin divider).
Hysteretic Thermal Shutdown
The thermal shutdown circuitry senses the controller die temperature
which is well coupled to the heat sink through the exposed, grounded
pad. The threshold is set at 117 °C typical with a 36 °C hysteresis.
When the controller die temperature rises above this threshold (OTP),
the controller initiates a soft-shutdown and remains disabled until the
controller die temperature falls by ~36 °C, at which point the device
will re-initiate the start-up sequence.
The maximum time delay for soft-shutdown to occur after an OTP
event is detected is tOTP beyond the next zero-crossing.
HiperPFS-3 Additional Features and Changes
Note: HiperPFS-3 is not a pin for pin drop-in replacement of
HiperPFS-2 due to functional changes and optimizations.
• Improved operating supply voltage maximum: 15 V.
• Reduced external component count.
• Improved tolerance of key parameters over a wide temperature
range.
• NLA implemented via fixed current sources for quick transient
response, replaces switched voltage gain in HiperPFS-2.
• Off-time controller senses actual feedback voltage to calculate
off-time to prevent inductor saturation.
• VOLTAGE MONITOR pin uses voltage-mode sensing rather than
•
•
•
•
•
•
•
•
•
•
•
• Modified architecture improving noise immunity and operational
accuracy.
•
• Feedback network voltage divider is decoupled from the loop
compensation components.
• High-line only family of parts added to HiperPFS-3 family.
• Peak-detector supports deglitch methodology for NTC in-rush
current limiting at start-up.
• Digital Power Factor Enhancer algorithm improves high-line light
load power factor.
•
•
•
•
current-mode sensing of HiperPFS-2, allowing flexibility in selection
of magnitude of resistor divider.
Reduced minimum line feed-forward gain supports higher power
delivery during line sag events.
Line feed-forward gain implemented with true squaring function,
versus piece-wise linear approximation.
Line voltage functions performed in the digital domain: peak detection, feed-forward, brown-in/brown-out and PF-enhancement.
Peak detector incorporates filtering to smooth out cycle-to-cycle
variation.
Optimized brown-in/brown-out thresholds with tighter tolerances.
Most timers are derived from an internal high-speed clock
providing accurate timing.
eSIP-16 package pinout has been modified for optimal operation
and internal grounding.
No-load/light-load power consumption optimized by re-engineered
burst-mode operation.
Reduced control-engine power consumption: standby current
reduced by ~4~5× HiperPFS-2 nominal.
HiperPFS-3 REFERENCE pin replaces HiperPFS-2 REFERENCE pin;
external bypass capacitor replaces external 1% resistor.
VFB(REF) reduced to 3.85 V nominal from 6.0 V nominal in
HiperPFS-2.
Peak detector optimized across maximum operational conditions
when operating with distorted waveforms and line drop-outs.
Square-wave detector feature for improved UPS operation.
Power good function is independent of engine during operation
except for OTP events.
FBOFF fault check is always enabled during operation.
Maximum CCM peak switching frequency has been increased from
~100 kHz to 123 kHz.
• OTA error amplifier replaces voltage error amplifier of
HiperPFS-2.
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PFS7523-7529/7533-7539
Output Power Table
eSIP Package
Efficiency Power Mode CREF = 0.1 mF
Product
Maximum Continuous
Output Power Rating at
90 VAC2
Peak Output Power
Rating at 90 VAC4
Full Power Mode CREF = 1.0 mF
Maximum Continuous
Output Power Rating at
90 VAC2
Minimum3
Peak Output Power
Rating at 90 VAC4
Minimum3
Maximum
PFS7523L/H
65 W
90 W
100 W
85 W
110 W
120 W
PFS7524L/H
80 W
110 W
125 W
100 W
130 W
150 W
PFS7525L/H
110 W
150 W
170 W
140 W
185 W
205 W
PFS7526H
140 W
190 W
215 W
180 W
230 W
260 W
PFS7527H
175 W
235 W
265 W
220 W
290 W
320 W
PFS7528H
210 W
285 W
320 W
270 W
350 W
385 W
PFS7529H
245 W
335 W
375 W
300 W
405 W
450 W
Efficiency Power Mode CREF = 0.1 mF
Product
Maximum Continuous
Output Power Rating at
180 VAC2
Minimum3
Maximum
PFS7533H
155 W
205 W
PFS7534H
200 W
PFS7535H
275 W
PFS7536H
350 W
PFS7537H
PFS7538H
PFS7539H
Peak Output Power
Rating at 180 VAC4
Maximum
Full Power Mode CREF = 1.0 mF
Maximum Continuous
Output Power Rating at
180 VAC2
Peak Output Power
Rating at 180 VAC4
Minimum3
Maximum
230 W
195 W
255 W
260 W
290 W
240 W
315 W
350 W
360 W
400 W
335 W
435 W
480 W
460 W
510 W
415 W
550 W
610 W
430 W
560 W
625 W
520 W
675 W
750 W
520 W
675 W
750 W
625 W
810 W
900 W
575 W
745 W
830 W
690 W
900 W
1000 W
280 W
Table 2. Output Power Table.
Notes:
1. See Key Application considerations.
2. Maximum practical continuous power at 90 VAC in an open-frame design with adequate heat sinking, measured at 50 °C ambient.
3. Recommended lower range of maximum continuous power for best light load efficiency; HiperPFS-3 will operate and perform below this level.
4. Internal output power limit.
11
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Application Example
limits the current to the diode in the optocoupler. IC U3 provides
optocoupler isolation through connector J2 for a power-good output
signal if required.
A High Efficiency, 275 W, 385 VDC Universal Input PFC
The circuit shown in Figure 13 is designed using a device from the
HiperPFS- 3 family of integrated PFC controllers. This design is rated
for a continuous output power of 275 W and provides a regulated
output voltage of 385 VDC nominal, maintaining a high input power
factor and overall efficiency from light load to full load.
Capacitor C15 is used for reducing the loop length and area of the
output circuit to reduce EMI and overshoot of voltage across the
drain and source of the MOSFET inside U1 at each switching edge.
The PFS7527H IC requires a regulated supply of 12 V for operation
and must not exceed 15 V. Resistors R6, R7, R8, Zener diode VR1,
and transistor Q2 form a series pass regulator that prevents the
supply voltage to IC U1 from exceeding 15 V. Capacitors C8, and C9
filter the supply voltage and provide bypassing and decoupling to
ensure reliable operation of IC U1. Diode D3 provides reverse
polarity protection.
Fuse F1 provides protection to the circuit and isolates it from the AC
supply in the event of a fault. Diode bridge BR1 rectifies the AC input
voltage. Capacitors C1-C7 together with inductors L2 and L3 form
the EMI filter which reduces the common mode and differential mode
noise. Resistors R1, R2 and CAPZero, IC U2 are required to discharge
the EMI filter capacitors once the circuit is disconnected. CAPZero
eliminates static losses in R1 and R2 by only connecting these
components across the input when AC is removed.
Resistor R15 programs the output voltage level [via the power good
threshold (PGT) pin] below which the power good [PG] pin will go
into a high-impedance state. Capacitor C14 provides noise immunity
on the POWER GOOD THRESHOLD pin.
Metal oxide varistor (MOV) RV1 protects the circuit during line surge
events by effectively clamping the input voltage seen by the power
supply.
IC U1 is configured in full power mode by capacitor C10 which is
connected to the REFERENCE pin.
The boost converter stage consists of inductor L1, and the HiperPFS-3 IC U1. This stage functions as a boost converter and controls
the input current of the power supply while simultaneously regulating
the output DC voltage. Diode D2 prevents a resonant buildup of
output voltage at start-up by bypassing inductor L1 while simultaneously charging output capacitor C17.
The rectified AC input voltage of the power supply is sensed by IC U1
using resistors R10-R13. These resistors values are large to minimize
power consumption. Capacitor C11 connected in parallel with the
bottom resistor R13 filters noise coupled into the VOLTAGE MONITOR
pin.
Thermistor RT1 limits the inrush input current of the circuit at
start-up and prevents saturation of L1. In most high-performance
designs, a relay will be used to bypass the thermistor after start-up to
improve power supply efficiency. Thermistor RT1 is bypassed by the
electro-mechanical relay RL1 after the output voltage is in regulation
and a power-good signal from U1 is asserted low. Resistor R3, R4,
and Q1 drive relay RL1 and optocoupler U3. Diode D1 clamps the
relay coil reverse voltage during de-assertion transitions. Resistor R5
Output voltage divider network comprising of resistors R16 – R19 are
used to scale the output voltage and provide feedback to the IC.
Capacitor C16 in parallel with resistor R19 attenuates high frequency
noise.
R14, C12 and C13 are required for shaping the loop response of the
feedback network.
D2
1N5408-T
C3
330 nF
275 VAC
F1
5A
L
t
O
R1
510 kΩ
C1
680 pF
250 VAC
C5
680 pF
250 VAC
D1
L2
9 mH
CAPZero
U2
CAP003DG
90 - 264
VAC
E
C2
680 pF
250 VAC
D
BR1
GBU8K-BP
800 V
RT1
2.5 Ω
C4
330 nF
275 V
RV1
320 VAC
+
R16
3.74 MΩ
1%
R10
6.2 MΩ
1%
C6
680 pF
250 VAC
D2
FB
C
HiperPFS-3
U1
PFS7527H
PGT
S
N
R18
6.2 MΩ
1%
VCC
CONTROL
R12
3.74 MΩ
1%
V
G
REF
L3
330 µH
R4
16.2 kΩ
1%
R3
10 kΩ
1%
Q1
MMBT4403
J4-1
R6
1Ω
1%
Q2
MMBT4401LT1G
R14
30.1 kΩ
1%
Power
Good
J2-1
U3
LTV817A
D1
S1AB-13-F
1
VCC
Supply
2
4
R7
1Ω
1%
RL1
J4-2
C8
47 µF
50 V
C10
1 µF
50 V
VR1
BZX384-B13,115
13 V
+
C15
10 nF
1 kV
R15
332 kΩ
1%
R8
2.21 kΩ
1%
DC
OUT
3
D3
S1AB-13-F
J2-2
C17
180 µF
450 V
R13
162 kΩ
1%
+
R5
3.01 kΩ
1%
J3-1
R17
6.2 MΩ
1%
PG
R11
6.2 MΩ
1%
C7
680 nF
450 V
R2
510 kΩ
VO
K
L1
400 µH
C9
1 µF
35 V
C12
100 nF
25 V
C13
1 µF
50 V
C14
1 nF
50 V
C16
470 pF
50 V
R19
162 kΩ
1%
C11
470 pF
50 V
VO
PI-7257-061615
J3-3
Figure 13. 275 W PFC using PFS7527H.
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PFS7523-7529/7533-7539
Design, Assembly, and Layout Considerations
Power Table
The data sheet power table as shown in Table 2 represents the
maximum practical continuous output power based on the following
conditions:
For the universal input devices (PFS7523L/H – PFS7529H):
An input voltage range of 90 VAC to 264 VAC.
Overall efficiency of at least 93% at the lowest operating voltage.
385 V nominal output.
Sufficient heat sinking to keep device temperature ≤100 ºC.
1.
2.
3.
4.
Operation beyond the limits stated above will require derating.
Operation at elevated temperatures could result in reduced MTBF and
performance degradation, e.g. reduced efficiency, reduced power
limit, PF, and potential of observing hysteretic brown-out, etc., and is
not recommended. Use of a nominal output voltage higher than 395 V
is not recommended for HiperPFS-3 based designs. Operation at
voltages higher than 395 V can result in higher than expected
drain-source voltage during line and load transients.
HiperPFS-3 Selection
Selection of the optimum HiperPFS-3 part depends on required
maximum output power, PFC efficiency and overall system efficiency
(when used with a second stage DC-DC converter), heat sinking
constraints, system requirements and cost goals. The HiperPFS-3
part used in a design can be easily replaced with the next higher or
lower part in the power table to optimize performance, improve
efficiency or for applications where there are thermal design
constraints. Minor adjustments to the inductance value and EMI filter
components may be necessary in some designs when the next higher
or the next lower HiperPFS-3 part is used in an existing design for
performance optimization.
Every HiperPFS-3 family part has an optimal load level where it offers
the most value. Operating frequency of a part will change depending
on load level. Change of frequency will result in change in peak to
peak current ripple in the inductance used. Change in current ripple
will affect input PF and total harmonic distortion of input current.
Input Fuse and Protection Circuit
The input fuse should be rated for a continuous current above the
input current at which the PFC turns-off due to input under- voltage.
This voltage is referred to as the brown-out voltage.
The fuse should also have sufficient I2t rating in order to avoid
nuisance failures during start-up. At start-up a large current is drawn
from the input as the output capacitor charges to the peak of the
applied voltage. The charging current is only limited by any inrush
limiting thermistors, impedance of the EMI filter inductors and the
forward resistance of the input rectifier diodes. A MOV will typically be
required to protect the PFC from line surges. Selection of the MOV
rating will depend on the energy level (EN1000-4-5 Class level) which
the PFC is required to withstand.
A suitable NTC thermistor should be used on the input side to provide
inrush current limiting. Choice of this thermistor should depend on
the inrush current specification for the power supply. NTC thermistors may not be placed in any other location in the circuit as they fail
to limit the stress on the part in the event of line transients and also
fail to limit the inrush current in a predictable manner. The example
in Figure 13 shows the circuit configuration that has the inrush
limiting NTC thermistor on the input side which is bypassed with a
relay after PFC start-up. This arrangement ensures that a consistent
inrush limiting performance is achieved by the circuit.
Input EMI Filter
The variable switching frequency of the HiperPFS-3 effectively
modulates the switching frequency and reduces conducted EMI peaks
associated with the harmonics of the fundamental switching frequency.
This is particularly beneficial for the average detection mode used in
EMI measurements.
The PFC is a switching converter and will need an EMI filter at the
input in order to meet the requirements of most safety agency
standards for conducted and radiated EMI. Typically a common mode
filter with X capacitors connected across the line will provide the
required attenuation of high frequency components of input current
to an acceptable level. The leakage reactance of the common mode
filter inductor and the X capacitors form a low pass filter. In some
designs, additional differential filter inductors may have to be used to
supplement the differential mode inductance of the common-mode
choke.
A filter capacitor with low ESR and high ripple current capability
should be connected at the output of the input bridge rectifier. This
capacitor reduces the generation of the switching frequency components of the input current ripple and simplifies EMI filter design.
Typically, 0.33 mF per 100 W should be used for universal input
designs and 0.15 mF per 100 W of output power should be used for
230 VAC only designs.
It is often possible to use a higher value of capacitance after the
bridge rectifier and reduce the X capacitance in the EMI filter.
Regulatory requirements require use of a discharge resistor to be
connected across the input X capacitance on the AC side of the
bridge rectifier. This is to ensure that residual charge is dissipated
after the input voltage is removed when the capacitance is higher
than 0.1 mF. Use of CAPZero integrated circuits from Power Integrations, helps eliminate the steady- state losses associated with the use
of discharge resistors connected permanently across the X capacitors.
Inductor Design
For ferrite inductors the optimal design has KP of 0.3 to 0.45. (KP is
defined as the current peak-to-peak value divided by the peak value
at minimum AC voltage and 90* phase angle, full load). KP 0.45 tends towards excessive winding AC resistance losses due to
large high-frequency AC currents, especially since most ferrite
inductor designs will require >3 winding layers. Flux density at
maximum current limit should be 2.42 V
2.6
2.8
3.0
VV < 2 V
4.5
4.8
5.1
V V > 2.42 V
3.0
3.3
3.5
A
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PFS7523-7529/7533-7539
Parameter
Symbol
Conditions
SOURCE = 0 V; VCC = 12 V,
-40 °C < TJ(C) < 125 °C
(Note C) (Unless Otherwise Specfied)
Min
Typ
Max
VV < 2 V
5.5
5.9
6.2
V V > 2.42 V
3.6
4.0
4.4
VV < 2 V
6.8
7.2
7.5
V V > 2.42 V
4.6
4.9
5.25
VV < 2 V
8.0
8.4
8.8
V V > 2.42 V
5.35
5.8
6.2
VV < 2 V
9.0
9.5
9.9
V V > 2.42 V
6.0
6.5
7.1
VV < 2 V
10
10.5
11
V V > 2.42 V
6.7
7.2
7.7
3.8
4.1
4.3
Units
Current Limit/Circuit Protection (cont.)
PFS7525L/H
di/dt = 400 mA/ms
TJ(C) = 25 °C
PFS7526H
di/dt = 500 mA/ms
TJ(C) = 25 °C
PFS7527H
di/dt = 650 mA/ms
TJ(C) = 25 °C
PFS7528H
di/dt = 800 mA/ms
TJ(C) = 25 °C
PFS7529H
di/dt = 920 mA/ms
TJ(C) = 25 °C
Over-Current
Protection
PFS7533H
di/dt = 250 mA/ms
TJ(C) = 25 °C
IOCP
A
PFS7534H
di/dt = 300 mA/ms
TJ(C) = 25 °C
4.5
4.8
5.1
PFS7535H
di/dt = 400 mA/ms
TJ(C) = 25 °C
5.5
5.9
6.2
PFS7536H
di/dt = 500 mA/ms
TJ(C) = 25 °C
6.8
7.2
7.5
PFS7537H
di/dt = 650 mA/ms
TJ(C) = 25 °C
8.0
8.4
8.8
PFS7538H
di/dt = 800 mA/ms
TJ(C) = 25 °C
9.0
9.5
9.9
PFS7539H
di/dt = 920 mA/ms
TJ(C) = 25 °C
10
10.5
11
23
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Rev. A 06/15
PFS7523-7529/7533-7539
Parameter
Symbol
Conditions
SOURCE = 0 V; VCC = 12 V,
-40 °C < TJ(C) < 125 °C
(Note C) (Unless Otherwise Specified)
Min
Typ
Max
Units
Current Limit/Circuit Protection (cont.)
Normalized Frequency
at Power Limit
SOA Protection
Fixed Off-Time
Leading Edge Blanking
(LEB) Time Period
Minimum On-Time
in IOCP
FLIM
CREF = 1.0 µF
TJ(C) = 25 °C
±7
0 °C < TJ(C) < 100 °C
±10
200
250
%
tOFF(SOA)
TJ(C) = 25 °C
300
tLEB
TJ(C) = 25 °C
See Note A
220
ns
tON_OCP(MIN)
TJ(C) = 25 °C
400
ns
ms
VCC Auxiliary Power Supply
VCC Operating Range
VCC
UVLO+
12
15
V
Start-Up VCC
(Rising Edge)
VCCUV(LO+)
0 °C < TJ(C) < 100 °C
9.6
9.85
10.1
V
Shutdown VCC
(Falling Edge)
VCCUV(LO-)
0 °C < TJ(C) < 100 °C
9.05
9.3
9.55
V
VCC Hysteresis
VCC(HYS)
0 °C < TJ(C) < 100 °C
0.50
0.57
0.65
V
UVLO Shutdown
Delay Timer
tUV(LO-)
See Note A
500
Time From VCC >
VCCUVLO+ Until Device
Commences Switching
tRESET
V > VBR+
See Note A
60
75
ms
REFERENCE Pin Voltage
VREF
0 °C < TJ(C) < 100 °C
4.95
5.25
5.45
V
REFERENCE Pin
Required Capacitance
CREF
Full Power Mode
0.8
1.0
Efficiency Mode
0.08
0.1
ns
Series Regulator
REFERENCE Pin
UVLO Rising Edge
REFUV+
0 °C < TJ(C) < 100 °C
See Note A
REFERENCE Pin
UVLO Falling Edge
REFUV-
0 °C < TJ(C) < 100 °C
See Note A
4.4
IPG(T)
0 °C < TJ(C) < 100 °C; VPGT = 3.0 V
-10.65
tPG
0 °C < TJ(C) < 100 °C; PG = 20 kW Pull-Up to
VCC, See Note A
tPG(D)
See Note A
μF
0.2
5.0
V
V
Power Good
Power Good Deassertion Threshold Output
Reference Current
Power Good Delay Time
(From FB > VPG+ to
PG < 1 V)
Power Good
Deglitch Time
-10
-9.35
VBR+
See Note A
36
°C
Parameter
Power Good (cont.)
Power Good
Deassertion Threshold
Thermal Protection (OTP)
Over-Temperature
Hysteresis
VTS MOSFET
PFS7523
PFS7533
PFS7524
PFS7534
PFS7525
PFS7535
On-State
Resistance
RDS(ON)
ID = 0.5 × IOCP
PFS7526
PFS7536
PFS7527
PFS7537
PFS7528
PFS7538
PFS7529
PFS7539
TJ(M) = 25 °C
0.61
TJ(M) =100 °C
TJ(M) = 25 °C
1.10
0.51
TJ(M) = 100 °C
TJ(M) = 25 °C
0.41
0.34
0.30
TJ(M)= 100 °C
W
0.36
0.52
0.26
TJ(M) = 100 °C
TJ(M) = 25 °C
0.42
0.62
TJ(M) = 100 °C
TJ(M) = 25 °C
0.51
0.73
TJ(M) = 100 °C
TJ(M) = 25 °C
0.63
0.92
TJ(M) = 100 °C
TJ(M) = 25 °C
0.76
0.32
0.46
0.22
0.27
0.40
25
www.power.com
Rev. A 06/15
PFS7523-7529/7533-7539
Parameter
Symbol
Conditions
SOURCE = 0 V; VCC = 12 V,
-40 °C < TJ(C) < 125 °C
(Note C) (Unless Otherwise Specified)
Min
Typ
Max
Units
VTS MOSFET
Effective Output
Capacitance
Coss
TJ(M) = 25 °C
VGS = 0 V,
VDS = 0 to 80% BVDSS
See Note A
PFS7523
PFS7533
176
PFS7524
PFS7534
210
PFS7525
PFS7535
265
PFS7526
PFS7536
312
PFS7527
PFS7537
369
PFS7528
PFS7538
420
PFS7529
PFS7539
487
Breakdown Voltage
BVDSS
TJ(M) = 25 °C, VCC = 12 V
ID = 250 mA, VFB= V V = 0 V
Breakdown Voltage
Temperature
Coefficient
BVDSS(TC)
See Note A
Off-State
Drain Current
Leakage
IDSS
VDS = 80%
BVDSS
VCC = 12 V
VFB = V V =
VC = 0
530
pF
V
0.048
%/°C
PFS7523
PFS7533
TJ(M) =100 °C
80
PFS7524
PFS7534
TJ(M) =100 °C
100
PFS7525
PFS7535
TJ(M) =100 °C
120
PFS7526
PFS7536
TJ(M) =100 °C
150
PFS7527
PFS7537
TJ(M) =100 °C
170
PFS7528
PFS7538
TJ(M) =100 °C
200
PFS7529
PFS7539
TJ(M) =100 °C
235
mA
Turn-Off Voltage
Rise Time
tR
See Notes A, B, C
50
ns
Turn-On Voltage
Fall Time
tF
See Notes A, B, C
100
ns
26
Rev. A 06/15
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PFS7523-7529/7533-7539
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Qspeed Diode (3A) PFS7523-7529/7533-7535
DC Characteristics
Reverse Current
IR
VR = 530 V
Forward Voltage
VF
IF = 3 A
Junction Capacitance
CJ
TJ(D) = 25 °C
0.4
mA
TJ(D) = 100 °C
0.07
mA
TJ(D) = 25 °C
1.55
TJ(D) = 100 °C
1.47
VR = 10 V, 1 MHz
18
V
pF
Dynamic Characteristics (Note: See Figures 19, 20 for dynamic characteristic definition)
tRR
di/dt = 200 A/μs,
VR = 400 V
IF = 3 A
Reverse Recovery
Charge
QRR
di/dt = 200 A/μs,
VR = 400 V
IF = 3 A
Maximum Reverse
Recovery Current
IRRM
di/dt = 200 A/μs,
VR = 400 V
IF = 3 A
S
di/dt = 200 A/μs,
VR = 400 V
IF = 3 A
Reverse Recovery Time
Softness Factor = tB/t A
TJ(D) = 25 °C
26.5
TJ(D) = 100 °C
32
TJ(D) = 25 °C
40.6
TJ(D) = 100 °C
65.7
TJ(D) = 25 °C
2.1
TJ(D) = 100 °C
3.0
TJ(D) = 25 °C
1
TJ(D) = 100 °C
0.45
ns
nC
A
27
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Rev. A 06/15
PFS7523-7529/7533-7539
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Qspeed Diode (6A) PFS7536-7539
DC Characteristics
Reverse Current
IR
VR = 530 V
Forward Voltage
VF
IF = 6 A
Junction Capacitance
CJ
TJ(D) = 25 °C
0.8
mA
TJ(D) = 100 °C
0.15
mA
TJ(D) = 25 °C
1.51
TJ(D) = 100 °C
1.44
VR = 10 V, 1 MHz
41
V
pF
Dynamic Characteristics (Note: See Figures 19, 20 for dynamic characteristic definition)
Reverse
Recovery
Time
tRR
di/dt = 200 A/μs,
VR = 400 V
IF = 6 A
Reverse Recovery
Charge
QRR
di/dt = 200 A/μs,
VR = 400 V
IF = 6 A
Maximum Reverse
Recovery Current
IRRM
di/dt = 200 A/μs,
VR = 400 V
IF = 6 A
S
di/dt = 200 A/μs,
VR = 400 V
IF = 6 A
Softness Factor = tB/t A
TJ(D) = 25 °C
28.5
TJ(D) = 100 °C
37.3
TJ(D) = 25 °C
58
TJ(D) = 100 °C
105.5
TJ(D) = 25 °C
2.95
TJ(D) = 100 °C
4.05
TJ(D) = 25 °C
0.53
TJ(D) = 100 °C
0.31
ns
nC
A
NOTES:
A. Not tested parameter. Guaranteed by design.
B. Tested in typical Boost PFC application circuit.
C. Normally limited by internal circuitry.
D. Test under this condition may require pulsed operation due to self-heat. Pulse parameters (duration, repetition) are TBD.
E. BVDSS 540 V maximum for 10 ns.
28
Rev. A 06/15
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PFS7523-7529/7533-7539
VR
tRR
IF
tR
dIF/dt
D1
DUT
L1
Pulse Generator
tB
15 V
RG
0
Q1
0.4xIRRM
IRRM
PI-7614-041315
Figure 20. Reverse Recovery Test Circuit.
3
Thermal Resistance of Internal Qspeed Diode is 5.2 °C/W for
PFS7523-7529, PFS7533-7535 and 2.6 °C/W for PFS7536-7539.
Thermal Resistance of Internal Power MOSFET shown below.
2.5
PI-7539-061615
Thermal Resistance θJC (°C/W)
Figure 19. Reverse Recovery Definitions.
2
1.5
1
0.5
0
PFS7523/
PFS7533
PFS7524/
PFS7534
PFS7525/
PFS7535
PFS7526/
PFS7536
PFS7527/
PFS7537
PFS7528/
PFS7538
PFS7529/
PFS7539
Figure 21. Thermal Resistance eSIP-16D / eSIP-16G Package ( θJC).
29
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Rev. A 06/15
PFS7523-7529/7533-7539
Typical Performance Characteristics
1.1
1.08
1.06
1.04
1.02
1
0.98
0.96
PI-7633-061615
I(OCP) Normalized
to Room Temperature
1.12
1.8
1.6
RDS(ON) Normalized
to Room Temperature
PI-7632-061615
1.14
1.4
1.2
1
0.8
0.6
0.4
0.2
0.94
0.92
0
-40 -20
0
20
40
60
80 100 120
-40 -20
Temperature (˚C)
250
240
230
220
0
20
40
60
80 100 120
Temperature (˚C)
Figure 24. tOFF(SOA) vs. Temperature.
60
80 100 120
1.08
PI-7635-061615
PI-7634-061615
260
-40 -20
40
Figure 23. Normalized RDS(ON) vs. Temperature.
Normalized Minimum On-Time
in IOCP (nsec)
tOFF(SOA) µs
270
20
Temperature (˚C)
Figure 22. Normalized I(OCP) vs. Temperature.
280
0
1.06
1.04
1.02
1
0.98
0.96
0.94
-40 -20
0
20
40
60
80 100 120
Temperature (˚C)
Figure 25. Normalized On-Time in IOCP vs. Temperature.
30
Rev. A 06/15
www.power.com
PFS7523-7529/7533-7539
100000
IR-3A-200 V
IR-3A-400 V
IR-3A-530 V
1000
Reverse Current (µA)
PI-7637-061615
Reverse Current (µA)
10000
100
10
PI-7638-061615
Typical Performance Characteristics
IR-6A-200 V
IR-6A-400 V
IR-6A-530 V
10000
1000
100
10
1
1
25
50
75
100
125
-40
150
50
Temperature (˚C)
125
150
Figure 27. Temperature Dependence of 6 A Qspeed Diode
Reverse Current
Scaling Factors:
PFS7523L/33H
PFS7524L/34H
PFS7525L/25H/35H
PFS7526H/36H
PFS7527H/37H
PFS7528H/38H
PFS7529H/39H
PI-7636-052615
IDSS at 80% of BVDSS (µA)
100
100
Temperature (˚C)
Figure 26. Temperature Dependence of 3 A Qspeed Diode
Reverse Current.
1000
75
1
1.2
1.5
1.8
2.1
2.4
2.8
10
1
75
100
125
150
Temperature (°C)
Figure 28. Typical Temperature Dependence of IDSS at 80%
of BVDSS.
31
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Rev. A 06/15
Rev. A 06/15
1
5
6
10 11
END VIEW
0.628 (15.95) Ref.
0.060 (1.52) Ref.
9
FRONT VIEW
7 8
Pin 1 I.D.
0.653 (16.59)
0.647 (16.43)
0.038 (0.97)
3 4
0.019 (0.48) Ref.
A
2
13 14
16
2
0.140 (3.56)
0.120 (3.05)
Detail A
0.016 (0.41) 13×
0.011 (0.28)
0.020 M 0.51 M C
3
0.021 (0.53)
0.019 (0.48)
0.048 (1.22)
0.046 (1.17)
10° Ref.
All Around
0.056 (1.42) Ref.
0.325 (8.25)
0.320 (8.13)
B
SIDE VIEW
0.081 (2.06)
0.077 (1.96)
0.027 (0.70)
0.023 (0.58)
0.020 (0.50)
0.118 (3.00)
0.047 (1.19)
0.016 (0.41)
Ref.
0.290 (7.37)
Ref.
C
eSIP-16D (H Package)
3
PCB FOOT PRINT
Dimensions in inches, (mm).
All dimensions are for reference.
0.118 (3.00)
0.029 Dia Hole
0.062 Dia Pad
BACK VIEW
4
0.024 (0.61) 13×
0.019 (0.48)
0.010 M 0.25 M C A B
0.207 (5.26)
0.187 (4.75)
0.216 (5.49)
Ref.
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions noted are determined at the outermost
extremes of the plastic body exclusive of mold flash,
tie bar burrs, gate burrs, and interlead flash, but
including any mismatch between the top and bottom
of the plastic body. Maximum mold protrusion is 0.007
[0.18] per side.
3. Dimensions noted are inclusive of plating thickness.
4. Does not include interlead flash or protrusions.
5. Controlling dimensions in inches (mm).
PI-7242-010614
0.076 (1.93)
0.038 (0.97)
0.012 (0.30) Ref.
0.076 (1.93)
0.519 (13.18)
Ref.
0.586 (14.88) Ref.
PFS7523-7529/7533-7539
32
www.power.com
www.power.com
1
5
6
END VIEW
0.628 (15.95) Ref.
0.060 (1.52) Ref.
11
13
0.056 (1.42) Ref.
9
10
FRONT VIEW
Typ. 9 Places
7
8
Pin 1 I.D.
0.038 (0.97)
3
4
0.019 (0.48) Ref.
A
2
0.653 (16.59)
0.647 (16.43)
14
16
2
0.094 (2.40)
Detail A
0.048 (1.22)
0.046 (1.17)
0.021 (0.53)
0.019 (0.48)
10° Ref.
All Around
R0.012 (0.30)
Typ., Ref.
0.016 (0.41) 13×
0.011 (0.28)
0.020 M 0.51 M C
3
0.325 (8.25)
0.320 (8.13)
B
0.081 (2.06)
0.077 (1.96)
SIDE VIEW
0.027 (0.70)
0.023 (0.58)
0.020 (0.50)
0.128 (3.26)
0.122 (3.10)
0.144 (3.66) Ref.
0.047 (1.19) Ref.
0.050 (1.26) Ref.
0.290 (7.37)
Ref.
C
eSIP-16G (L Package)
14
13
11
10
3
5
4
4
3
1
0.173 (4.39)
0.163 (4.14)
0.024 (0.61) 13×
0.019 (0.48)
0.010 M 0.25 M C A B
7
6
0.076 (1.93)
0.038 (0.97)
BACK VIEW
9
8
Dimensions in inches, (mm).
All dimensions are for reference.
PCB FOOT PRINT
0.094 (2.40)
0.029 Dia Hole
0.062 Dia Pad
16
0.216 (5.49)
Ref.
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions noted are determined at the outermost
extremes of the plastic body exclusive of mold flash,
tie bar burrs, gate burrs, and interlead flash, but
including any mismatch between the top and bottom
of the plastic body. Maximum mold protrusion is 0.007
[0.18] per side.
3. Dimensions noted are inclusive of plating thickness.
4. Does not include interlead flash or protrusions.
5. Controlling dimensions in inches (mm).
PI-7256-012114
Typ. 3 Pieces
0.076 (1.93)
0.079 (1.99)
0.069 (1.74)
0.586 (14.88) Ref.
PFS7523-7529/7533-7539
Rev. A 06/15
33
PFS7523-7529/7533-7539
Part Ordering Information
Part Number
Option
Quantity
PFS7523L/H
Tube
30
PFS7524L/H
Tube
30
PFS7525L/H
Tube
30
PFS7526H
Tube
30
PFS7527H
Tube
30
PFS7528H
Tube
30
PFS7529H
Tube
30
PFS7533H
Tube
30
PFS7534H
Tube
30
PFS7535H
Tube
30
PFS7536H
Tube
30
PFS7537H
Tube
30
PFS7538H
Tube
30
PFS7539H
Tube
30
Part Marking Information
• HiperPFS Product Family
• HiperPFS-3 Series Number
• Package Identifier
PFS 7523 L
L
Plastic eSIP, L Bend
H
Plastic eSIP
34
Rev. A 06/15
www.power.com
PFS7523-7529/7533-7539
Notes
35
www.power.com
Rev. A 06/15
Revision
A
Notes
Date
Initial Release.
06/15
For the latest updates, visit our website: www.power.com
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations
does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY
HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one
or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of
Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set
forth at http://www.power.com/ip.htm.
Life Support Policy
POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:
1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose
failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or
death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness.
The PI logo, TOPSwitch, TinySwitch, LinkSwitch, LYTSwitch, InnoSwitch, DPA-Switch, PeakSwitch, CAPZero, SENZero, LinkZero, HiperPFS,
HiperTFS, HiperLCS, Qspeed, EcoSmart, Clampless, E-Shield, Filterfuse, FluxLink, StakFET, PI Expert and PI FACTS are trademarks of Power
Integrations, Inc. Other trademarks are property of their respective companies. ©2015, Power Integrations, Inc.
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e-mail: eurosales@power.com
Japan
Kosei Dai-3 Bldg.
2-12-11, Shin-Yokohama,
Kohoku-ku
Yokohama-shi Kanagwan
222-0033 Japan
Phone: +81-45-471-1021
Fax: +81-45-471-3717
e-mail: japansales@power.com
Taiwan
5F, No. 318, Nei Hu Rd., Sec. 1
Nei Hu Dist.
Taipei 11493, Taiwan R.O.C.
Phone: +886-2-2659-4570
Fax: +886-2-2659-4550
e-mail: taiwansales@power.com
UK
First Floor, Unit 15, Meadway Court,
Korea
Rutherford Close,
RM 602, 6FL
Stevenage, Herts. SG1 2EF
Korea City Air Terminal B/D, 159-6 United Kingdom
Samsung-Dong, Kangnam-Gu,
Phone: +44 (0) 1252-730-141
Seoul, 135-728, Korea
Fax: +44 (0) 1252-727-689
Phone: +82-2-2016-6610
e-mail: eurosales@power.com
Fax: +82-2-2016-6630
e-mail: koreasales@power.com
Singapore
51 Newton Road
#19-01/05 Goldhill Plaza
Singapore, 308900
Phone: +65-6358-2160
Fax: +65-6358-2015
e-mail: singaporesales@power.com
