HiperPFS-4 Family
PFC Controller with Integrated 600 V MOSFET and Diode Option
Optimized for High PF and Efficiency Across Load Range
Key Benefits
• High efficiency and power factor across load range
• >95% efficiency from 10% load to 100% load
• 0.95 achievable at 20% load for H and L packages
• Programmable Power Good (PG) signal
• Digital line peak detection for robust performance even with
distorted input voltage from UPS or generators
• Digital power factor enhancer compensates for EMI filter and bridge
distortion
• Spread-spectrum across >60 kHz window simplifies EMI filtering
• Protection features include: UVLO, UV, OV, OTP, brown-in/out, cycleby-cycle current limit and power limiting for overload protection
• Withstands 305 VAC steady-state and 410 VAC abnormal input
• Eliminates insulating pad/heat-spreader
D
+
HiperPFS-4
VCC
PG
VCC
CONTROL
FB
C
AC
IN
DC
OUT
PGT
S
V
G
REF
PI-7965-100318
Figure 1a. Typical Application Schematic without Integrated Diode.
Applications
•
•
•
•
•
PC
Printer
LCD TV
Video game consoles
80 Plus™ Platinum
designs
D
• High-power adaptors
K
+
• High-power LED lighting
VCC
PG
• Industrial and appliance
VCC
• Generic PFC converters
CONTROL
FB
C
AC
IN
DC
OUT
PGT
HiperPFS-4
S
V
G
REF
PI-7224a-042720
Figure 1b. Typical Application Schematic with Integrated Diode.
InSOP-24B (C Package)
eSIP-16D (H Package)
eSIP-16G (L Package)
Figure 2. Package Options.
Body Dimensions: 10.8 mm x 9.4 mm for C Package and
16.53 mm x 8.25 mm for H & L Packages.
www.power.com
August 2020
This Product is Covered by Patents and/or Pending Patent Applications.
PFS7x23-7x29/7633-7636
Output Power Table
Universal Input Devices (C Package) Without Integrated Diode
Product
Continuous Output Power at 90 VAC
PFS7623C
75 W
PFS7624C
90 W
PFS7626C
105 W
PFS7628C
110 W
Universal Input Devices (H and L Packages)
Without Integrated Diode
Product
Continuous
Output Power at
90 VAC
Peak Output Power
PFS7623H/L
110 W
120 W
PFS7624H/L
130 W
150 W
PFS7625H/L
185 W
205 W
PFS7626H/L
230 W
260 W
PFS7627H/L
290 W
320 W
PFS7628H/L
350 W
385 W
PFS7629H/L
405 W
450 W
High-Line Input Only Devices (H Package)
Without Integrated Diode
Continuous
Output Power at
180 VAC
Peak Output
Power
PFS7633H
255 W
280 W
PFS7634H
315 W
350 W
PFS7635H
435 W
480 W
PFS7636H
550 W
610 W
Product
Universal Input Devices With Integrated Diode
Product
Maximum Continuous
Output Power Rating
at 90 VAC
(Full Power Mode)
Peak Output Power
(Full Power Mode)
PFS7723L/H
110 W
120 W
PFS7724L/H
130 W
150 W
PFS7725L/H
185 W
205 W
260 W
PFS7726H
230 W
PFS7727H
290 W
320 W
PFS7728H
350 W
385 W
PFS7729H
405 W
450 W
Table 1.
Output Power Table (See Table 2 on page 12 for Maximum Continuous
Output Power Ratings.)
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Rev. F 08/20
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PFS7x23-7x29/7633-7636
Description
The HiperPFS™-4 devices incorporate a continuous conduction mode
(CCM) boost PFC controller, gate driver and 600 V power MOSFET in a
single, low-profile (GROUND pin connected) power package. HiperPFS-4
devices eliminate need for external current sense resistors and their
associated power loss, and use an innovative control technique that
adjusts the switching frequency over output load, input line voltage,
and input line cycle.
This control technique maximizes efficiency over the entire load range,
particularly at light loads. Additionally, it minimizes the EMI filtering
requirements due to its wide bandwidth spread spectrum effect. The
HiperPFS-4 uses advanced digital techniques for line monitoring, line
feed-forward scaling, and power factor enhancement; while using
analog techniques for the core controller in order to maintain extremely
low no-load power consumption. The HiperPFS-4 also features an
integrated non-linear error amplifier for enhanced load transient
response, a user programmable Power Good (PG) signal as well as user
selectable power limit functionality. HiperPFS-4 includes Power
Integrations’ standard set of comprehensive protection features, such
as UV, OV, brown-in/out, and hysteretic thermal shutdown. HiperPFS-4
also provides cycle-by-cycle current limit and Safe Operating Area
(SOA) protection of the power MOSFET, output power limiting for
overload protection, and pin-to-pin short-circuit protection
HiperPFS-4’s innovative variable frequency continuous conduction
mode operation (VF-CCM) minimizes switching losses by maintaining a
low average switching frequency, while modulating the switching
frequency in order to suppress EMI, the traditional challenge with
continuous conduction mode solutions. Systems using HiperPFS-4
typically reduce the total X and Y capacitance requirements of the
converter, the inductance of both the boost choke and EMI noise
suppression chokes, thereby reducing overall system size and cost.
Additionally, HiperPFS-4 devices dramatically reduce component count
and board footprint while simplifying system design and enhancing
reliability, when compared with designs that use discrete MOSFETs and
controllers. The innovative variable frequency, continuous conduction
mode controller enables the HiperPFS-4 to realize all of the benefits of
continuous conduction mode operation while leveraging low-cost,
small, simple EMI filters.
Many regions mandate high power factor for many electronic products
with high power requirements. These rules are combined with
numerous application-specific standards that require high power supply
efficiency across the entire load range, from full load to as low as 10%
load. High efficiency at light load is a challenge for traditional PFC
solutions where fixed MOSFET switching frequencies cause fixed
switching losses on each cycle, even at light loads. In addition to
featuring flat efficiency across the load range, HiperPFS-4 also enables
a high power factor of >0.95 at 20% load. HiperPFS-4 simplifies
compliance with new and emerging energy-efficiency standards over a
broad market space in applications such as PCs, LCD TVs, notebooks,
appliances, pumps, motors, fans, printers and LED lighting.
HiperPFS-4’s advanced power packaging technology and high
efficiency simplify the complexity of mounting the IC and thermal
management, while providing very high power capabilities in a single
compact package; these devices are suitable for PFC applications with
maximum continuous power from 75 W to 405 W universal (550 W
high-line only).
Product Highlights
Protected Power Factor Correction Solution
• Incorporates 600 V power MOSFET, controller and gate driver.
• EN61000-3-2 Class C and Class D compliance.
• Integrated protection features reduce external component count
• Accurate built-in brown-in/out protection.
•
•
•
•
•
•
Accurate built-in undervoltage (UV) protection.
Accurate built-in overvoltage (OV) protection.
Hysteretic thermal shutdown (OTP).
Internal power limiting function for overload protection.
Cycle-by-cycle power-switch current limit.
Internal non-linear error amplifier for enhanced load transient
response
• No external current sense resistor required.
• Provides ‘lossless’ internal sensing via sense-FET.
• Reduces component count and system losses.
• Minimizes high current gate drive loop area.
• Minimizes output overshoot and stresses during start-up
• Integrated power limit.
• Improved dynamic response.
• Digitally controlled input line feed-forward gain adjustment for
flattened loop gain across entire input voltage range.
• Eliminates up to 39 discrete components for higher reliability and
lower cost.
Solution for High Efficiency, Low EMI and High PF
• Continuous conduction mode PFC uses novel constant amp-second
[on-time] volt-second [off-time] control.
• High efficiency across load.
• High power factor across load.
• Frequency sliding technique for light load efficiency improvements.
• >95% efficiency from 10% load to full load achievable at
nominal input voltages.
• Variable switching frequency to simplify EMI filter design.
• Varies over line input voltage to maximize efficiency and
minimize EMI filter requirements.
• Varies with input line cycle voltage by >60 kHz to maximize
spread spectrum effect.
Advanced Package for High Power Applications
(H & L Packages)
• Up to 450 W [universal], 610 W [high-line only] peak output power
capability in a highly compact package.
• Simple adhesive or clip mounting to heat sink.
• No insulation pad required and can be directly connected to
heat sink.
• Staggered pin arrangement allows simple routing of board traces
and to meet high-voltage creepage requirements.
• Single package solution for PFC converter reduces assembly costs
and layout size.
SMD Package (C Package)
• Allows the elimination of metal heat sink.
• Use PCB copper foil for heat dissipation.
Pin Functional Description
BIAS POWER (VCC) Pin
This is a 10.2-15 VDC [12 V typical] bias supply used to power the IC.
The bias voltage must be externally clamped to prevent the BIAS
POWER pin from exceeding 15 VDC to ensure long-term reliability
REFERENCE (REF) Pin
This pin is connected to an external bypass capacitor and is used to
program the IC for either FULL or EFFICIENCY power mode. The
external capacitor is connected between the REFERENCE and SIGNAL
GROUND [G] pins. Note: the return trace to the ground pin must not
be shared with other return traces that may pass large return
currents during surge events. The REFERENCE pin has two valid
capacitor values to select ‘Full’ (1.0 mF ±20%) or ‘Efficiency’ (0.1 mF
±20%) power modes.
SIGNAL GROUND (G) Pin
Discrete components used in the feedback circuit, including loop
compensation, decoupling capacitors for the BIAS POWER (VCC),
REFERENCE (REF) and VOLTAGE MONITOR (V) must be referenced to
3
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Rev. F 08/20
PFS7x23-7x29/7633-7636
the SIGNAL GROUND (G) pin. The SIGNAL GROUND pin is also
connected to the tab of the device. The SIGNAL GROUND pin should
not be tied directly to the SOURCE pin external to the IC.
VOLTAGE MONITOR (V) Pin
The VOLTAGE MONITOR pin is tied to the rectified high-voltage DC
rail through a 100:1, 1% high-impedance resistor divider to minimize
power dissipation and standby power consumption. The recommended
resistance value is between 8 MW and 16 MW. Changing this divider
ratio affects peak power limit, brown-in/out thresholds and will
degrade input current quality (reduce power factor and increase
THD). A small ceramic capacitor forming an 80 ms nominal timeconstant must be connected between the VOLTAGE MONITOR pin to
the SIGNAL GROUND pin to bypass any switching noise present on
the rectified DC bus.
This pin also features brown-in/out detection thresholds and
incorporates a weak current source that acts as a pull-down in the
event of an open circuit condition.
COMPENSATION (C) Pin
This pin is used for loop pole/zero compensation of the OTA error
amplifier via the connection of a network of capacitors and a resistor
between the COMPENSATION pin and SIGNAL GROUND pin. The
COMPENSATION pin connects internally to the output of the OTA
error amplifier and the input to the on-time and off-time controllers.
FEEDBACK (FB) Pin
This pin is connected to the main voltage regulation feedback resistor
divider network and is also used for fast over and undervoltage
protection. This pin also detects the presence of the feedback
voltage divider network at start-up and during operation. The divider
ratio should be the same as the VOLTAGE MONITOR pin for proper
H Package (eSIP-16D)
(Front View)
and optimized power limit and power factor. A large upper resistor
between 8 MW and 16 MW ±1% is recommended. A small ceramic
capacitor between FEEDBACK and SIGNAL GROUND, forming a
nominal 80 ms time-constant with the bottom resistor, is required.
POWER GOOD (PG) Pin
Use of the PG function is optional. The POWER GOOD pin is an
active low, open-drain connection which sinks current when the
output voltage is in regulation. At start-up, once the FEEDBACK pin
voltage has risen to ~95% of the internal reference voltage, the
POWER GOOD pin is asserted low.
After start-up, the output voltage threshold at which the PG signal
becomes high-impedance depends on the threshold programmed by
the POWER GOOD THRESHOLD pin resistor. When not used, the
POWER GOOD pin is left unconnected.
POWER GOOD THRESHOLD (PGT) Pin
This pin is used to program the output voltage threshold at which the
PG signal becomes high-impedance representing the PFC stage falling
out of regulation. The low threshold for the PG signal is programmed
with a resistor between the POWER GOOD THRESHOLD and SIGNAL
GROUND pins. Tying the POWER GOOD THRESHOLD to the
REFERENCE pin disables the power good function (i.e. POWER GOOD
pin remains high impedance).
SOURCE (S) Pins
These pins are the source connection of the power switch as well as
the negative bulk capacitor terminal connection.
DRAIN (D) Pin
This is the drain connection of the internal power switch.
Boost Diode Cathode (K) Pin
This is the cathode connection of the internal Qspeed diode.
H Package (eSIP-16D)
(Back View)
Pin 1 I.D.
G
L Package (eSIP-16G)
(Front View)
Exposed Pad (Backside of
Both H and L Packages)
Internally Connected to
GROUND (G) Pin
G
Pin 1 I.D.
NC
S
14
16
NC/K
13
D
9 11
PGT
S 24
S
D 16-19
7
FB
VCC
REF
G
V
C
FB
PG
PGT
S
S
D
NC
NC/K
C Package (InSOP-24B)
(Top View)
8 10
PG
1
5
V
NC/K
NC
D
S
S
PGT
PG
FB
C
V
G
REF
VCC
16 14 13 1110 9 8 7 6 5 4 3
NC 13
NC 14
NC 15
3
6
C
3 4 5 6 7 8 910 11 1314 16
REF
1
4
G
VCC
1
Exposed Pad
(Backside)
Not Shown
Note pin 16 is NC for PFS76xx and K pin for PFS772x.
C Package (InSOP-24B)
(Bottom View)
12
11
10
9
8
7
6
5
4
3
2
1
G
NC
NC
NC
PGT
PG
FB
C
V
REF
G
VCC
Exposed Pad
Connected to
DRAIN (D) Pin
PI-8616-081320
Figure 3. Pin Configuration.
4
Rev. F 08/20
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PFS7x23-7x29/7633-7636
DRAIN (D)
BOOST DIODE CATHODE (K)
BIAS POWER (VCC)
VOLTAGE MONITOR (V)
INPUT LINE INTERFACE
VV
12 V GATE DRIVER
REF SERIES/SHUNT
REGULATOR
+
-
PEAK
DETECTOR
ADC
BROWN-IN/
OUT DETECT
UVLO
Integrated Qspeed
Ultrafast Diode
(Diode option in PFS772xH/L only)
BO, BI
HL/LL
MON(PFE)
IOCP
VCC
MOFF × (VFB - VV)
~(VO-VIN)
LOW/HIGH
LINE DETECT
VBRST FBREF VPG(H) FBUV FBOFF FBOV
Off-Time Controller
CINT
PF
ENHANCER
+
REFERENCE
(REF)
IPGT
REFERENCE
AND BAND GAP
PON
FEEDBACK Pin
OV/UV/OFF
Power
MOSFET
ISNS
IOCP
+
VCC
Latch
LEB
-
TIMER
SUPERVISOR
senseFET
+
VOFF
+
VOFF
VOFF is a function of the error-voltage
(VE) and is used to reduce
the average operating frequency
as a function of output power
Frequency
Slide
HL/LL
Non-Linear OTA
+
+
OCP
-
-
FBREF
FEEDBACK
(FB)
OTA
-
POWER LIMIT
SOA RAMP
Feedback UV
VBRST
-
Feedback OFF
On-Time Controller
CINT
FBUV
-
FBOFF
+
PON × MON(PFE) × ISNS
MON(PFE) is the switch
current sense scale
factor which is a function
of the peak input voltage
Buffer and
De-Glitch
Filter
+
+
HL/LL
FBOV
+
VE
VE
Feedback OV
VFB
+
VPG(H)
REF
-
START-UP,
FMEA CHECKS
SOURCE (S)
SIGNAL GROUND (G)
IPGT
POWER GOOD
THRESHOLD
(PGT)
POWER GOOD
(PG)
COMPENSATION (C)
PI-7969a-081920
Figure 4. Functional Block Diagram.
Functional Description
The HiperPFS-4 family are variable switching frequency boost PFC
devices. It employs a constant amp-second on-time and constant
volt-second off-time control algorithm. This algorithm is used to
regulate the output voltage and shape the input current to comply
with regulatory harmonic current limits (high power factor). Integrating the switch current and controlling it to have a constant amp-sec
product over the on-time of the switch allows the average input
current to follow the input voltage. Integrating the difference
between the output and input voltage maintains a constant voltsecond balance dictated by the electro-magnetic properties of the
boost inductor and thus regulates the output voltage and power.
More specifically, the control technique sets constant volt-seconds for
the off-time (tOFF). The off-time is controlled such that:
^ V O -
V IN h # t OFF = K 1
(1)
(2)
Since the volt-seconds during the on-time must equal the voltseconds during the off-time, to maintain flux equilibrium in the PFC
choke, the on-time (tON) is controlled such that
V IN # t ON = K 1
The controller also sets a constant value of charge delivered during
each on-cycle of the power MOSFET. The charge per cycle is varied
gradually over many switching cycles in response to load changes so
it can be considered constant for a half line cycle. With this constant
charge (or amp-second) control, the following relationship is therefore
also true:
I IN # t ON = K 2
Substituting tON from (2) into (3) gives:
V IN # K 2
I IN =
(3)
(4)
K1
The relationship of (4) demonstrates that by controlling a constant
amp-second on-time and constant volt-second off-time, the input
current IIN is proportional to the input voltage VIN, therefore providing
the fundamental requirement of power factor correction.
This control produces a continuous mode power switch current
waveform that varies both in frequency and peak current value across
a line half-cycle to produce an input current proportional to the input
voltage.
5
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Rev. F 08/20
PFS7x23-7x29/7633-7636
Control Engine
The controller features a low bandwidth, high gain OTA error-amplifier
of which its non-inverting terminal is connected to an internal voltage
reference of 3.85 V. The inverting terminal of the error-amplifier is
available on the external FEEDBACK pin which connects to the output
voltage divider network with a divider ratio of 1:100 to regulate the
output voltage to 385 V nominally. The FEEDBACK pin connects
directly to the divider network for fast transient load response.
The internally sensed FET switch current is scaled by the input
voltage peak detector current sense gain (MON) then integrated and
compared with the error-amplifier signal (VE) to determine the cycle
on-time. Internally the difference between the input and output
voltage is derived and the resultant is scaled, integrated, and
compared to a voltage reference (VOFF) to determine the cycle off-time.
Careful selection of the internal scaling factors produce input current
waveforms with very low distortion and high power factor.
Line Feed-Forward Scaling Factor (MON) and PF Enhancer
The VOLTAGE MONITOR (V) pin voltage is sampled and converted by
a Δ-Σ ADC to a quantized digital value. A digital line cycle peak
detector, with dynamic time constants and multi-cycle filtering,
derives and smooths the peak of the input line voltage. This peak is
used internally to scale the gain of the current sense signal through
the MON variable. This contribution is required to reduce the dynamic
range of the control feedback signal as well as flatten the loop gain
over the operating input line range. The line-sense feed-forward gain
adjustment is proportional to the square of the peak rectified AC line
voltage and is adjusted as a function of the VOLTAGE MONITOR pin
voltage.
At high-line and light load, the feed-forward MON variable is dynamically adjusted across the line cycle in order to compensate for the line
current distortion through the EMI filter and full bridge network, and
improve power factor.
VE
Latch
RESET
IS dt
VOFF
Latch
SET
(VOUT-VIN)dt
Gate
Drive (Q)
Maximum
ON-time
Minimum
OFF-time
Timing
Supervisor
PI-5335-061615
The line-sense feed-forward gain is also important in providing a
switch power limit over the input line range.
This characteristic is optimized to maintain a relatively constant
internal error-voltage level at full load from an input line of 90 to
230 VAC.
Beyond the specified peak power rating of the device, the internal
power limit will regulate the output voltage below the set regulation
threshold as a function of output overload to maintain constant
output power. Figure 6 illustrates the typical regulation characteristic
as a function of load.
Below the brown-in threshold (VBR+) the power limit is reduced when
the device is operated in the ‘Full’ power mode as shown in Figure 7.
As the input line voltage is reduced toward the brown-out threshold
(VBR-) and if the load exceeds the power limit derating, the boost
output voltage will drop out of regulation in accordance with Figure 6.
The rated peak power shown in Table 1 is not derated for voltages
below the brown-in threshold when the device is operated in the
‘Efficiency’ mode.
Start-Up with Pin-to-Pin Short-Circuit Protection
At start-up, the engine performs a sequence of operational checks
and pin short/open evaluations, as shown in Figure 8, prior to the
commencement of switching. When the input voltage peak is above
brown-in, the engine enables switching.
The OTA error amplifier provides a non-linear amplifier (NLA)
mechanism to overcome the inherently slow feedback loop response
when the sensed output voltage on the FEEDBACK pin is outside its
regulation window. This allows the error amplifier function to limit
the maximum overshoot and undershoot during load transient events.
To reduce switch and output diode current stress at start-up, the
HiperPFS-4 calculates off-time based upon output voltage (VOUT) during
start-up, resulting in a relatively soft controlled start-up.
Once the applied VCC is above the VCCUVLO+ threshold, and the output
of the on-chip VREF regulator is above REFUV+, the value of the
REFERENCE pin capacitor is detected and the full or efficiency power
mode is latched. The pin open/short tests are performed, and if the
FEEDBACK pin voltage is valid the over-temperature OTP is checked
to be false. Once the preceding checks are satisfied the input voltage
is monitored via the VOLTAGE MONITOR pin until it exceeds the VBR+
threshold [but the peak detector is not saturated]. It is at this point
that switching is enabled.
Timing Supervisor and Operating Frequency Range
The controller operates with a variable switching frequency over the
line frequency half-cycle, typically spanning a range of 22 – 123 kHz
when operating in CCM, the controller also features a timing supervisor
function which monitors and limits the maximum switch on-time and
off-time as well as ensures a minimum cycle on-time. Figure 9(a)
shows the typical half-line frequency profile of the device switching
frequency as a function of input voltage at peak load conditions.
Figure 9(b) shows for a given line condition of 115 VAC, the effect of
EcoSmart™ on the switching frequency as a function of load.
Figure 5. Idealized Converter Waveforms.
6
Rev. F 08/20
www.power.com
0.8
0.6
0.4
0.2
0.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Normalized to Peak Output Power Rating
Figure 6. Typical Normalized Output Voltage Characteristics as Function of
Normalized Peak Load Rating for eSIP Package.
1.2
PI-7544a-112216
1.0
Normalized Minimum Power Limit
1.2
PI-7227-061615
Normalized to Set Output Voltage
Regulation Threshold
PFS7x23-7x29/7633-7636
1.0
0.8
0.6
0.4
0.2
0
PFS7623-29 70
PFS7633-39 160
75
80
170
85
90
180
95
100
190
Input Voltage (VAC)
Figure 7. Normalized Minimum Power Limit as Function of Input Voltage for
H and L Packages.
Start
NO
YES
NO
Apply Current to
C Pin for 65 µs
VCC > UVLO+
and
REF > REFUV+?
YES
Reference
Capacitor Valid?
(C > 2.5 V) or
Feedback < FBOFF
NO
Remove Current
Source on
C Pin, Short C to G
YES
Capacitor Reset:
Short C to G
for 230 µs
YES
NO
Feedback > FBOFF
YES
Remove Short
on C Pin
OTP Fault
NO
NO
Peak Valid and
Peak > VBR+
YES
Remove C to G
Short, Start
Switching
PI-7249-061615
Figure 8. Start-Up Flow Chart.
7
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Rev. F 08/20
PFS7x23-7x29/7633-7636
EcoSmart
The HiperPFS-4 includes an EcoSmart function wherein the internal
error signal (VE) is used to detect the converter output power. This
sets the average switching frequency as a function of output power.
currents constitute the majority of the load. Higher output voltage
ripple at light load is an artifact of efficient burst mode operation.
Power Good Signal (PG)
The HiperPFS-4 features a ‘power good’ (PG) circuit which comprises
an internal comparator that turns ‘on’ an open-drain switch during
start-up when the sensed output voltage on the FEEDBACK pin rises
to ~95% (VPG+) of the output voltage threshold. During start-up,
prior to the output voltage reaching VPG+, the PG signal is in a
high-impedance state (internal switch is in off-state).
As shown in Figure 10, the off-time integrator control reference (VOFF)
is controlled with respect to the internal error-voltage level (output
power) to allow the converter to maintain output voltage regulation
and relatively flat conversion efficiency from 20% to 100% of rated
load, which is essential to meet many efficiency directives. The
degree of frequency slide is also controlled as a function of input line
voltage. The lower VOFF slope as a function of input voltage reduces
the average frequency extremes for high input line operation.
135 VAC
230 VAC
180 VAC 90 VAC
115 VAC
Peak Load
45
0
90
135
180
130
120
110
100
90
80
70
60
50
40
30
20
10
0
VIN = 115 VAC
100% Peak Load
d
Expected Frequency
Range at Peak
Rated Load
P k Load
L d
75% Peak
50% Peak
a Load
25% Peak Load
0
Line Conduction Angle (°)
45
90
135
Line Conduction Angle (°)
Figure 9. (a) Frequency Variation over Line Half-Cycle as a Function of Input Voltage (b) Frequency Variation over Line Half-Cycle as a Function of Load.
Note: Frequency Profiles Shown were Analytically Derived and Reflect CCM Operation Across the Entire Line Cycle.
VA
VB
VOFF(MAX)
VOFF
VA
VIN < 140 VAC
VB
VIN > 170 VAC
4.0 V
(Full Power)
VE
4 V 5.2 V
140 VAC
VIN
170 VAC
PI-7228-061615
Figure 10. EcoSmart Frequency Slide VOFF vs. VE and VOFF(MAX) vs. Input Voltage.
8
Rev. F 08/20
PI-7232-0616154
130
120
110
100
90
80
70
60
50
40
30
20
10
0
PI-7231-061615
Frequency (kHz)
Burst-Mode for No-Load Power Consumption Reduction
Under no-load conditions the HiperPFS-4 engine is architected to
enter a burst mode which gates the power switch on and off between
fixed error voltage levels. This ensures low power consumption by
switching in bursts in order to maintain regulation when leakage
Frequency (kHz)
The power good signal transitions from ‘on’ to off-state when the
sensed output voltage on the FEEDBACK pin falls to a user selected
threshold, programmed via resistor on the POWER GOOD THRESHOLD (PGT) pin. The POWER GOOD THRESHOLD pin sources a fixed
current IPGT. This current combined with the power good threshold
resistor sets the threshold when the power good signal transitions
from the on-state to the high-impedance off-state as the PFC output
falls out of regulation.
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180
PFS7x23-7x29/7633-7636
The power good comparator has an internal 81 µs de-glitch filter (tPGD)
to prevent noise events from falsely triggering the programmed VPGthreshold.
In the event a load fault prevents the boost from achieving regulation
(above ~95% of the set output voltage threshold) the PG function will
remain in the high-impedance state and will not indicate when an
output voltage has fallen below the user programmed VPG- threshold.
The VPG- user programmed threshold is enabled once the VPG+
threshold has been reached.
If the POWER GOOD THRESHOLD programming pin is tied to
REFERENCE pin, the power good function is disabled and PG remains
in the high-impedance (‘off’) state. This is the preferred configuration when PG is not in use. If the POWER GOOD THRESHOLD pin is
shorted to the SIGNAL GROUND pin, the PG signal will transition to
the on-state at VPG+ and remain low (‘on’) until the PFC output voltage
has fallen below the VFB_UV threshold for greater than tFB_UV seconds.
Similar to the disable condition described above, if the value of the
PGT resistor is such that the VPG- threshold is greater than the VPG+
threshold, the PG signal will latch off and remain in the high-impedance off-state.
The Power Good function is not valid under the following conditions:
A. VCC or VREF are not in a valid range of operation. VCC below UVLOor VREF below REFUV- the power good function is not valid with the
POWER GOOD pin in a high-impedance state.
B. Power Good will go to high-impedance state when a soft shutdown
is initiated by an over-temperature fault to provide early indication to
secondary circuits of an OT fault.
C. PGT is outside the valid programming range of between 225 V and
360 V. PGT voltages above this range, including PGT floating, will
prevent PG from transitionning to active pull-down. PGT voltages
below this range result in PG deassertion at the output undervoltage (VFB_UV) threshold.
D. Once the start-up sequence check has passed and the converter
goes into start-up, if PGT is opened, then the PG signal will remain
latched in the high-impedance state until the controller is reset.
Selectable Power Limit
The capacitor on the REFERENCE pin allows user selection between
’full’ and ‘efficiency’ power limit for each device. The ‘efficiency’
power mode will permit user selection of a larger device for a given
output power requirement for increased conversion efficiency.
In ‘full’ power mode the REFERENCE pin capacitor is 1.0 mF ±20%
and the ‘efficiency’ power limit mode is selected with a 0.1 mF ±20%
capacitor.
If the REFERENCE pin is accidentally shorted to ground, the IC will
disable switching and remain disabled until all conditions for the
start-up sequence are satisfied..
If the REFERENCE pin is open-circuit, the absence of a bypass capacitor
will prevent start-up. During operation, an open-circuit may result in
enough REFERENCE pin noise to result in a VREF REFUV- shutdown.
Protection Modes
Brown-In Protection (VBR+)
The VOLTAGE MONITOR pin has an input line undervoltage detection
to limit the minimum start-up voltage. This detection threshold will
inhibit the device from starting at input voltages below brown-in and
above input peak voltages of 400 VPK.
Brown-Out Protection (VBR-)
The VOLTAGE MONITOR pin features a brown-out protection mode
wherein the HiperPFS-4 will turn-off when the VOLTAGE MONITOR
pin voltage is below the line undervoltage threshold (VBR-) for a
period exceeding tBRWN_OUT (brown-out debounce period). In the event
a single half-line cycle is missing (normal operating line frequency is
47 Hz to 63 Hz) the brown-out detection will not be initiated. Once
brown-out has been triggered, the HiperPFS-4 soft-shutdown
gradually reduces the internal error-voltage to zero volts over a period
of 1 ms to ramp the power MOSFET on-time to zero. The onset of
this soft-shutdown is aligned to the next line cycle zero crossing to
minimize reactive component di/dt transients and allow time for the
energy stored within the boost choke as well as the input EMI filter to
dissipate. This helps minimize voltage transients after the bridge
rectifier, which helps to prevent false restarts. The device will enter
Set internally
by VPG+
100% VOUT (385 V)
95% VOUT (365 V)
Output Voltage
Rising
87.5% VOUT (337 V)
Set externally
by RPGT
R PG = 0.875 # 3.85 = 3.37 V = 337 kX
I PG
10 nA
tPGD
tPGD
PG = High Impedance
PG = On-State
tPG
Output Voltage
Falling
PG = High Impedance
PI-7229-061615
Figure 11. Power Good Function Description.
9
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PFS7x23-7x29/7633-7636
After a brown-in event, until after the tSTARTUP timer has expired, the line
voltage brown-out threshold is reduced to VBR-NTC and the brown-out
timer is extended to tBRWN_OUT_NTC to allow for the drop in line voltage due
to an in-rush limiting negative temperature coefficient (NTC) thermistor
in series with the input line.
If the tBRWN_OUT_NTC debounce timer is triggered by the sensed line
voltage dropping below the VBR-NTC threshold but the line voltage
recovers to above the VBR-NTC threshold before the tBRWN_OUT_NTC expires,
then the tSTARTUP timer will be re-started.If the line does not recover
above the VBR-NTC threshold before the tBRWN_OUT_NTC debounce timer
expires a shutdown will occur.
After the tSTARTUP timer has expired, if the VOLTAGE MONITOR pin
voltage rises above VBR-NTC, the brown-out debounce timer will switch
to normal period (tBRWN_OUT) and the brown-out threshold will switch to
VBR-. If the VOLTAGE MONITOR pin voltage is not qualified above
VBR- after the subsequent tBRWN_OUT timer has expired then a brown-out
shutdown will occur.
HiperPFS-4 incorporates input waveform discrimination to determine
if the line signal peak-to-average ratio is more representative of a
sine wave or a high duty cycle square wave. The brown-out
threshold is reduced to VBR_SQ when a high duty cycle (UPS) square
wave is detected.
VCC Undervoltage Protection (UVLO)
The BIAS POWER (VCC) pin has an undervoltage lock-out protection
which inhibits the IC from starting unless the applied VCC voltage is
above the VCCUVLO+ threshold. The IC initiates a start-up once the
BIAS POWER pin voltage exceeds the VCCUVLO+ threshold. After
start-up the IC will continue to operate until the BIAS POWER pin
voltage has fallen below the VCCUVLO- level. The absolute maximum
voltage on the BIAS POWER pin is 17.5 V which must be externally
limited to prevent long term damage to the IC.
Line Dependent Over Current Protection (OCP) limit
The device includes a cycle-by-cycle over-current protection
mechanism which protects the device in the event of a fault. The
intent of OCP protection in this device is protection of the internal
power MOSFET and is not specifically intended to protect the converter
from output short-circuit or overload fault conditions.
For universal line input parts, the OCP limit is set as a function of the
input line voltage, one setting for low-line voltages and another
setting for high-line voltages. This helps to bound power limit into
short-circuits as well as helps to minimize the stress on the switch
due to current overloads at higher input line conditions. Figure 12
illustrates the hysteretic adjustment of the OCP levels as a function
of VOLTAGE MONITOR pin line-sensing. This equates to selecting the
low-line OCP (the greater of the two settings) when the peak of the
input line voltage drops below 140 VAC for 3 consecutive half-cycles
and selecting the high-line OCP level (the lesser of the two settings)
when the input line voltage rises above 170 VAC for 1 half-cycle,
(except in follower mode, as described in the subsequent sections).
The HiperPFS-4 utilizes a high input line OCP after detecting the
VOLTAGE MONITOR pin above the high-line threshold, VHIGH+. The
controller reverts back to low-line OCP (as well as low-line frequency
slide) only after 3 consecutive half-line cycle peak values that are
IOCP(LL)
IOCP
an auto-restart, including FMEA pin fault checks and other start-up
qualifications prior to checking for the line voltage being above the
brown-in voltage by virtue of the VOLTAGE MONITOR pin being above
VBR+.
IOCP(HL)
~140 VAC
VIN
~170 VAC
PI-7255-061615
Figure 12. Line Dependent OCP.
below the low-line threshold VHIGH-. In the event of a line drop-out,
the controller may revert from high-line to low-line parameters if the
drop-out exceeds 37 ms (nominal). High-line only input parts use a
single fixed OCP threshold.
A follower-mode feature updates the controller to high-line status
rapidly, as soon as the input voltage exceeds VHIGH+. This feature has
particular benefit for high-line hard-start conditions after a long AC
line drop-out where the peak detector may initially indicate a low
input line condition.
A leading edge blanking circuit inhibits the current limit comparator
for a short time (tLEB) after the power MOSFET is turned on. This
leading edge blanking time is set so that switch current spikes caused
by drain capacitance and rectifier reverse recovery time will not cause
premature termination of the MOSFET conduction period.
Safe Operating Area (SOA) Mode
Since the cycle-by-cycle OCP mechanism described above does not
prevent the possibility of inductor current ‘stair-casing’, an SOA mode
is also featured. Rapid build-up of the switch current can occur in the
event of inductor saturation or when the input and output voltage
differential is small combined with too little inductor reset time.
The SOA mode is triggered whenever the switch current reaches
current limit (IOCP) and the on-time is less than tSOA. The SOA mode
forces an off-time equal to tOFF(SOA) and pulls the internal error-voltage
(VE) down by 1/2 of its maximum value in order to ensure the switch
remains within its SOA.
Fast Output Voltage Overvoltage Protection (FBOV)
The HiperPFS-4 features a voltage feedback threshold comparator on
the FEEDBACK pin which detects an output voltage overvoltage
condition to allow rapid response, independent of the COMPENSATION pin response, to prevent hazardous voltage conditions from
occurring. The overvoltage protection is hysteretic – the voltage on
the FEEDBACK pin must drop by 0.1 V (equating to an output voltage
drop of 10 V) before switching is re-started.
FEEDBACK to COMPENSATION Pin Short Detection Safeguard
The PFC controller continuously monitors the FEEDBACK and
COMPENSATION pins to ensure that there are no potential short
conditions between the adjacent FEEDBACK and COMPENSATION
pins, which could result in output overvoltage conditions if not
detected. In the event a potential short is detected, a rapid short
check is performed and a shutdown is executed in the event that a
suspected short is validated.
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Open FEEDBACK Pin Protection
The FEEDBACK pin continuously sinks a static current of IFBPD [VCC
>VCCUVLO+] to protect against a fault related to an open FEEDBACK pin
or incomplete feedback divider network. The internal current sink
introduces a small static offset to the output regulation which can be
accounted for in selecting the output feedback regulation components
(FEEDBACK pin divider).
Hysteretic Thermal Shutdown
The thermal shutdown circuit senses the controller die temperature
which is well coupled to the heat sink through the exposed, grounded
pad. The threshold is set at 117 °C typical with a 36 °C hysteresis.
When the controller die temperature rises above this threshold (OTP),
the controller initiates a soft-shutdown and remains disabled until the
controller die temperature falls by ~36 °C, at which point the device
will re-initiate the start-up sequence.
The maximum time delay for soft-shutdown to occur after an OTP
event is detected is tOTP beyond the next zero-crossing.
HiperPFS-4 Additional Features and Changes
HiperPFS-4 (eSIP) maintains similar pin-out as HiperPFS-3.
• The breakdown voltage rating of the PFC MOSFET and diode has
been increased to 600 V.
• PFC output voltage can be designed for up to 440 VDC output to
allow operation with 277 VAC line voltage.
11
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PFS7x23-7x29/7633-7636
Output Power Table for H, L and C Packages
eSIP Package Without Integrated Diode
Efficiency Power Mode CREF = 0.1 mF
Product
Maximum Continuous
Output Power Rating at
90 VAC2
Full Power Mode CREF = 1.0 mF
Maximum Continuous
Output Power Rating at
90 VAC2
Peak Output Power
Rating at 90 VAC4
Minimum3
Peak Output Power
Rating at 90 VAC4
Minimum3
Maximum
PFS7623H/L
65 W
90 W
100 W
85 W
110 W
120 W
PFS7624H/L
80 W
110 W
125 W
100 W
130 W
150 W
PFS7625H/L
110 W
150 W
170 W
140 W
185 W
205 W
PFS7626H/L
140 W
190 W
215 W
180 W
230 W
260 W
PFS7627H/L
175 W
235 W
265 W
220 W
290 W
320 W
PFS7628H/L
210 W
285 W
320 W
270 W
350 W
385 W
PFS7629H/L
245 W
335 W
375 W
300 W
405 W
450 W
Efficiency Power Mode CREF = 0.1 mF
Product
Maximum Continuous
Output Power Rating at
180 VAC2
Minimum3
Maximum
PFS7633H
155 W
205 W
PFS7634H
200 W
PFS7635H
275 W
PFS7636H
350 W
460 W
Maximum
Full Power Mode CREF = 1.0 mF
Maximum Continuous
Output Power Rating at
180 VAC2
Peak Output Power
Rating at 180 VAC4
Peak Output Power
Rating at 180 VAC4
Minimum3
Maximum
230 W
195 W
255 W
260 W
290 W
240 W
315 W
350 W
360 W
400 W
335 W
435 W
480 W
510 W
415 W
550 W
610 W
280 W
InSOP Package Without Integrated Diode
Full Power Mode CREF = 1.0 mF
Maximum Continuous Output Power Rating at 90 VAC2
Product
Maximum
PFS7623C
75 W
PFS7624C
90 W
PFS7626C
105 W
PFS7628C
110 W
eSIP Package With Integrated Diode
Efficiency Power Mode CREF = 0.1 mF
Product
Maximum Continuous
Output Power Rating at
90 VAC2
Minimum3
Peak Output Power Rating at 90 VAC4
Maximum
Full Power Mode CREF = 1.0 mF
Maximum Continuous
Output Power Rating at
90 VAC2
Minimum3
Peak Output Power
Rating at 90 VAC4
Maximum
PFS7723L/H
65 W
90 W
100 W
85 W
110 W
120 W
PFS7724L/H
80 W
110 W
125 W
100 W
130 W
150 W
PFS7725L/H
110 W
150 W
170 W
140 W
185 W
205 W
260 W
PFS7726H
140 W
190 W
215 W
180 W
230 W
PFS7727H
175 W
235 W
265 W
220 W
290 W
320 W
PFS7728H
210 W
285 W
320 W
270 W
350 W
385 W
PFS7729H
245 W
335 W
375 W
300 W
405 W
450 W
Table 2. Output Power Table.
Notes:
1. See Key Application considerations.
2. Maximum practical continuous power in an open-frame design with adequate heat sinking, measured at 50 °C ambient.
3. Recommended “efficiency power mode” for best light load efficiency.
4. Internal output power limit.
12
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PFS7x23-7x29/7633-7636
Application Example for H and L Packages
coil reverse voltage during de-assertion transitions. Resistor R5 limits
the current to the diode in the optocoupler. IC U3 provides optocoupler isolation through connector J2 for a power-good output signal if
required.
A High Efficiency, 275 W, 385 VDC Universal Input PFC
The circuit shown in Figure 13 is designed using a device from the
HiperPFS-4 family of integrated PFC controllers. This design is rated
for a continuous output power of 275 W and provides a regulated
output voltage of 385 VDC nominal, maintaining a high input power
factor and overall efficiency from light load to full load.
Capacitor C15 is used for reducing the loop length and area of the
output circuit to reduce EMI and overshoot of voltage across the
drain and source of the MOSFET inside U1 at each switching edge.
The PFS7627H IC requires a regulated supply of 12 V for operation
(15 V max). Resistors R6, R7, R8, Zener diode VR1, and transistor Q2
form a series pass regulator that prevents the supply voltage to IC U1
from exceeding 15 V. Capacitors C8, and C9 filter the supply voltage
and provide bypassing and decoupling to ensure reliable operation of
IC U1. Diode D3 provides reverse polarity protection.
Fuse F1 provides protection to the circuit and isolates it from the AC
supply in the event of a fault. Diode bridge BR1 rectifies the AC input
voltage. Capacitors C1-C7 together with inductors L2 and L3 form
the EMI filter which reduces the common mode and differential mode
noise. Resistors R1, R2 and CAPZero-2, IC U2 are required to
discharge the EMI filter capacitors once the circuit is disconnected.
CAPZero-2 eliminates static losses in R1 and R2 by only connecting
these components across the input when AC is removed.
Resistor R15 programs the output voltage level [via the POWER
GOOD THRESHOLD (PGT) pin] below which the POWER GOOD [PG]
pin will go into a high-impedance state. Capacitor C14 provides noise
immunity on the POWER GOOD THRESHOLD pin.
Metal oxide varistor (MOV) RV1 protects the circuit during line surge
events by effectively clamping the input voltage seen by the power
supply.
IC U1 is configured in full power mode by capacitor C10 which is
connected to the REFERENCE pin.
Inductor L1 and boost diode D4 in conjunction with HiperPFS-4 IC U1,
form the boost converter stage, controlling the input current of the
power supply while simultaneously regulating the output DC voltage.
Diode D2 prevents a resonant buildup of output voltage at start-up by
bypassing inductor L1 while simultaneously charging output capacitor
C18.
The rectified AC input voltage of the power supply is sensed by IC U1
using resistors R10-R13. These resistors values are large to minimize
power consumption. Capacitor C11 connected in parallel with the
bottom resistor R13 filters noise coupled into the VOLTAGE MONITOR
pin.
Output voltage divider network comprising resistors R16 – R19 are
used to scale the output voltage and provide feedback to the IC.
Capacitor C16 in parallel with resistor R19 attenuates high frequency
noise.
Thermistor RT1 limits the inrush input current of the circuit at start-up
and prevents saturation of L1. However in the highest efficiency
designs, an electro-mechanical relay RL1 will be used to bypass the
thermistor once the output voltage is in regulation as indicated by a
power good signal (asserted low). Resistors R3 and R4, and transistor
Q1, drive relay RL1 and optocoupler U3. Diode D1 clamps the relay
Components R14, C12 and C13 are required for shaping the loop
response of the feedback network.
D2
1N5408-T
D4
LXA06T600
C3
330 nF
275 VAC
F1
5A
L
RT1
2.5 Ω
t
C1
680 pF
250 VAC
90 - 264
VAC
E
BR1
GBU8K-BP
800 V
O
R1
510 kΩ
C5
680 pF
250 VAC
D1
L2
9 mH
CAPZero
U2
CAP200DG
C2
680 pF
250 VAC
C4
330 nF
275 V
RV1
520 VAC
R10
6.2 MΩ
1%
R16
3.74 MΩ
1%
PG
VCC
R11
6.2 MΩ
1%
CONTROL
D2
R2
510 kΩ
FB
C
R12
3.74 MΩ
1%
PGT
HiperPFS-4
U1
PFS7627H
S
N
V
G
REF
L3
330 µH
R4
16.2 kΩ
1%
R3
10 kΩ
1%
Q1
MMBT4403
J4-1
R6
1Ω
1%
Q2
MMBT4401LT1G
R14*
30.1 kΩ
1%
Power
Good
J2-1
U3
LTV817A
D1
S1AB-13-F
1
VCC
Supply
2
4
R7
1Ω
1%
RL1
J4-2
C8
47 µF
50 V
C10
1 µF
50 V
VR1
BZX384-B13,115
13 V
+
C15
10 nF
1 kV
R15
332 kΩ
1%
R8
2.21 kΩ
1%
DC
OUT
3
D3
S1AB-13-F
J2-2
C18
180 µF
450 V
R13
162 kΩ
1%
+
R5
3.01 kΩ
1%
+
J3-1
R17
6.2 MΩ
1%
R18
6.2 MΩ
1%
D
C7
680 nF
630 V
C6
680 pF
250 VAC
VO
L1
400 µH
C9
1 µF
35 V
C12*
100 nF
25 V
C13*
1 µF
50 V
C14
1 nF
50 V
C16
470 pF
50 V
R19
162 kΩ
1%
C11
470 pF
50 V
VO
PI-8054a-120418
J3-3
Figure 13. 275 W PFC using PFS7627H (*Note: Use R14 = 20 kW, C13 = 2.2 mF, C12 = 150 nF When Designing with PFS7626C and PFS7628C).
13
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PFS7x23-7x29/7633-7636
Design, Assembly, and Layout Considerations
Power Table
The data sheet power table as shown in Table 2 represents the
maximum practical continuous output power based on the following
conditions:
For the universal input devices (PFS7x23L/H – PFS7629H):
1. An input voltage range of 90 VAC to 264 VAC.
2. Overall efficiency of at least 93% at the lowest operating voltage.
3. 385 V nominal output.
4. Sufficient heat sinking to keep device temperature ≤100 ºC.
Operation beyond the limits stated above will require de-rating.
Operation at elevated temperatures could result in reduced MTBF and
performance degradation, e.g. reduced efficiency, reduced power
limit, PF, and potential of observing hysteretic brown-out, etc., and is
not recommended.
HiperPFS-4 Selection
Selection of the optimum HiperPFS-4 part depends on required
maximum output power, PFC efficiency and overall system efficiency
(when used with a second stage DC-DC converter), heat sinking
constraints, system requirements and cost goals. The HiperPFS-4
part used in a design can be easily replaced with the next higher or
lower part in the power table to optimize performance, improve
efficiency or for applications where there are thermal design
constraints. Minor adjustments to the inductance value and EMI filter
components may be necessary in some designs when the next higher
or the next lower HiperPFS-4 part is used in an existing design for
performance optimization.
Every HiperPFS-4 family part has an optimal load level where it offers
the most value. Operating frequency of a part will change depending
on load level. Change of frequency will result in change in peak to
peak current ripple in the inductance used. Change in current ripple
will affect input PF and total harmonic distortion of input current.
Input Fuse and Protection Circuit
The input fuse should be rated for a continuous current above the
input current at which the PFC turns-off due to input undervoltage.
This voltage is referred to as the brown-out voltage.
The fuse should also have sufficient I2t rating in order to avoid
nuisance failures during start-up. At start-up a large current is drawn
from the input as the output capacitor charges to the peak of the
applied voltage. The charging current is only limited by any inrush
limiting thermistors, impedance of the EMI filter inductors and the
forward resistance of the input rectifier diodes. A MOV will typically
be required to protect the PFC from line surges. Selection of the
MOV rating will depend on the energy level (EN1000-4-5 Class level)
which the PFC is required to withstand.
A suitable NTC thermistor should be used on the input side to provide
inrush current limiting. Choice of this thermistor should depend on
the inrush current specification for the power supply. NTC thermistors may not be placed in any other location in the circuit as they fail
to limit the stress on the part in the event of line transients and also
fail to limit the inrush current in a predictable manner. The example
in Figure 13 shows the circuit configuration that has the inrush
limiting NTC thermistor on the input side which is bypassed with a
relay after PFC start-up. This arrangement ensures that a consistent
inrush limiting performance is achieved by the circuit.
Input EMI Filter
The variable switching frequency of the HiperPFS-4 effectively
modulates the switching frequency and reduces conducted EMI peaks
associated with the harmonics of the fundamental switching frequency.
This is particularly beneficial for the average detection mode used in
EMI measurements.
The PFC is a switching converter and will need an EMI filter at the
input in order to meet the requirements of most safety agency
standards for conducted and radiated EMI. Typically a common
mode filter with X capacitors connected across the line will provide
the required attenuation of high frequency components of input
current to an acceptable level. The leakage reactance of the common
mode filter inductor and the X capacitors form a low pass filter. In
some designs, additional differential filter inductors may have to be
used to supplement the differential mode inductance of the commonmode choke.
A filter capacitor with low ESR and high ripple current capability
should be connected at the output of the input bridge rectifier. This
capacitor reduces the generation of the switching frequency
components of the input current ripple and simplifies EMI filter
design. Typically, 0.33 mF per 100 W should be used for universal
input designs and 0.15 mF per 100 W of output power should be used
for 230 VAC only designs.
It is often possible to use a higher value of capacitance after the
bridge rectifier and reduce the X capacitance in the EMI filter.
For applications where PF at light load is important, be aware that all
capacitors prior to the boost stage are not corrected for PF and thus
the larger the capacitor value may degrade PF performance at light
load
Regulatory requirements require use of a discharge resistor to be
connected across the input X capacitance on the AC side of the
bridge rectifier. This is to ensure that residual charge is dissipated
after the input voltage is removed when the capacitance is higher
than 0.1 mF. Use of CAPZero-2 integrated circuits from Power
Integrations, helps eliminate the steady-state losses associated with
the use of discharge resistors connected permanently across the X
capacitors.
Inductor Design
For ferrite inductors the optimal design has KP of 0.3 to 0.45. (KP is
defined as the current peak-to-peak value divided by the peak value
at minimum AC voltage and 90° phase angle, full load). KP 0.45 tends towards excessive winding AC resistance losses due to
large high-frequency AC currents, especially since most ferrite
inductor designs will require >3 winding layers. Flux density at
maximum current limit should be 2.42 V
2.6
2.8
3.0
VV < 2 V
4.5
4.8
5.1
V V > 2.42 V
3.0
3.3
3.5
VV < 2 V
6.8
7.2
7.5
V V > 2.42 V
4.6
4.9
5.25
3.15
3.33
3.47
PFS7628C
di/dt = 250 mA/ms
TJ(C) = 25 °C
A
24
Rev. F 08/20
www.power.com
PFS7x23-7x29/7633-7636
Parameter
Symbol
Conditions
SOURCE = 0 V; VCC = 12 V,
-40 °C < TJ(C) < 125 °C
(Note C) (Unless Otherwise Specified)
Min
Typ
Max
VV < 2 V
3.8
4.1
4.3
V V > 2.42 V
2.6
2.8
3.0
VV < 2 V
4.5
4.8
5.1
V V > 2.42 V
3.0
3.3
3.5
VV < 2 V
5.5
5.9
6.2
V V > 2.42 V
3.6
4.0
4.4
VV < 2 V
6.8
7.2
7.5
V V > 2.42 V
4.6
4.9
5.25
VV < 2 V
8.0
8.4
8.8
V V > 2.42 V
5.35
5.8
6.2
VV < 2 V
9.0
9.5
9.9
V V > 2.42 V
6.0
6.5
7.1
VV < 2 V
10
10.5
11
V V > 2.42 V
6.7
7.2
7.7
PFS7633H
di/dt = 250 mA/ms
TJ(C) = 25 °C
3.8
4.1
4.3
PFS7634H
di/dt = 300 mA/ms
TJ(C) = 25 °C
4.5
4.8
5.1
PFS7635H
di/dt = 400 mA/ms
TJ(C) = 25 °C
5.5
5.9
6.2
PFS7636H
di/dt = 500 mA/ms
TJ(C) = 25 °C
6.8
7.2
7.5
Units
Current Limit/Circuit Protection (cont.)
PFS7x23H/L
di/dt = 250 mA/ms
TJ(C) = 25 °C
PFS7x24H/L
di/dt = 300 mA/ms
TJ(C) = 25 °C
PFS7x25H/L
di/dt = 400 mA/ms
TJ(C) = 25 °C
PFS7x26H
di/dt = 500 mA/ms
TJ(C) = 25 °C
PFS7x27H
di/dt = 650 mA/ms
TJ(C) = 25 °C
Over-Current
Protection
IOCP
PFS7x28H
di/dt = 800 mA/ms
TJ(C) = 25 °C
PFS7x29H
di/dt = 920 mA/ms
TJ(C) = 25 °C
Normalized Frequency
at Power Limit
FLIM
SOA Protection
Fixed Off-Time
±7
0 °C < TJ(C) < 100 °C
±10
200
250
%
tOFF(SOA)
TJ(C) = 25 °C
tLEB
TJ(C) = 25 °C
See Note A
220
ns
tON_OCP(MIN)
TJ(C) = 25 °C
400
ns
Leading Edge Blanking
(LEB) Time Period
Minimum On-Time
in IOCP
CREF = 1.0 µF
TJ(C) = 25 °C
A
300
ms
VCC Auxiliary Power Supply
VCC Operating Range
Start-Up VCC
(Rising Edge)
VCC
VCCUV(LO+)
0 °C < TJ(C) < 100 °C
UVLO+
12
15
V
9.6
9.85
10.1
V
25
www.power.com
Rev. F 08/20
PFS7x23-7x29/7633-7636
Parameter
Symbol
Conditions
SOURCE = 0 V; VCC = 12 V,
-40 °C < TJ(C) < 125 °C
(Note C) (Unless Otherwise Specified)
Min
Typ
Max
Units
VCC Auxiliary Power Supply (cont.)
Shutdown VCC
(Falling Edge)
VCCUV(LO-)
0 °C < TJ(C) < 100 °C
9.05
9.3
9.55
V
VCC Hysteresis
VCC(HYS)
0 °C < TJ(C) < 100 °C
0.50
0.57
0.65
V
UVLO Shutdown
Delay Timer
tUV(LO-)
See Note A
500
Time From VCC >
VCCUVLO+ Until Device
Commences Switching
tRESET
V > VBR+
See Note A
60
75
ms
REFERENCE Pin
Voltage
VREF
0 °C < TJ(C) < 100 °C
4.95
5.25
5.50
V
REFERENCE Pin
Required Capacitance
CREF
Full Power Mode
0.8
1.0
Efficiency Mode
0.08
0.1
ns
Series Regulator
0.2
μF
REFERENCE Pin
UVLO Rising Edge
REFUV+
0 °C < TJ(C) < 100 °C
See Note A
REFERENCE Pin
UVLO Falling Edge
REFUV-
0 °C < TJ(C) < 100 °C
See Note A
4.4
Power Good Deassertion Threshold Output
Reference Current
IPG(T)
0 °C < TJ(C) < 100 °C; VPGT = 3.0 V
-10.65
Power Good Delay
Time (From FB > VPG+
to PG < 1 V)
tPG
0 °C < TJ(C) < 100 °C; PG = 20 kW Pull-Up to VCC,
See Note A
Power Good
Deglitch Time
tPG(D)
See Note A
57
81
108
ms
Power Good Internal
Assertion Threshold
VPG(+)
0 °C < TJ(C) < 100 °C
3.55
3.65
3.75
V
Power Good Relative
Threshold
VPG+REL(FB)
0 °C < TJ(C) < 100 °C
VFBREF
-0.24
VFBREF
-0.20
VFBREF
-0.16
VPG(-)
V (PGT) = 3 V
0 °C < TJ(C) < 100 °C
2.94
V (PGT)
±30 mV
3.06
V
POWER GOOD Pin
Leakage Current in
Off-State
IOZHPG
FB < VPG(-)
0 °C < TJ(C) < 100 °C
500
nA
POWER GOOD Pin
On-State Voltage
VOLPG
0 °C < TJ(C) < 100 °C
IPG = 2.0 mA; FB = 3.85 V
2
V
Controller Junction
Temperature (TJ(C)) for
Shutdown
TOTP+
See Note A
117
°C
Controller Junction
Temperature (TJ(C)) for
Restart
TOTP-
See Note A
81
°C
TOTP(HYST)
V > VBR+
See Note A
36
°C
5.0
V
V
Power Good
Power Good
Deassertion Threshold
-10
-9.35
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