TFS7701-7708
™
HiperTFS-2
Family
Combined Two-Switch Forward and Flyback Power Supply Controllers
with Integrated High-Voltage MOSFETs
Product Enhancements
•
•
Selectable 132 kHz main switching frequency for lower cost
and smaller magnetics
Increased main peak power vs. HiperTFS-1
Self-biased high-side driver eliminates high-side bias winding
and diode
Package lead form and pinout modified for easier insertion and
PC-board layout
Tighter UV(ON) standby threshold tolerance
Improved standby no-load performance
•
•
•
•
•
•
•
•
Typical Applications
• PC (80 PLUS® Bronze and 80 PLUS Silver)
• Printer
• LCD TV
• Video game consoles
• High-power adapters
• Industrial and appliance
Key Benefits
• Single IC solution for two-switch forward main (66 kHz/132 kHz)
and flyback (132 kHz) standby
• High integration allows smaller form factor and higher power
density designs, with reduced component count
• Incorporates control, gate drivers, and three power MOSFETs
• Level shift technology eliminates need for pulse transformer
• Protection features include: UV, OV, OTP, OVP, standby OPC,
SCP, and ILIMIT
• Transformer reset control, prevents saturation under all conditions
• Main duty cycle operation above 50% for reduced rms currents
and lower output diode voltage rating
• Less than 10% variation in standby overload power over input
voltage range
Output Power Table
TFS7701H
TFS7702H
L
DC Input
(VDC)
FB
EN
HS
TFS7703H
229 W
375 W
20 W
TFS7704H
251 W
419 W
20 W
TFS7705H
269 W
466 W
20 W
TFS7706H
298 W
513 W
20 W
TFS7707H
322 W
553 W
20 W
TFS7708H
343 W
586 W
20 W
Two-Switch
Forward
Transformer
Main
Output
D
Standby
Output
RTN
DSB
*
FB
Standby Flyback
Transformer
EN
*
*
*
EN
FB
BP
G
Flyback
100 V - 400 V
Continuous
(50 °C)
20 W
20 W
Table 1. Output Power Table.
Notes:
1. Maximum practical continuous power in an open frame design with adequate
heat sinking to maintain a heat sink temperature ≤95 ºC (see Key Applications
Considerations for more information) measured at specified ambient temperature.
2 Peak load less than 10 seconds and average power less than maximum
continuous load.
3. Package: eSIP-16F. (Note: Direct attach to heat sink, does not require insulation
SIL pad).
HD
Control, Gate Drivers, Level Shift
R
Two-Switch Forward
380 V
Continuous1
Peak2
(50 °C)
148 W
187 W
190 W
297 W
Product 3
+
HiperTFS-2 VDDH
Up to 586 W peak output power in a highly compact package
>90% efficiency at full load
Simple clip mounting to heat sink without need for insulation pad
Halogen free and RoHS compliant
eSIP-16F (H Package)
Figure 2.
S
Package Option.
*Simplified feedback circuit
PI-7078-082213
Figure 1.
Schematic of Two-Switch Forward and Flyback Converter.
www.power.com
April 2015
This Product is Covered by Patents and/or Pending Patent Applications.
TFS7701-7708
Section List
Description................................................................................................................................................................... 3
Product Highlights....................................................................................................................................................... 3
Pin Functional Description.......................................................................................................................................... 5
Pin Configuration....................................................................................................................................................... 5
Functional Block Diagram......................................................................................................................................6-7
Functional Description ................................................................................................................................................ 8
Design, Assembly and Layout Considerations...................................................................................................... 14
Layout Considerations............................................................................................................................................... 17
Transformer Secondary and Output Diodes............................................................................................................ 21
Main Converter Typical Waveforms.......................................................................................................................... 22
Quick Design Checklist.............................................................................................................................................. 23
Design Example.......................................................................................................................................................... 25
Absolute Maximum Ratings...................................................................................................................................... 27
Parameter Table...................................................................................................................................................... 27
Package Details ......................................................................................................................................................... 34
Part Ordering Information......................................................................................................................................... 40
Part Marking Information ......................................................................................................................................... 41
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Rev. B 04/15
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TFS7701-7708
Description
The HiperTFS-2 device family members incorporate both a
high-power two-switch-forward converter and a mid-power
flyback (standby) converter into a single, low-profile eSIP™
power package. The single chip solution provides the controllers
for the two-switch-forward and flyback converters, high- and
low-side drivers, all three of the high-voltage power MOSFETs,
and eliminates the converter’s need for costly external pulse
transformers. The device is ideal for high power applications
that require both a main power converter (two-switch forward)
up to 586 W peak, and standby converter (flyback) up to 20 W.
HiperTFS-2 includes Power Integrations’ standard set of
comprehensive protection features, such as integrated softstart, fault and overload protection, and hysteretic thermal
shutdown. HiperTFS-2 utilizes advanced power packaging
technology that simplifies the complexity of two-switch forward
layout, mounting and thermal management, while providing very
high power capabilities in a single compact package. The
devices operate over a wide input voltage range, and can be
used following a power-factor correction stage such as HiperPFS.
Two-switch-forward power converters are often selected for
applications demanding cost-effective converters that have high
efficiency, fast transient response, and high rejection to line
voltage variation. The two-switch-forward controller
incorporated into HiperTFS-2 devices improves on the classic
topology by allowing operation considerably above 50% duty
cycle. This improvement reduces RMS current conduction
losses, minimizes the size and cost of the bulk capacitor, and
minimizes output diode voltage ratings. The advanced design
also includes transformer flux reset control (saturation protection)
and charge-recovery switching of the high-side MOSFET, which
reduces switching losses. This combination of innovations
yields an extremely efficient power supply with smaller
MOSFETs, fewer passives and discrete components, and a
lower-cost smaller transformer.
HiperTFS-2’s flyback standby controller and MOSFET solution is
based on the highly popular TinySwitch™ technology used in
billions of power converter ICs due to its simplicity of operation,
light load efficiency, and rugged, reliable, performance. This
flyback converter can provide up to 20 W of output power and
the built-in overload power compensation reduces component
design margin.
Product Highlights
Protected Two-Switch Forward and Flyback
Combination Solution
• Incorporates three high-voltage power MOSFETs, main and
standby controllers, and gate drivers
• Level shift technology eliminates need for pulse transformer
• Programmable line undervoltage (UV) detection prevents
turn-off glitches
• Programmable line overvoltage (OV) detection; latching and
non-latching
•
•
•
•
•
•
Accurate hysteretic thermal shutdown (OTP)
Accurate selectable cycle-by-cycle current limit (main and
standby)
• Line compensated standby MOSFET current limit for
standby over power compensation (OPC)
Fully integrated soft-start to minimize start-up stress
Simple fast AC reset
Reduced EMI
• Synchronized 66/132 kHz forward and 132 kHz flyback
converters
• Frequency jitter
Eliminates up to 30 discrete components for higher reliability
and lower cost
Asymmetrical Two-Switch Forward Reduces Losses
• Allows >50% duty cycle operation
• Reduces primary-side RMS currents and conduction losses
• Minimizes the size and cost of the bulk capacitor
• Allows reduced capacitance or longer hold-up time
• Allows lower voltage output diodes for higher efficiency
• Transformer reset control
• Prevents transformer saturation under all conditions
• Extends duty cycle to satisfy AC cycle drop out ride through
• Duty cycle soft-start
• Satisfies 2 ms ~ 20 ms start-up with large capacitance at
output
• Self-biased high-side driver eliminates high-side bias winding
(66 kHz)
• Remote-on/off function
• Voltage-mode controller with current limit
20 W Flyback with Selectable Power Limit
• TinySwitch-III based converter
• Selectable power limit (10 W, 12.5 W, 15 W, 20 W)
• Built-in overload power compensation (OPC)
• Flat overload power vs. input voltage
• Reduces component stress during overload conditions
• Reduces required design margin for transformer and output
diode
• Output overvoltage (OVP) protection with fast AC reset
• Latching, non-latching, or auto-restart
• Output short-circuit protection (SCP) with auto-restart
Advanced Package for High Power Applications
• Up to 586 W peak output power capability in a highly
compact package
• Simple clip mounting to heat sink
• Can be directly connected to heat sink without insulation pad
• Provides lower thermal resistance than a TO-220
• Heat slug connected to ground potential for low EMI
• Two row lead form for easy insertion into PC-board
• Single power package for two power converters reduces
assembly costs and layout size
3
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Rev. B 04/15
TFS7701-7708
Typical Two-Switch
Forward
HiperTFS-2
Nominal Duty Cycle
33%
45%
Maximum Duty Cycle
15 mA into the BYPASS pin to cause latching shut-off of both
converters. Resetting requires the BYPASS pin voltage to fall
below 4.8 V.
High Current
Trace with
Large di/dt
Figure 17.
Ok
Good Good
PI-7013-050313
The PCB Trace from the Bulk Capacitor to the SOURCE Pin Contains
Currents with Large di/dt. Do not Return any Small Signal Ground
Connections to this Trace, Such as Small Signal Bypass Capacitors,
or Optocouplers.
Bypass Capacitors
The BYPASS pin and ENABLE pin bypass capacitors must be
connected with short traces to the GROUND pin. Likewise, the
VDDH bypass capacitor must be connected with short traces
to the HIGH-SIDE SOURCE pin.
Primary Return (B-) Routing for HiperTFS-2 and PFC MOSFET
When the HiperTFS-2 shares a heat sink with a HiperPFS or
other PFC MOSFET, there is potential for noise coupling to
cause misbehavior, due to the very high di/dt associated with
the PFC diode reverse recovery. The metal in the backside of
the HiperTFS-2 is internally connected to the SOURCE pin and
thus the heat sink will be at SOURCE pin potential. The heat
sink should not be used to conduct current. The HiperTFS-2
requires a dedicated PCB trace from the SOURCE pin to the
bulk capacitor B- pin. The HiperPFS (or PFC MOSFET Source)
requires a separate PCB trace to the bulk capacitor B- pin. The
bulk capacitor is preferably placed between the HiperPFS and
HiperTFS-2. The heat sink must have a single connection to the
PFC SOURCE pin, which must be as close as possible to the
PFC MOSFET. Because of the PFC’s higher di/dt, the bulk
capacitor should be closer to the PFC than to the HiperTFS-2.
See Figure 18.
Standby Primary Bias (VAUX ) Capacitor Ground Routing
The primary VAUX output filter capacitor negative terminal should
be routed to the bulk capacitor B- terminal. This is to prevent
the large noise currents that flow during common-mode surge
and ESD, from flowing in the HiperTFS-2 small-signal PCB
ground traces and creating ground bounce issues.
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Rev. B 04/15
TFS7701-7708
Heat Sink
Heat Sink
Foot
HiperTFS-2
PFC
S
Bulk
Capacitor
S
BBad
Ok
Best
Bad
PI-7029-053013
Figure 18. Proper Heat Sink, TFS-2, and PFC Connections to the Bulk Capacitor, are Necessary to Prevent Interference. PFC and HiperTFS-2 both need Dedicated
Return Traces to Bulk Capacitor B-. Bulk Capacitor is PReferably Placed Between the PFC and HiperTFS-2.
Standby
Flyback
HiperTFS-2
Bulk
Capacitor
VAUX
G
S
Bad
Good
Ok
PI-7014-053013
Figure 19. The (-) Terminal of the VAUX Capacitor Should be Connected to B- of the Bulk Capacitor, and not to the Ground Traces. This will Improve Lightning Surge and
ESD Immunity, due to Capacitive Displacement Currents Flowing Through the Primary-to-Secondary Capacitance in the Flyback Transformer.
Y Capacitor Connections
Y class safety capacitors connected across the isolation barrier,
should be routed directly to the positive of the bulk capacitor,
and preferably to B+ instead of B- to divert surge and ESD
currents away from the HiperTFS-2 small signal components
and PCB traces. See Figure 20.
This will also improve surge and ESD immunity. The secondaryside of the Y capacitor should be connected to the main
transformer secondary return pin. This will reduce the height of
thin “spikes” coincident with the main converter switching
edges in the output ripple, which comes from common-mode
switching noise. See Figure 21.
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Rev. B 04/15
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TFS7701-7708
Best
HD
Bulk
Capacitor
HiperTFS-2
S
Good
Not
Recommended
Bad
Y
Capacitor
Bad
PI-7011-052913
Figure 20. Recommended Y Capacitor Connections to Improve Surge and ESD Immunity and Output Ripple High-Frequency Noise.
Large Spikes Caused by
Incorrect Y Capacitor
Secondary Location
VIN
*R1
Normal
Switching Ripple
HiperTFS-2
C1 *C2
VDDH
CONTROL
VHIGH_BIAS
Place all These
Components
Close to
VDDH, HS
HD
HS
Cathode Close
to C2
PI-7020-051713
PI-7000-052113
Figure 21.
Close-up of Output Ripple Voltage Showing Large Spikes. These
Spikes are Often Caused by Common-Mode Switching Noise
Appearing in the Output. A Poor Secondary Layout or a Y Capacitor
Connected to the Output Connector Instead of to the Transformer
Secondary GROUND Pin, can Cause the Spikes.
STANDBY DRAIN, MAIN DRAIN, HIGH-SIDE SOURCE, and
HIGH-SIDE OPERATING VOLTAGE Pins
The STANDBY DRAIN, MAIN DRAIN, HIGH-SIDE SOURCE, and
HIGH-SIDE OPERATING VOLTAGE pins are high-voltage switching
nodes with high dv/dt and must be kept away from the traces
connected to low voltage small signal pins (i.e., LINE-SENSE,
RESET, FEEDBACK, ENABLE pins). Stray capacitance between
them will cause capacitive noise injection. The small components
connected to the HIGH-SIDE OPERATING VOLTAGE pin also
have high dv/dt with respect to the other small signal traces.
Place them close to the HIGH-SIDE OPERATING VOLTAGE pin
and away from the other small signal traces. Also place the
Figure 22.
VDDH Components Exhibit Large dv/dt and Should be Mounted Close
to the HIGH-SIDE SOURCE and VDDH pins. The Diode Should be
Mounted Close to the VDDH Pin so that the Cathode Trace can be
Made Short. The Anode Trace is Connected to VAUX and is Quiet.
bootstrap diode (if used, required for 132 kHz), close to the
HIGH-SIDE OPERATING VOLTAGE pin.
LINE-SENSE and RESET
Care must be taken to avoid noise injection into the LINE-SENSE
and RESET pins. These pins have multiple series resistors in
order to reduce the voltage stress per resistor. See Figure 23.
The series resistors in each chain do not have to be the same
type or value. If they have different maximum voltage ratings,
they should have different values, proportional to their voltage
ratings. If the resistors are different types with different
withstand voltage ratings, (e.g., 0805 SMD for R25 and R36,
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Rev. B 04/15
TFS7701-7708
and through-hole for the others), their values should be
proportional to their voltage ratings (while maintaining the correct
total series value).
C2
2.2 nF
1 kV
R12
1.33 MΩ
1%
R13
1.33 MΩ
1%
R12
100 Ω
1/2 W
R18
1.33 MΩ
1%
R19
1.33 MΩ
1%
The last resistor in the series chain, should be connected to the
LINE-SENSE and RESET pins, (R35 and R36 in Figure 23) must
be SMD type and placed very close to their associated pins.
HiperTFS-2
The traces that feed these pins, and the additional series
resistors, should not be placed close to any high dv/dt traces
and areas with high-voltage switching. Noise on these pins
may cause distortion of the various functions determined by the
LINE-SENSE and RESET pins, such as LINE-SENSE pin UVLO,
and LINSE-SENSE and RESET pin duty cycle limiting. For
optimal performance, the LINSE-SENSE and RESET pins are
located in between the BYPASS and GROUND pins which have
DC voltages, so that the traces connecting to the DC voltages
can act as Faraday shields for the traces connected to the
LINSE-SENSE and RESET pins. See Figure 24.
R36
1.33 MΩ
1%
R
Place These Components
as Close as Possible to the
LINE-SENSE and RESET Pins
L
R35
1.33 MΩ
1%
PI-7021-060313
Figure 23. LINE-SENSE and RESET Pin Resistor Chain. The Highlighted Resistors
Should be SMD Type and Placed as Close as Possible to Their
Respective Pins.
Feedback and Enable Pins
The FEEDBACK and ENABLE pins should likewise be kept
away from noisy, high-voltage switching areas. If it is unavoidable
to have long traces connecting to FEEDBACK pins, then route
these traces parallel to and close to, quiet, low impedance
traces that act as Faraday shields, such as VAUX or BP.
20
Rev. B 04/15
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TFS7701-7708
Transformer Secondary and Output Diodes
Flyback Layout
The diode and output capacitor should be mounted close to the
secondary winding and routed with short traces. The standby
GROUND
Pin
primary bias (VAUX ) capacitor and diode should be mounted
close to the winding.
LINE-SENSE
Pin
BYPASS
Pin
RESET
Pin
Bypass
Capacitor
MAIN DRAIN
Pin (Noisy)
BYPASS Pin
Trace Acting
as Shield
GROUND Pin
Trace Acting
as Shield
High-Side Source
Trace (Noisy)
LINE-SENSE AND
RESET Pin Resistors
(SMD)
PI-7012-052113
Figure 24. LINE-SENSE and RESET Pin Resistor Layout. The 2 Resistors Connected to LINSE-SENSE and RESET Pins Should be SMD, and the GROUND and BYPASS
Pin Traces Provide Faraday Shielding Against the HIGH-SIDE SOURCE and MAIN-DRAIN Pin Traces. The Bypass Capacitor is Through-Hole Type so that the
Traces Connecting to the Pins can be Very Short.
DSB
(Noisy)
Ground
(Shield)
ENABLE High-Side
Pin
Drain (Quiet)
VAUX
(Quiet)
FEEDBACK
Pin
High-Side
Source (Noisy)
VDDH Parts
(Noisy)
Bootsrap Diode
Placed Near VDDH
PI-7022-052113
Figure 25. Layout Around ENABLE and FEEDBACK Pin. Use Quiet Traces as Faraday Shields from Noisy Traces, Especially if the Traces to the Optocouplers are Long.
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PI-7023-043013
TFS7701-7708
Transformer Secondary Pins
Drain Voltage (V)
2.8 µs
400
200
0
Main Converter Typical Waveforms
Main Transformer Primary Inductance and
Resonant Frequency
At zero load, check the resonant frequency visible in the Drain
voltage. This is the resonant frequency between the primary
inductance and the total capacitance reflected to the primary
(MOSFETs, transformer self-capacitance, output diode
capacitances). See Figure 27. A low resonant frequency can
prevent proper core reset at low-line and continuous-mode light
load, and can lead to core staircase saturation. See Figure 29.
Too much primary inductance causes the Drain rise time to be
very slow, eroding core reset volt-seconds. If the measured
resonant frequency is below 120 kHz (for 132 kHz operation), or
below 60 kHz (for 66 kHz operation), reduce transformer
primary inductance by increasing core gap. This initial test is a
rule of thumb. The final test is to check for complete core reset
at very low input voltage (just above the main UVLO threshold),
at a light load that is just above borderline continuous operation.
Reducing primary inductance below the value necessary for
complete core reset, will reduce efficiency.
400
High-Side
Main Drain High-Side
VCOSS
200
Turn-On
Edge
1.5
0.5
VBULK
Shelf
0
1
PI-7024-072513
600
Snubber
Clamp
Voltage
Turn-Off
Edge
Drain
Current
0
Figure 28. Typical Full Load Waveforms of the Main Drian. High-Side MOSFET
Source, and Drain Current.
600
Soft Corner in (HS) Voltage,
Flux goes Negative, no
Risk of Saturation
Sharp Corner (D) Voltage
at Turn-On
400
PI-7034-053113
Figure 26. Layout of Forward Transformer Secondary and Output Diodes. The
Diodes and Secondary Pins Should be Mounted Close Together, to
Minimize the Loop Area They Form.
Voltage (V)
PI-7016-052913
Current (A)
Output Diodes
Figure 27. Drain Voltage at Zero Load, to Measure Magnetizing Resonant
Frequency. In the Above Example, the Cursors Were Set to Measure
a Half-Cycle. The Resonant Frequency calculates as
fO = 1/(2.8 ms × 2) = 177 kHz.
Voltage (V)
High-Current
Loop Area
200
0
Flyback Standby Converter
The data sheet standby max power rating represents the
minimum practical continuous output power level that can be
obtained under the following assumed conditions:
1. The minimum DC input voltage is 115 V.
Drain (D) Clamp Diode
Large Reverse
Recovery Current
Current (A)
Full Load
Figure 16 shows the typical full-load waveform. Check highside VCOSS at turn-on. It is typically below 40% of the input
voltage. If it is greater, ensure that the low-side MOSFET clamp
diode is a standard-recovery (slow) rectifier (1N4007) and the
high-side MOSFET clamp diode (to ground) is an ultrafast type
(e.g., UF4005). Reducing the primary inductance by 20-30%
will also decrease this voltage, and in some cases may improve
full load efficiency.
0.4
0.2
0
2 µs/div
Figure 29.
Low-Line Operation (Just Above Main UV-OFF Threshold), with Load in
Borderline Continuous Mode. The Output will be out of Regulation.
This is the Condition to test for Complete Core Reset. The Soft Corner
in the (HS) Voltage at Turn-On Signifies Reversal of Magnetizing
Current and thus Complete Core Reset. The Sharp Corner in the
Drain (D) Waveform Signifies Hard-Reverse Recovery in the Drain
(Standard-Recovery) Clamp Rectifier. This is Acceptable for Transient
Conditions (e.g., Hold-Up Time)
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TFS7701-7708
2.
3.
4.
5.
6.
7.
Efficiency of 80% at full load, minimum nominal input.
Minimum data sheet value of I2f.
Transformer primary inductance tolerance of ±10%.
Reflected output voltage (VOR) of 100 V.
Voltage only output of 5 V with a Schottky diode.
Continuous conduction mode operation with transient
KP* value of 0.25.
8. Highest standby current limit selection.
9. Heat sink max temperature is 95 °C.
present turn remote to ON. Keep input voltage below UV start
threshold (typically 330 V). Slowly increase input voltage until
main converter starts. Check for proper waveforms and for
output regulation. Check for over-heating components,
especially the Drain clamp diode, and associated snubber
components. Slowly increase input voltage and load. Check
for over-heating components again.
*Below a value of 1, KP is the ratio of ripple to peak primary
current. A transient KP limit of ≥0.25 is recommended to
prevent reduced power capability due to premature termination
of switching cycles. Due to the initial current limit (IINIT ) being
exceeded at MOSFET turn-on.
Flyback
1. Maximum standby drain voltage – Verify that DSB voltage
does not exceed 675 V at highest input voltage and peak
(overload) output power. This 50 V margin to the 725 V
BVDSS specification gives margin for unit-to-unit variation.
2. Maximum DSB current – At maximum ambient temperature,
maximum input voltage and peak output (overload) power,
verify Standby Drain current waveforms for any signs of
transformer saturation and excessive leading edge current
spikes at start-up. Repeat under steady-state conditions
and verify that the leading edge current spike event is below
ILIMIT(N)(MIN) at the end of the tLEB(MIN). Under all conditions, the
maximum Standby Drain current should be below the
specified absolute maximum ratings.
3. Thermal check – With main converter off (and any system
fans are also off), at specified maximum output power,
minimum input voltage and maximum ambient temperature,
verify that the temperature specifications are not exceeded
for the HiperTFS-2, transformer, output diode, and output
capacitors.
Reducing No-Load Consumption
The BYPASS pin can be powered from the internal high-voltage
current source from the HIGH-SIDE DRAIN pin, but R16 (7.5 kΩ)
in Figure 30 will reduce no-load consumption by providing the
BYPASS pin current from a lower voltage and inhibiting the
internal high-voltage current source.
Audible Noise
Standard dip varnishing on the standby transformer will prevent
the possibility of audible noise in the standby converter.
Additionally, the peak core flux density should be kept below
3000 Gauss (300 mT). Vacuum impregnation of the transformer
is not recommended because it will increase standby no-load
losses due to the increased primary capacitance. Higher flux
densities are possible, however careful evaluation of the audible
noise performance should be made using production transformer
samples before approving the design. Ceramic capacitors that
use dielectrics such as Z5U, when used in clamp circuits with
high ripple voltage, may also generate audio noise. If this is the
case, try replacing them with a capacitor having a different
dielectric or construction, for example a film type.
Recommended First-Time Power-Up Procedure
Place a small, fast-blow low-capacity fuse between the bulk
capacitor and the HiperTFS-2 circuitry. Use a current-limited
bench power supply to power the HiperTFS-2 converter instead
of using the PFC or the AC mains. Be careful using a
programmable bench AC source in DC mode, because when
they are loaded with a large bulk capacitor and their output is
turned off, the output of the AC source can undershoot to a
negative voltage and damage the HiperTFS-2. If a remote-on
circuit is present, keep it OFF so that only the standby will run.
Place a voltage and current probe on the STANDBY DRAIN pin.
Raise the bulk capacitor voltage slowly until the standby turns
on. Check for proper waveforms (peak voltage, and check for
core saturation) and for output regulation. Check the VAUX
voltage. Check for over-heating components. Slowly increase
the load and the input voltage. Check for over-heating
components again.
Place voltage probes on DRAIN and HIGH-SIDE SOURCE pins.
Place current probe in DRAIN pin. If a remote-on circuit is
Quick Design Checklist
Main (Forward) Converter
Examine the voltage and current at 20% load and nominal input
voltage. Measure and check the following:
• Switching frequency
• Duty cycle
• Peak voltage
Repeat the measurements at full load. Be cautious of overheating the power supply and use a strong fan. Measure the
source voltage (HS) of the high-side MOSFET at turn-on for
each steady-state switch cycle (Figure 28). It should be < 40%
of the bulk voltage. Calculate and verify the KP from the current
waveform and verify with the spreadsheet. Also check the peak
current at peak load – do not dwell at peak load for more than
several seconds to prevent over-heating.
Check for any oscillation visible in the Drain current envelope.
Start-Up
Examine the start-up voltage and current. The peak start-up
current should be close to the ILIMIT of the device. Examine the
output voltage monotonicity. Check for the high-side misfiring
during start-up. If the bootstrap diode is omitted (66 kHz only),
the VDDH capacitor should be ≥4.7 mF to prevent misfiring.
Start-up should be acceptable with either the remote-on/off
switch, or by bringing up the HVDC supply with remote-on already
asserted. Check startup at maximum expected input voltage.
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TFS7701-7708
Brown-Out
At full load, reduce input voltage until the output just falls out of
regulation. Note the HVDC input voltage, measure the duty
cycle, and check the waveforms for complete core reset. Reduce
the input voltage further until the output just drops below
regulation (it is now in “LR mode”) while checking for complete
core reset further reduce input voltage to find the voltage at
which the converter shuts off (main UVLO)
Temperatures
Use a thermal camera and check device hotspot temperature,
and the temperatures of the snubber components, output
diodes, and magnetics.
Light Load
Examine the high-side MOSFET Source waveform at very light
load. As the load is reduced, the duty cycle will begin to
reduce, and at light enough load the high-side Source voltage
will not reach ground. Keep reducing the load and check for
misfiring in the high-side MOSFET. At 132 kHz operation, some
misfiring at very light load may occur, but it should occur at
such low duty cycles that any audio noise in the main transformer
will not be audible if the transformer is dip-varnished.
Loop Stability
As a first check, do a load step of 50% -> 100% load, and
check for oscillation or excessive ringing. Also check from
100% to peak load (be careful to avoid over-heating when
operating at peak load).
Check for cross-talk between the forward and flyback outputs.
When a load transient is applied to one output, the other output
should only show a very small perturbation, well below the
output ripple specification.
Use a gain-phase analyzer and check gain and phase margin at
full load. Also check the minimum phase at lower frequencies.
Check minimum phase at reduced load (just enough for
continuous mode operation).
24
Rev. B 04/15
www.power.com
TFS7701-7708
Design Example
+380 VDC
+380 VDC
C21
2.2 nF
250 VAC
R12
1.33 MΩ
1%
R13
1.33 MΩ
1%
C1
120 µF
450 V
U3B
PC357A
D13
1N4005
R16
7.5 kΩ
VR4
MMSZ5243BT1G
13 V
R20
4.7 kΩ
12 V Bias
R35
1.33 MΩ
1%
Q1
MMBT4401
R22
4.7 kΩ
R6
100 Ω
1/2 W
R1
2.2 Ω
1W
R18
1.33 MΩ
1%
R19
1.33 M
1%
HiperTFS-2
U6
TFS7703H 13 VDDH
R7
2.2 Ω
1/2 W
D4
1N4007
HD
16
CONTROL
D7
STPS30L60CT
R5
4.7 Ω
1/2 W
D3
1N4007
R36
1.33 MΩ
1%
L
9
R25
232 kΩ
1%
FB
C3 EF25
100 nF
50 V
4
D
6
FB
BP
11
R27
232 kΩ
1%
DSB
3
EN
R38
1 kΩ
U1A
PC357A
R9
15 kΩ
1%
C4
47 nF
50 V
R21
3.3 kΩ
C9
1 nF
100 V
7,8,9
C13
470 pF R26
100 V 200 Ω
D16
SB3100
5
Main
J5-1,2
R11
39 kΩ
C5
47 nF
50 V
C24
1500 µF
16 V
C10
1500 µF
16 V
C8
47 nF
50 V
U5
LM431
T2
EE16 9,10
3
+12 V
R15
1 kΩ
1W
HS
14
D8
UF4005
C18
1 nF
200 V
C22
3.3 nF
100 V
T1
C6
100 nF
50 V
1
10
R10
220 Ω
10,11,12
R37
2.2 Ω
J4-1
R24
3.92 kΩ
RTN
1%
J5-3,4
L2
2.2 µH
+12 V
Standby
J2-1
R28
100 Ω
SW1
Remote
ON/OFF
8
U1B
PC357A
R39
4.7 kΩ
EN
B-
L1
41 µH
R14
1 kΩ
R
7
R23
619 Ω
1%
D10
BAV19WS
C2
2.2 nF
1 kV
D6
STPS30L60CT
F1
3.5 A
VR3
P6KE150A
J3-1
5 G
C19
1 nF
200 V
U2A
PC357A
6 S
U2B
PC357A
J4-2
14 - 25 V
B-
C20
330 µF
35 V
J3-3
C17
1000 µF
16 V
D9
UF4005
C12
10 µF
16 V
R30
1 kΩ
D12
UF4003
R33
1 kΩ
U7
LM431
2
1
6,7
R34
19.1 kΩ
1%
C15
330 µF
25 V
R32
10 kΩ
C16
330 nF
50V
U3A
PC357A
R31
4.99 kΩ
1%
RTN
PI-6999-110513
J2-2
Figure 30. Design Example: 12 V / 15 A Main Output, 12 V, 0.83 A Standby.
High-Efficiency +12 V, 15 A Main Output and 12 V, 0.83 A
The circuit in Figure 30 is an example of a design using
HiperTFS-2 providing a 180 W +12 V forward main converter
and a 10 W, 12 V standby output from the flyback controller of
HiperTFS-2. The very high integration of two full converters
within a single package immediately shows the result of very
low external parts count for the entire design. Both the main
converter and the flyback section of HiperTFS-2 are designed to
provide very high-efficiency.
The main converter takes advantage of the ability to operate
above 50% duty factor which lowers RMS switch currents and
allows using lower voltage more efficient Schottky diodes on
the output. The flyback standby section uses Power Integrations’
TinySwitch technology which is often used in designs that
demand high-efficiency and low no-load input power consumption.
The design in Figure 30 is intended to work with a PFC boost
front end that nominally provides a 385 VDC input. The main
converter will regulate to full load between 300 VDC and
385 VDC. This voltage range guarantees greater than 20 ms
hold-up time with C1 (120 µF). R27 selects the 650 mA standby
MOSFET current limit, and R25 selects the 3.24 A main converter
current limit. The standby section is designed to operate
whether the boost PFC stage is on or off. The standby
therefore is designed to operate from 100 VDC to 385 VDC
which covers the normal universal input of 90 VAC to 265 VAC.
The start-up sequence is initiated with HiperTFS-2 charging the
BYPASS pin capacitor via the internal high-voltage current
source. Current limit selection then follows via FEEDBACK pin
and ENABLE pin resistors. The HiperTFS-2 then senses the
input voltage via the LINE-SENSE pin resistor series chain R12,
R13, R35. When the input voltage reaches 100 V VDC the
LINE-SENSE pin UV standby threshold is reached and the
standby converter turns on. After several milliseconds the
standby output will reach regulation and the primary VAUX 14-25 V
bias will be stable. R16 (7.5 kΩ) will provide bias current for the
operating current of the BYPASS pin to inhibit the internal
high-voltage current source to reduce zero-load consumption.
When the input bulk voltage reaches 336 VDC which is the UV
threshold for the main converter, the main converter will initiate
a turn-on sequence once the remote-on command from
secondary is activated. The remote-on switch (SW1) on the
secondary-side for this particular design allows the user to
manually activate that main converter by turning on the remoteon optocoupler. In actual PC designs the remote-on would be
controlled by a computer start-up command.
This optocoupler sources 6 mA (set by R23) into the BYPASS
pin of the HiperTFS-2 which is greater than the threshold
current to start the turn-on sequence for the main converter.
The main converter will first turn on the bottom switch to allow
the high-side drive to receive the bootstrap bias. After 60 ms
the main converter will start switching both high-side and
low-side main switches at 132 kHz (set by the value of C12
which is 10 mF) and the main output voltage will rise. Once the
regulator U5 becomes active, current will flow through the
optocoupler U1. The collector of U1 will sink current out of the
FEEDBACK pin to adjust for appropriate duty cycle to maintain
regulation. The normal operating sink current is between 1 mA
and 2 mA. D9 provides bootstrap charging for the high-side
driver supply pin VDDH. R14 limits the current from the
bootstrap.
25
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Rev. B 04/15
TFS7701-7708
During normal and brown-out operation the RESET pin senses
the turn-off clamp voltage via the resistor chain R36, R18, R19
and the internal controller determines the maximum safe duty
factor by comparing the RESET pin current with the LINESENSE pin current. This feature guarantees that saturation of
the transformer is completely avoided in all conditions including
brown-out and load transients.
The LINE-SENSE pin also has a UV low threshold which turns
off the main converter when the input voltage is below 212 V.
This design in particular is intended to operate with a forced air
cooling at full load to maintain a heat sink temperature below
95 ºC at full load at worst-case ambient temperature. The
standby uses auto-restart to protect the standby output from
output overload. The main output is current limited by the
selected internal primary current limit of the main switch path.
See PCB layout in Figure 31. HiperTFS-2 small signal pin
decoupling capacitors are placed close to the HiperTFS-2.
Small signal components and traces connected to the
HiperTFS-2 are kept away or shielded from traces with large
switching voltages. The optocouplers are placed to minimize
capacitive coupling between their signal traces, and traces with
high-voltage switching. Small signal ground return, and ground
traces that conduct large switching currents, are segregated.
Proper PCB clearance is observed between the high-voltage
pins and traces, and low-voltage traces and components.
The Y capacitor (C21) is placed so that it has short direct
connections to the bulk capacitor B+ pin (C1), and the
transformer secondary pins (T1). The output rectifiers (D6 and
D7) are placed close to the secondary pins. The main output
capacitor (C10), is placed close to the main output connector.
Jumpers are used to augment the PCB traces in the highcurrent secondary traces.
The primary bias diode (D12) and capacitor (C20), standby
output diode (D16) and capacitor (C17), are placed close to the
standby transformer (T2). C20 negative terminal is routed to the
bulk capacitor B- pin instead of to the HiperTFS-2 SOURCE or
GROUND pin. The 2nd standby output filter capacitor (C15) is
placed close to the standby output connector (J2).
PI-7030-052113
Figure 31. PCB Layout of Design Example Schematic in Figure 30.
26
Rev. B 04/15
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TFS7701-7708
Absolute Maximum Ratings(1,5)
DRAIN Voltage High-Side MOSFET .......................-0.3 V to 530 V
DRAIN Voltage Low-Side MOSFET..................... -0.3 V to 725 V
DRAIN Peak Current Low-Side
and High-Side: TFS7701...........................................2.6 (5.0)(4) A
TFS7702...........................................4.2 (8.0)(4) A
TFS7703...........................................5.0 (9.3)(4) A
TFS7704......................................... 5.7 (10.7)(4) A
TFS7705..........................................6.1 (11.4)(4) A
TFS7706..........................................6.4 (12.1)(4) A
TFS7707......................................... 7.2 (13.4)(4) A
TFS7708......................................... 8.3 (15.5)(4) A
DRAIN Voltage Standby MOSFET....................... -0.3 V to 725 V
DRAIN Peak Current Standby MOSFET................ 1.20 (2.25)(4) A
ENABLE (EN) Pin Voltage .......................................... -0.3 V to 9 V
ENABLE (EN) Pin Current .............................................. 100 mA
FEEDBACK (FB) Pin Voltage ................................... -0.3 V to 9 V
FEEDBACK (FB) Current ............................................... 100 mA
LINE-SENSE (L) Pin Voltage .........................................-0.3 V to 9 V
LINE-SENS (L) Pin Current ............................................ 100 mA
RESET (R) Pin Voltage ............................................ -0.3 V to 9 V
RESET (R) Pin Current ........................................................ 100 mA
BYPASS Supply (BP) Pin Voltage .............................. -0.3 V to 9 V
BYPASS Supply (BP) Pin Current ....................................... 100 mA
HIGHT-SIDE (VDDH) Supply Pin Voltage ........... -0.3 V to 13.4 V
HIGH-SIDE (VDDH) Supply Pin Current ........................... 50 mA
Storage Temperature .............................................-65 °C to 150 °C
Operating Junction Temperature(2).................... -40 °C to 150 °C
Lead Temperature(3) ..................................................................260 °C
Notes:
1. All voltages referenced to SOURCE, TJ = 25 °C.
2. Normally limited by internal circuitry.
3. 1/16 in. (1.59 mm) from case for 5 seconds.
4. The higher peak DRAIN current is allowed while the DRAIN
voltage is simultaneously less than 400 V.
5. Maximum ratings specified may be applied one at a time,
without causing permanent damage to the product.
Exposure to Absolute Rating conditions for extended periods
of time may affect product reliability.
Thermal Resistance
High-Side MOSFET (qJC) TFS7701-7706..........................5 °C/W
TFS7707-7708..........................4 °C/W
Parameter
Symbol
Low-Side MOSFET (qJC) .................................................1 °C/W
Notes:
1. All voltages referenced to SOURCE, TA = 25 °C.
Conditions
SOURCE = 0 V; TJ = 0 °C to 100 °C
(Unless Otherwise Specified)
Min
Typ
Max
62
70
fM1(MA)
66
4
132
8
250
fM2(MA)
250
Units
Control Functions
Switching Frequency
– PC Main
Frequency Jitter
Modulation Rate
fS1(MA)
fS2(MA)
TJ = 25 °C
TJ = 25 °C
Average
Peak-to-Peak Jitter
Average
Peak-to-Peak Jitter
124
140
kHz
Hz
Remote-ON Main
BYPASS Pin
Remote-ON Current
IBP(ON)
IBP(HYST)
66 kHz
BYPASS Pin
Remote-OFF
Current Hysteresis
IBP(HYST)
4.3
VEN = Open
132 kHz
5.3
TFS7701
TFS7702
TFS7703
TFS7704
TFS7705
TFS7706
TFS7707
TFS7708
TFS7701
TFS7702
TFS7703
TFS7704
TFS7705
TFS7706
TFS7707
3.8
3.7
3.6
3.6
3.5
3.4
3.4
3.4
3.6
3.5
3.3
3.2
3.1
2.9
2.8
TFS7708
2.7
6.3
mA
mA
27
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Rev. B 04/15
TFS7701-7708
Parameter
Remote-ON Main (cont.)
BYPASS Pin Latching
Shutdown Threshold
Main/Standby
Remote-ON Delay
Main/Standby
Remote-OFF Delay
Soft-Start
High-Side Start-Up
Charge Time
Soft-Start Period
Symbol
Conditions
SOURCE = 0 V; TJ = 0 °C to 100 °C
(Unless Otherwise Specified)
Min
Typ
Max
Units
IBP(SD)
17
mA
tR(ON)
2.5
ms
tR(OFF)
2.5
ms
tD(CH)
60
ms
tSS
See Note D
12
ms
PWM Gain
DCREG(MA)
-1800 mA < IFB < -1500 mA, IL = 60 mA,
IR = 160 mA
-70
%/mA
PWM Gain
Temperature Drift
TCDCREG
0.05
%/°C
-1.2
mA
-2.1
mA
12
kHz
2.9
V
FEEDBACK Pin
FEEDBACK Pin Feedback Onset current
IFB(ON)
FEEDBACK Pin Current
at Zero Duty Cycle
IFB(OFF)
FEEDBACK Pin
Internal Filter Pole
fP(FB)
FEEDBACK Pin Voltage
VFB
IL = 100 mA, IR = 170 mA
TJ = 25 °C
IFB = IFB(ON)
LINE-SENSE Pin (Line Voltage)
Line Undervoltage
Threshold – Standby
Line Undervoltage
Threshold – Main
IL(SB-UVON)
IL(SB-UVOFF)
IL(MA-UVON)
IL(MA-UVOFF)
Line Overvoltage
Threshold – Main
and Standby
IL(MA-OVOFF)
LINE-SENSE Pin
Voltage
VL
IL(MA-OVON)
TJ = 25 °C
TJ = 25 °C
TJ = 25 °C
TJ = 25 °C
LINE-SENSE Pin
IL(SC)
Short-Circuit
RESET Pin (Duty Limit/Main Only Remote-OFF)
Reset Overvoltage
Threshold
RESET Pin Voltage
RESET Pin
Short-Circuit Current
Duty Cycle –
Programmable Limit
IR(MA-OVON)
IR(MA-OVOFF)
Threshold
23.75
25
26.25
Threshold
9.0
10.5
12
Threshold
80
84
88
Threshold
47
54
58
Threshold
119
130
146
Threshold
135
144
164
IL = 79 mA
IL = 149 mA
0.75
1.0
1.27
1.45
1.55
1.85
VL = VBP
TJ = 25 °C
mA
mA
mA
V
mA
3900
Threshold
165
205
245
Threshold
175
215
255
mA
VR
IR = 155 mA
1.55
V
IR(SC)
VR = VBP
3750
mA
IL = 100 mA, IR = 110 mA
50.5
IL = 115 mA, IR = 170 mA
48.2
IL = 90 mA, IR = 170 mA
61
DCLIMIT(MA)
DCMAX(MA)
%
28
Rev. B 04/15
www.power.com
TFS7701-7708
Parameter
Symbol
Conditions
SOURCE = 0 V; TJ = 0 °C to 100 °C
(Unless Otherwise Specified)
Min
Typ
Max
Units
Current Limit Programming
FEEDBACK Pin
Current Limit
Detection Range #1
ILIM(1)(MA)
Start-up
See Note B
0-5
mA
FEEDBACK Pin
Current Limit
Detection Range #2
ILIM(2)(MA)
Start-up
See Note B
5-12
mA
ILIM(3)(MA)
Start-up
See Note B
12-24
mA
FEEDBACK Pin
Current Limit
Detection Range #3
Maximum Current Limit
Current Limit
ILIM(1)(MA)
ILIM(2)(MA)
ILIM(3)(MA)
ILIM(1)(MA)
ILIM(2)(MA)
ILIM(3)(MA)
ILIM(1)(MA)
ILIM(2)(MA)
ILIM(3)(MA)
ILIM(1)(MA)
ILIM(2)(MA)
ILIM(3)(MA)
ILIM(1)(MA)
ILIM(2)(MA)
ILIM(3)(MA)
ILIM(1)(MA)
ILIM(2)(MA)
ILIM(3)(MA)
ILIM(1)(MA)
ILIM(2)(MA)
ILIM(3)(MA)
ILIM(1)(MA)
ILIM(2)(MA)
ILIM(3)(MA)
TFS7701
TJ = 25 °C
FS = 66 kHz
TFS7702
TJ = 25 °C
FS = 66 kHz
TFS7703
TJ = 25 °C
FS = 66 kHz
TFS7704
TJ = 25 °C
FS = 66 kHz
TFS7705
TJ = 25 °C
FS = 66 kHz
TFS7706
TJ = 25 °C
FS = 66 kHz
TFS7707
TJ = 25 °C
FS = 66 kHz
TFS7708
TJ = 25 °C
FS = 66 kHz
di/dt = 175 mA/ms
di/dt = 224 mA/ms
di/dt = 249 mA/ms
di/dt = 267 mA/ms
di/dt = 343 mA/ms
di/dt = 381 mA/ms
di/dt = 333 mA/ms
di/dt = 428 mA/ms
di/dt = 475 mA/ms
di/dt = 370 mA/ms
di/dt = 475 mA/ms
di/dt = 528 mA/ms
di/dt = 409 mA/ms
di/dt = 525 mA/ms
di/dt = 584 mA/ms
di/dt = 448 mA/ms
di/dt = 576 mA/ms
di/dt = 639 mA/ms
di/dt = 482 mA/ms
di/dt = 619 mA/ms
di/dt = 688 mA/ms
di/dt = 509 mA/ms
di/dt = 655 mA/ms
di/dt = 727 mA/ms
1.58
2.40
2.99
3.33
3.68
4.03
4.33
4.58
1.19
1.53
1.70
1.82
2.34
2.60
2.26
2.91
3.24
2.52
3.24
3.60
2.78
3.58
3.98
3.05
3.92
4.36
3.28
4.22
4.69
3.47
4.46
4.96
1.82
2.78
3.46
3.85
A
4.26
4.66
5.01
5.30
Low-Side Main MOSFET
TFS7701
ID = 10% ILIM(3)(MA)
ON-State
Resistance
RDS(ON)
TFS7702
ID = 10% ILIM(3)(MA)
TFS7703
ID = 10% ILIM(3)(MA)
TFS7704
ID = 10% ILIM(3)(MA)
TJ = 25 °C
TJ = 100 °C
TJ = 25 °C
TJ = 100 °C
TJ = 25 °C
TJ = 100 °C
TJ = 25 °C
TJ = 100 °C
4.3
6.5
2.7
4.1
2.0
3.0
1.55
2.35
4.95
7.48
3.10
4.70
2.30
3.45
1.78
2.70
W
29
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Rev. B 04/15
TFS7701-7708
Parameter
Symbol
Conditions
SOURCE = 0 V; TJ = 0 °C to 100 °C
(Unless Otherwise Specified)
Min
Typ
Max
1.3
1.95
1.1
1.65
1.0
1.45
0.9
1.3
1.49
2.24
1.26
1.90
1.15
1.67
1.03
1.50
150
150
150
150
170
170
470
470
Units
Low-Side Main MOSFET (cont.)
TFS7705
ID = 10% ILIM(3)(MA)
ON-State
Resistance
RDS(ON)
TFS7706
ID = 10% ILIM(3)(MA)
TFS7707
ID = 10% ILIM(3)(MA)
TFS7708
ID = 10% ILIM(3)(MA)
OFF-State Drain
Leakage Current
Breakdown Voltage
IDSS(D)
BVDSS(D)
TFS7701
TFS7702
TFS7703
TFS7704
TFS7705
TFS7706
TFS7707
TFS7708
TJ = 25 °C
TJ = 100 °C
TJ = 25 °C
TJ = 100 °C
TJ = 25 °C
TJ = 100 °C
TJ = 25 °C
TJ = 100 °C
VL, VR = 0 V,
IBP = 6 mA,
VDS = 560 V,
TJ = 100 °C
VL, VR = 0 V, IBP = 6 mA, TJ = 25 °C
725
W
mA
V
Rise Time
tR(D)
100
ns
Fall Time
tF(D)
50
ns
High-Side Main MOSFET
TFS7701
(VHD - VHS ) = 1 V
TFS7702
(VHD - VHS ) = 1 V
TFS7703
(VHD - VHS ) = 1 V
ON-State Resistance
RDS(ON)(HD)
TFS7704
(VHD - VHS ) = 1 V
TFS7705
(VHD - VHS ) = 1 V
TFS7706
(VHD - VHS ) = 1 V
TFS7707
(VHD - VHS ) = 1 V
TFS7708
(VHD - VHS ) = 1 V
Effective Output
Capacitance
COSS(EFF)(HD)
TFS7701
TFS7702
TFS7703
TFS7704
TFS7705
TFS7706
TFS7707
TFS7708
TJ = 25 °C
TJ = 100 °C
TJ = 25 °C
TJ = 100 °C
TJ = 25 °C
TJ = 100 °C
TJ = 25 °C
TJ = 100 °C
TJ = 25 °C
TJ = 100 °C
TJ = 25 °C
TJ = 100 °C
TJ = 25 °C
TJ = 100 °C
TJ = 25 °C
TJ = 100 °C
TJ = 25 °C, VGS = 0 V
VDS = 0 V to 80% VDSS(HD)
1.90
2.40
1.90
2.40
1.20
1.50
1.20
1.50
0.90
W
1.10
0.90
1.10
0.71
0.90
0.71
0.90
55
55
82
82
110
110
165
165
pF
30
Rev. B 04/15
www.power.com
TFS7701-7708
Parameter
Symbol
Conditions
SOURCE = 0 V; TJ = 0 °C to 100 °C
(Unless Otherwise Specified)
Min
TJ = 25 °C
530
Typ
Max
Units
High-Side Main MOSFET (cont.)
Breakdown Voltage
BVDSS(HD)
TFS7701
TFS7702
TFS7703
TFS7704
TFS7705
TFS7706
TFS7707
TFS7708
530
60
60
60
60
80
80
110
110
OFF-State Drain
Current Leakage
IDSS(HD)
Turn-On Voltage
Rise Time
tR(HD)
30
ns
Turn-Off Voltage
Fall Time
tF(HD)
25
ns
VD = 424 V,
TJ = 100 °C
mA
High-Side Bias
Shunt Voltage
VDDH(SHUNT)
IDDH = 5 mA
See Note A
12.2
V
High-Side Undervoltage
ON-Threshold
VDDH(UVON)
See Note A
11.5
V
High-Side Undervoltage
OFF-Threshold
VDDH(UVOFF)
See Note A
10.3
V
High-Side Shunt
Hysteresis Voltage
VDDH(HYST)
See Note A
1.1
V
Standby MOSFET
ON-State
Resistance
RDS(ON)(DS)
IDSB = 10% ILIM(4)(DSB)
TJ = 25 °C
8.5
9.7
TJ = 100 °C
12.8
14.6
W
VBP = 6.2 V
OFF-State Drain
Leakage Current
VEN = 0 V
VDS = 560 V
TJ = 100 °C
IDSS1(DS)
IDSS2(DS)
Breakdown Voltage
BVDSS(DS)
DRAIN Supply Voltage
VDSB(START)
VBP = 6.2 V
200
mA
VDS = 375 V,
TJ = 50 °C
VEN = 0 V
VBP = 6.2 V, VEN = 0 V,
TJ = 25 °C
15
725
V
50
V
Standby Controller
Output Frequency
in Standard Mode
Maximum Duty Cycle
fS(SB)
DCMAX(DSB)
ENABLE Pin
Upper Turnoff
Threshold Current
IDIS
ENABLE Pin Voltage
VEN
TJ = 25 °C
Average
124
Peak-to-Peak Jitter
IL = 40 mA
IEN = -25 mA
132
140
8
kHz
66
69
72
%
-150
-105
-80
mA
2.7
3.6
4.5
V
31
www.power.com
Rev. B 04/15
TFS7701-7708
Parameter
Symbol
Conditions
SOURCE = 0 V; TJ = 0 °C to 100 °C
(Unless Otherwise Specified)
Min
Typ
Max
ICH1
VBP = 0 V,
TJ = 25 °C
-5
-4.0
-2
ICH2
VBP = 4 V,
TJ = 25 °C
-4
-2.1
0
VBP
VDS = 50 V
5.60
5.80
6.00
V
0.80
1.1
1.3
V
5.8
6.15
6.4
V
Units
Standby Controller (cont.)
BYPASS Pin
Charge Current
BYPASS Pin Voltage
mA
BYPASS Pin
Voltage Hysteresis
VBP(HYST)
BYPASS Pin
Shunt Voltage
VBP(SHUNT)
IBP = 2 mA
ENABLE Pin Current
Limit Selection Range #1
ILIM(1)(DSB)
Start-up
0-5
mA
ENABLE Pin Current
Limit Selection Range #2
ILIM(2)(DSB)
Start-up
5-12
mA
ENABLE Pin Current
Limit Selection Range #3
ILIM(3)(DSB)
Start-up
12-24
mA
ENABLE Pin Current
Limit Selection Range #4
ILIM(4)(DSB)
Start-up
24-48
mA
ILIM(1)(DSB)
IL = 20 mA, di/dt = 95 mA/ms, TJ = 25 °C
450
500
540
ILIM(2)(DSB)
IL = 20 mA, di/dt = 105 mA/ms, TJ = 25 °C
500
550
600
ILIM(3)(DSB)
IL = 20 mA, di/dt = 123 mA/ms, TJ = 25 °C
610
650
690
ILIM(4)(DSB)
IL = 20 mA, di/dt = 143 mA/ms, TJ = 25 °C
690
750
810
Δ ILIM
ILIM (IL = 100 mA) / ILIM (IL = 20 mA)
di/dt = 125 mA/ms
Power Coefficient
I2f
I2f = ILIM(3)(DSB)(TYP)× fS(SB)(OSC)(TYP)
TJ = 25 °C
0.9 × I2f
Initial Current Limit
IINIT
TJ = 25 °C
See Note D
0.75 ×
ILIM(MIN)
tLEB(D)
TJ = 25 °C
tLEB(DSB)
TJ = 25 °C
See Note D
tILD(D)
TJ = 25 °C
Standby Circuit Protection
Standby Current Limit
mA
84
%
General Circuit Protection
Leading Edge
Blanking Time (Main)
Leading Edge Blanking
Time (Standby)
Current Limit
Delay (Main)
170
I2f
1.12 × I2f
A2Hz
150
ns
215
ns
150
ns
32
Rev. B 04/15
www.power.com
TFS7701-7708
Parameter
Symbol
Conditions
SOURCE = 0 V; TJ = 0 °C to 100 °C
(Unless Otherwise Specified)
Min
Typ
Max
Units
General Circuit Protection (cont.)
Current Limit
Delay (Standby)
tILD(DSB)
TJ = 25 °C
150
ns
Thermal Shutdown
Temperature
TSD
See Note D
118
°C
Thermal Shutdown
Hysteresis
TSD(HYST)
55
°C
Auto-Restart ON-Time
at fOSC Standby
Auto-Restart Duty
Cycle Standby
tAR
TJ = 25 °C
64
ms
DCAR
TJ = 25 °C
2.2
%
IS1
EN Current > IDIS
(No MOSFETs Switching)
200
IS2
EN Open (Standby MOSFET
Switching at fOSC)
360
Supply Current
DRAIN Supply Current
550
800
mA
710
960
NOTES:
A. VDDH(SHUNT) minus VDDH(UV_ON) is equal to 250 mV minimum.
B. Level 1 RFB = open, Level 2 RFB = 511 kW, Level 3 RFB = 232 kW.
C. Level 1 REN = open, Level 2 REN = 511 kW, Level 3 REN = 232 kW, Level 4 REN = 107 kW.
D. Guaranteed by characterization. Not tested in production.
33
www.power.com
Rev. B 04/15
TFS7701-7708
1.0
0.9
-50 -25
0
25
50
75 100 125 150
1.1
PI-5999-060210
1.1
PI-5998-060210
MAIN DRAIN Pin Breakdown Voltage
(Normalized to 25 °C)
Note: Curves shown with fS1(MA) = 66 kHz and fS(SB) = 132 kHz.
STANDBY DRAIN Pin Breakdown Voltage
(Normalized to 25 °C)
Typical Performance Characteristics
1.0
0.9
-50 -25
0.8
0.6
0.4
0.2
0.0
-25
0
25
50
75
100 125
Junction Temperature (°C)
PI-7055-061713
MAIN DRAIN (D) Current Limit
(Normalized to 25 °C)
1.0
0.8
0.6
0.4
0.2
0.0
-50 -25
0
25
50
75
100 125
Junction Temperature (°C)
Figure 36. Main Drain (D) Current Limit vs. Temperature.
75 100 125 150
PI-7054-061713
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-50 -25
0
25
50
75
100 125
Junction Temperature (°C)
Figure 35. Standby Switching Frequency vs. Temperature.
Figure 34. Main Switching Frequency vs. Temperature.
1.2
50
1.2
PI-7056-061713
-50
STANDBY DRAIN (DSB) Current Limit
(Normalized to 25 °C)
1.0
25
Figure 33. Standby Supply. Breakdown vs. Temperature.
STANDBY DRAIN (DSB) Output Frequency
(Normalized to 25 °C)
PI-7053-061713
MAIN DRAIN (D) Output Frequency
(Normalized to 25 °C)
Figure 32. Main Supply. Breakdown Voltage vs. Temperature.
1.2
0
Junction Temperature (°C)
Junction Temperature (°C)
1.0
0.8
0.6
0.4
0.2
0.0
-50
-25
0
25
50
75
100 125
Junction Temperature (°C)
Figure 37. Standby Drain (DSB) Current Limit vs. Temperature.
34
Rev. B 04/15
www.power.com
TFS7701-7708
0.8
0.6
0.4
0.2
PI-7058-061313
1.0
4
LINE-SENSE Pin Voltage (V)
1.2
PI-7057-061713
LINE-SENSE Pin Standby Undervoltage
(Normalized to 25 °C)
Typical Performance Characteristics (cont.)
3
2
1
0
0.0
-50 -25
0
25
50
75
0
100 125
80 100 120 140 160
2
1
PI-7060-061313
FEEDBACK Pin Current (mA)
3
1
0
0
-1
-2
-3
-4
-5
0
50
100
150
200
250
0
RESET Pin Current (µA)
1
2
3
4
5
6
7
FEEDBACK Pin Voltage (V)
Figure 41. FEEDBACK (FB) Pin Current vs. Voltage.
100
50
0
-50
-100
25
PI-7062-061713
PI-7061-061313
150
BYPASS Pin Current (mA)
Figure 40. RESET (R) Pin Voltage vs. Current.
ENABLE Pin Current (µA)
60
Figure 39. LINE-SENSE (L) Pin Voltage vs. Current.
PI-7059-061313
RESET Pin Voltage (V)
4
40
LINE-SENSE Pin Current (µA)
Junction Temperature (°C)
Figure 38. Standby Supply. Undervoltage Threshold vs.
Junction Temperature.
5
20
20
15
10
5
0
-150
0
1
2
3
4
5
6
ENABLE Pin Voltage (V)
Figure 42. ENABLE (EN) Pin Current vs. Voltage.
7
0
2
4
6
8
BYPASS Pin Voltage (V)
Figure 43. BYPASS (BP) Pin Current vs. Voltage.
35
www.power.com
Rev. B 04/15
TFS7701-7708
Typical Performance Characteristics (cont.)
30
20
10
PI-7064-061713
40
1.2
Normalized Duty Cycle
PI-7063-061713
VDDH Current (mA)
50
1.0
0.8
0.6
0.4
0.2
0.0
0
0
4
8
12
-50 -25
16
50
75
100 125
0.8
0.6
0.4
0.2
PI-7066-061713
1.0
1.25
DRAIN Current (A)
PI-7065-061713
1.2
Normalized Duty Cycle
25
Figure 45. Duty Cycle vs. Temperature (IL = 100 mA, IR = 110 mA).
Figure 44. VDDH Pin Current vs. Voltage.
1
0.75
0.5
TCASE = 25 °C
TCASE = 100 °C
0.25
0
0.0
-50 -25
0
25
50
75
0
100 125
Junction Temperature (°C)
3
2
1
TCASE = 25 °C
TCASE = 100 °C
Scaling Factors:
TFS7701 0.34
TFS7702 0.56
TFS7703 0.76
TFS7704 0.96
TFS7705 1.16
TFS7706 1.37
TFS7707 1.57
TFS7708 1.77
0
0
2
4
6
8 10 12 14 16 18 20
DRAIN Voltage (V)
Figure 48. Drain Supply. Output Characteristics.
6
8 10 12 14 16 18 20
1000
PI-7068-061413
4
4
Figure 47. Standby Supply. Output Characteristics.
STANDBY DRAIN (DSB)
Capacitance (pF)
PI-7067-061713
5
2
STANDBY DRAIN Voltage (V)
Figure 46. Duty Cycle vs. Temperature (IL = 115 mA, IR = 170 mA)
DRAIN Current (A)
0
Junction Temperature (°C)
VDDH Voltage (V)
100
10
0
0
100
200
300
400
500
600
STANDBY DRAIN (DBS) Pin Voltage (V)
Figure 49. Standby Drain Capacitance vs. Drain Voltage.
36
Rev. B 04/15
www.power.com
TFS7701-7708
Typical Performance Characteristics (cont.)
100
50
25
0
100
200
300
400
500
0
600
0
Figure 50. Main Drain Capacitance vs. Drain Voltage.
20
PI-7071-061413
200
100
400
TJ = 25 °C
TJ = 100 °C
5
100 200 300 400 500 600 700
0
1
MAIN DRAIN (D) Pin Voltage (V)
200
300
400
HD-HS Voltage (V)
Figure 54. High-Side MOSFET (HD-HS) Drain Current vs.
Drain Voltage.
4
5
6
7
PI-5972-051210
1.1
Breakdown Voltage
(Normalized to 25 °C)
COSS (pF)
Scaling Factors:
TFS7701 0.17
TFS7702 0.17
TFS7703 0.25
TFS7704 0.25
TFS7705 0.33
TFS7706 0.33
TFS7708 0.42
TFS7709 0.42
100
3
Figure 53. High-Side MOSFET (HD-HS) Drain Current vs.
Drain Voltage.
PI-7073-061713
1000
2
HD-HS Voltage (V)
Figure 52. Main Drain Switching Power vs. Drain Voltage.
0
600
Scaling Factors:
TFS7701 0.17
TFS7702 0.17
TFS7703 0.25
TFS7704 0.25
TFS7705 0.33
TFS7706 0.33
TFS7708 0.42
TFS7709 0.42
0
0
500
100 °C
25 °C
10
0
100
300
15
HD-HS Current (A)
Scaling Factors:
TFS7701 0.34
TFS7702 0.56
TFS7703 0.76
TFS7704 0.96
TFS7705 1.16
TFS7706 1.37
TFS7708 1.57
TFS7709 1.77
300
200
Figure 51. Standby Drain Switching Power vs. Drain Voltage.
500
400
100
STANDBY DRAIN (DSB) Pin Voltage (V)
PI-7702-061713
10
MAIN DRAIN (D) Pin Voltage (V)
Power (mW)
PI-5946-061713
75
Power (mW)
Scaling Factors:
TFS7701 0.34
TFS7702 0.56
TFS7703 0.76
TFS7704 0.96
TFS7705 1.16
TFS7706 1.37
TFS7707 1.57
TFS7708 1.77
1000
100
PI-7069-061413
MAIN DRAIN (D) Capacitance (pF)
10000
1.0
0.9
-50 -25
0
25
50
75 100 125 150
Temperature (°C)
Figure 55. High-Side MOSFET Breakdown Voltage vs. Temperature.
37
www.power.com
Rev. B 04/15
TFS7701-7708
2
Scaling Factors:
TFS7701 0.17
TFS7702 0.17
TFS7703 0.25
TFS7704 0.25
TFS7705 0.33
TFS7706 0.33
TFS7708 0.42
TFS7709 0.42
1.5
Power (mW)
PI-7074-061813
Typical Performance Characteristics (cont.)
1
0.5
0
0
100
200
300
400
HD-HS Voltage (V)
Figure 56. High-Side MOSFET (HD-HS) Power vs. Drain Voltage.
38
Rev. B 04/15
www.power.com
TFS7701-7708
THERMAL
GREASE
TFS2
CLIP
SELF TAP
SCREW
Figure 57. Heat Sink Assembly – using Thermally Conductive Silicone Grease.
39
www.power.com
Rev. B 04/15
Rev. B 04/15
1
5
6
Pin 1
13 14
8
9
10
16
2
B
0.035 (0.89) Ref.
0.012 (0.30) Typ.
0.101 (2.57) Ref.
0.167 (4.24) Ref.
0.235 (5.96) Ref.
0.140 (3.56)
0.120 (3.05)
Detail A
0.118 (3.00)
0.047 (1.19)
0.016 (0.41)
Ref.
0.290 (7.37)
Ref.
C
0.027 (0.70)
0.023 (0.58)
0.020 (0.50)
13
11
8
7
6
0.114
(2.91)
5
1
0.076
(1.94)
3
0.152
(3.88)
MOUNTING HOLE PATTERN (N.T.S)
All dimensions in inches (mm)
0.076 0.076
(1.94) (1.94)
10
9
3
7. Tied to SOURCE (Pin 6).
9. 10. Tied to HD (Pin 16).
8. Tied to HS (Pin 14).
6.
5. Controlling dimensions in inches (mm).
4. Does not include interlead flash or protrusions.
3. Dimensions noted are inclusive of plating thickness.
PI-7080-070813
2. Dimensions noted are determined at the outermost extremes of the plastic body exclusive of
mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between
the top and bottom of the plastic body. Maximum mold protrusion is 0.007 [0.18] per side.
4
0.207 (5.26)
0.187 (4.75)
0.201 (5.11)
Ref.
0.024 (0.61) 13×
0.019 (0.48)
0.010 M 0.25 M C A B
0.381 (9.68)
Ref.
BACK VIEW
0.114 0.114
(2.91) (2.91)
16
14
0.114
(2.91)
0.012 (0.30) Ref.
0.076 (1.93)
0.519 (13.18)
Ref.
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
Detail A (Scale = 9×)
SIDE VIEW
0.081 (2.06)
0.077 (1.96)
0.016 (0.41) 13×
0.011 (0.28)
0.020 M 0.51 M C
3
0.021 (0.53)
0.019 (0.48)
0.048 (1.22)
0.046 (1.17)
10° Ref.
All Around
0.056 (1.42) Ref.
0.325 (8.25)
0.320 (8.13)
TOP END VIEW B-B
Location of exposed metal tie-bars
7
END VIEW
0.010 (0.25) Typ.
0.041 (1.04) Ref.
0.020 (0.51) Ref.
6
10 11
FRONT VIEW
9
0.628 (15.95) Ref.
0.060 (1.52) Ref.
7 8
Pin 1 I.D.
0.653 (16.59)
0.647 (16.43)
0.038 (0.97)
3
0.019 (0.48) Ref.
A
2
eSIP-16F (H Package)
TFS7701-7708
40
www.power.com
TFS7701-7708
Part Ordering Information
Part Number
Option
Quantity
TFS7701H
Tube
30
TFS7702H
Tube
30
TFS7703H
Tube
30
TFS7704H
Tube
30
TFS7705H
Tube
30
TFS7706H
Tube
30
TFS7707H
Tube
30
TFS7708H
Tube
30
Part Marking Information
• HiperTFS-2 Product Family
• TFS Series Number
• Package Identifier
TFS 7705 H
H
Plastic eSIP-16F. Halogen Free and RoHS Compliant
41
www.power.com
Rev. B 04/15
Revision
Notes
Date
A
Code A.
11/13
B
Moved location of “output short-circuit protection (SCP)” bullet point on page 3.
04/15
For the latest updates, visit our website: www.power.com
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power
Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES
NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered
by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations.
A complete list of Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under
certain patent rights as set forth at http://www.power.com/ip.htm.
Life Support Policy
POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:
1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii)
whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant
injury or death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or effectiveness.
The PI logo, TOPSwitch, TinySwitch, LinkSwitch, LYTSwitch, InnoSwitch, DPA-Switch, PeakSwitch, CAPZero, SENZero, LinkZero,
HiperPFS, HiperTFS, HiperLCS, Qspeed, EcoSmart, Clampless, E-Shield, Filterfuse, FluxLink, StakFET, PI Expert and PI FACTS are
trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©2014, Power Integrations, Inc.
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