TOP100-4
TOPSwitch
Three-terminal Off-line PWM Switch
AC
IN
DRAIN
SOURCE
CONTROL
TOPSwitch
TOPSwitch SELECTION GUIDE
ORDER
PART
NUMBER
OUTPUT POWER RANGE
FLYBACK
100/110 V
VAC
48 V
DC
PFC/
BOOST
100/110
VAC
N*
N*
N*
N*
N*
July 2009
TOP100-4
VC
CONTROL
0
ZC
SHUTDOWN/
AUTO-RESTART
SHUNT REGULATOR/
ERROR AMPLIFIER
+
+
1
5.7 V
5.7 V
4.7 V
DRAIN
INTERNAL
SUPPLY
÷8
-
POWER-UP
RESET
EXTERNALLY
TRIGGERED
SHUTDOWN
+
R
Q
S
Q
-
THERMAL
SHUTDOWN
IFB
VI
LIMIT
CONTROLLED
TURN-ON
GATE
DRIVER
OSCILLATOR
DMAX
CLOCK
SAW
-
S
Q
+
R
Q
PWM
COMPARATOR
LEADING
EDGE
BLANKING
MINIMUM
ON-TIME
DELAY
RE
SOURCE
PI-1746-011796
Figure 2. Functional Block Diagram.
Pin Functional Description
DRAIN Pin:
Output MOSFET drain connection. Provides internal bias
current during start-up operation via an internal switched highvoltage current source. Internal current sense point.
CONTROL Pin:
Error amplifier and feedback current input pin for duty cycle
control. Internal shunt regulator connection to provide internal
bias current during normal operation. Trigger input for latching
shutdown. It is also used as the supply bypass and auto-restart/
compensation capacitor connection point.
SOURCE Pin:
Output MOSFET source connection. Primary-side circuit
common, power return, and reference point.
2
F
7 /09
DRAIN
SOURCE (TAB)
CONTROL
TO-220/3 (YO3A)
PI-1065A-110194
Figure 3. Pin Configuration.
TOP100-4
TOPSwitch Family Functional Description
During normal operation, the internal
output MOSFET duty cycle linearly
decreases with increasing CONTROL
pin current as shown in Figure 4. To
implement all the required control, bias,
and protection functions, the DRAIN
and CONTROL pins each perform
several functions as described below.
Refer to Figure 2 for a block diagram
and Figure 6 for timing and voltage
waveforms of the TOPSwitch integrated
circuit.
Control Voltage Supply
CONTROL pin voltage VC is the supply
or bias voltage for the controller and
driver circuitry. An external bypass
capacitor closely connected between the
CONTROL and SOURCE pins is
required to supply the gate drive current.
The total amount of capacitance
connected to this pin (CT) also sets the
auto-restart timing as well as control
loop compensation. VC is regulated in
either of two modes of operation.
Hysteretic regulation is used for initial
start-up and overload operation. Shunt
regulation is used to separate the duty
cycle error signal from the control circuit
supply current. During start-up, VC
current is supplied from a high-voltage
switched current source connected
internally between the DRAIN and
CONTROL pins. The current source
provides sufficient current to supply the
control circuitry as well as charge the
total external capacitance (CT).
Auto-restart
IB
DMAX
Slope = PWM Gain
-16%/mA
Duty Cycle (%)
TOPSwitch is a self biased and protected
linear control current-to-duty cycle
converter with an open drain output.
High efficiency is achieved through the
use of CMOS and integration of the
maximum number of functions possible.
CMOS significantly reduces bias
currents as compared to bipolar or
discrete solutions. Integration eliminates
external power resistors used for current
sensing and/or supplying initial start-up
bias current.
DMIN
ICD1 2.5
6.5
45
IC (mA)
PI-1691-112895
Figure 4. Relationship of Duty Cycle to CONTROL Pin Current.
VC
5.7 V
4.7 V
IC
Charging CT
0
DRAIN
VIN
Off
0
Switching
(a)
VC
5.7 V
4.7 V
IC
Charging CT
8 Cycles
0
DRAIN
ICD2
Discharging CT
ICD1
Discharging CT
VIN
95%
Off
5%
Off
Off
0
Switching
Switching
(b)
CT is the total external capacitance
connected to the CONTROL pin
PI-1124A-060694
Figure 5. Start-up Waveforms for (a) Normal Operation and (b) Auto-restart.
F
7/ 09
3
TOP100-4
TOPSwitch Family Functional Description (cont.)
The first time VC reaches the upper
threshold, the high-voltage current
source is turned off and the PWM
modulator and output transistor are
activated, as shown in Figure 5(a).
During normal operation (when the
output voltage is regulated) feedback
control current supplies the VC supply
current. The shunt regulator keeps VC at
typically 5.7 V by shunting CONTROL
pin feedback current exceeding the
required DC supply current through the
PWM error signal sense resistor RE. The
low dynamic impedance of this pin (ZC)
sets the gain of the error amplifier when
used in a primary feedback
configuration. The dynamic impedance
of the CONTROL pin together with the
external resistance and capacitance
determines the control loop
compensation of the power system.
If the CONTROL pin external
capacitance (CT) should discharge to the
lower threshold, then the output
MOSFET is turned off and the control
circuit is placed in a low-current standby
mode. The high-voltage current source
is turned on and charges the external
capacitance again. Charging current is
shown with a negative polarity and
discharging current is shown with a
positive polarity in Figure 6. The
hysteretic auto-restart comparator keeps
VC within a window of typically 4.7 to
5.7 V by turning the high-voltage current
source on and off as shown in Figure
5(b). The auto-restart circuit has a divideby-8 counter which prevents the output
MOSFET from turning on again until
eight discharge-charge cycles have
elapsed. The counter effectively limits
TOPSwitch power dissipation by
reducing the auto-restart duty cycle to
typically 5%. Auto-restart continues to
cycle until output voltage regulation is
again achieved.
4
F
7/ 09
Bandgap Reference
All critical TOPSwitch internal voltages
are derived from a temperaturecompensated bandgap reference. This
reference is also used to generate a
temperature-compensated current source
which is trimmed to accurately set the
oscillator frequency and MOSFET gate
drive current.
Oscillator
The internal oscillator linearly charges
and discharges the internal capacitance
between two voltage levels to create a
sawtooth waveform for the pulse width
modulator. The oscillator sets the pulse
width modulator/current limit latch at
the beginning of each cycle. The nominal
frequency of 100 kHz was chosen to
minimize EMI and maximize efficiency
in power supply applications. Trimming
of the current reference improves
oscillator frequency accuracy.
Pulse Width Modulator
The pulse width modulator implements
a voltage-mode control loop by driving
the output MOSFET with a duty cycle
inversely proportional to the current
flowing into the CONTROL pin. The
error signal across RE is filtered by an
RC network with a typical corner
frequency of 7 kHz to reduce the effect
of switching noise. The filtered error
signal is compared with the internal
oscillator sawtooth waveform to generate
the duty cycle waveform. As the control
current increases, the duty cycle
decreases. A clock signal from the
oscillator sets a latch which turns on the
output MOSFET. The pulse width
modulator resets the latch, turning off
the output MOSFET. The maximum
duty cycle is set by the symmetry of the
internal oscillator. The modulator has a
minimum ON-time to keep the current
consumption of the TOPSwitch
independent of the error signal. Note
that a minimum current must be driven
into the CONTROL pin before the duty
cycle begins to change.
Gate Driver
The gate driver is designed to turn the
output MOSFET on at a controlled rate
to minimize common-mode EMI. The
gate drive current is trimmed for
improved accuracy.
Error Amplifier
The shunt regulator can also perform the
function of an error amplifier in primary
feedback applications. The shunt
regulator voltage is accurately derived
from the temperature compensated
bandgap reference. The gain of the error
amplifier is set by the CONTROL pin
dynamic impedance. The CONTROL
pin clamps external circuit signals to the
VC voltage level. The CONTROL pin
current in excess of the supply current is
separated by the shunt regulator and
flows through RE as the error signal.
Cycle-By-Cycle Current Limit
The cycle by cycle peak drain current
limit circuit uses the output MOSFET
ON-resistance as a sense resistor. A
current limit comparator compares the
output MOSFET ON-state drain-source
voltage, VDS(ON), with a threshold voltage.
High drain current causes VDS(ON) to
exceed the threshold voltage and turns
the output MOSFET off until the start of
the next clock cycle. The current limit
comparator threshold voltage is
temperature compensated to minimize
variation of the effective peak current
limit due to temperature related changes
in output MOSFET RDS(ON).
The leading edge blanking circuit inhibits
the current limit comparator for a short
time after the output MOSFET is turned
on. The leading edge blanking time has
been set so that current spikes caused by
primary-side capacitances and
secondary-side rectifier reverse recovery
time will not cause premature
termination of the switching pulse.
TOP100-4
VIN
DRAIN
VIN
0
VOUT
IOUT
0
0
1
VC
1
2
•••
8
1
•••
VC(reset)
0
45 mA
1
IC
8
2
0
2
8
1
•••
1
2
8
1
•••
2
3
4
1
PI-1119-110194
Figure 6. Typical Waveforms for (1) Normal Operation, (2) Auto-restart, (3) Latching Shutdown, and (4) Power Down Reset.
Shutdown/Auto-restart
To minimize TOPSwitch power
dissipation, the shutdown/auto-restart
circuit turns the power supply on and off
at a duty cycle of typically 5% if an out
of regulation condition persists. Loss of
regulation interrupts the external current
into the CONTROL pin. VC regulation
changes from shunt mode to the
hysteretic auto-restart mode described
above. When the fault condition is
removed, the power supply output
becomes regulated, VC regulation returns
to shunt mode, and normal operation of
the power supply resumes.
Latching Shutdown
The output overvoltage protection latch
is activated by a high-current pulse into
the CONTROL pin. When set, the latch
turns off the TOPSwitch output.
Activating the power-up reset circuit by
removing and restoring input power, or
momentarily pulling the CONTROL pin
below the power-up reset threshold resets
the latch and allows TOPSwitch to
resume normal power supply operation.
VC is regulated in hysteretic mode when
the power supply is latched off.
Overtemperature Protection
Temperature protection is provided by a
precision analog circuit that turns the
output MOSFET off when the junction
temperature exceeds the thermal
shutdown temperature (typically 145°C).
Activating the power-up reset circuit by
removing and restoring input power or
momentarily pulling the CONTROL pin
below the power-up reset threshold resets
the latch and allows TOPSwitch to
resume normal power supply operation.
VC is regulated in hysteretic mode when
the power supply is latched off.
High-voltage Bias Current Source
This current source biases TOPSwitch
from the DRAIN pin and charges the
CONTROL pin external capacitance
(C T ) during start-up or hysteretic
operation. Hysteretic operation occurs
during auto-restart and latched
shutdown. The current source is switched
on and off with an effective duty cycle of
approximately 35%. This duty cycle is
determined by the ratio of CONTROL
pin charge (IC) and discharge currents
(ICD1 and ICD2). This current source is
turned off during normal operation when
the output MOSFET is switching.
F
7/ 09
5
TOP100-4
General Circuit Operation
Primary Feedback Regulation
The circuit shown in Figure 7 is a simple
5 V, 5 W bias supply using the TOP100.
This flyback power supply employs
primary-side regulation from a
transformer bias winding. This approach
is best for low-cost applications requiring
isolation and operation within a narrow
range of load variation. Line and load
regulation of ±5% or better can be
achieved from 10% to 100% of rated
load.
Voltage feedback is obtained from the
transformer (T1) bias winding, which
eliminates the need for optocoupler and
secondary-referenced error amplifier.
High-voltage DC is applied to the
primary winding of T1. The other side
of the transformer primary is driven by
the integrated high-voltage MOSFET
transistor within the TOP100 (U1). The
circuit operates at a switching frequency
of 100 kHz, set by the internal oscillator
of the TOP100. The clamp circuit
implemented by VR1 and D1 limits the
leading-edge voltage spike caused by
transformer leakage inductance to a safe
value. The 5 V power secondary winding
is rectified and filtered by D2, C2, C3,
and L1 to create the 5 V output voltage.
The output of the T1 bias winding is
rectified and filtered by D3, R1, and C5.
The voltage across C5 is regulated by
U1, and is determined by the 5.7 V
internal shunt regulator at the
CONTROL pin of U1. When the
rectified bias voltage on C5 begins to
exceed the shunt regulator voltage,
current will flow into the control pin.
Increasing control pin current decreases
the duty cycle until a stable operating
point is reached. The output voltage is
proportional to the bias voltage by the
turns ratio of the output to bias windings.
C5 is used to bypass the CONTROL pin.
C5 also provides loop compensation for
the power supply by shunting AC
currents around the CONTROL pin
dynamic impedance, and also determines
the auto-restart frequency during startup and auto-restart conditions. See DN8 for more information regarding bias
supplies.
D2
1N5822
L1
(Bead)
5V
VR1
P6KE91
C2
330 µF
25 V
C3
150 µF
25 V
RTN
D1
UF4004
D3
1N4148
DC
INPUT
C5
47 µF
DRAIN
SOURCE
T1
R1
22 Ω
CIRCUIT PERFORMANCE:
Load Regulation - ±4%
(10% to 100%)
Line Regulation - ±1.5%
95 to 185 V DC
Ripple Voltage ±25 mV
CONTROL
U1
TOP100YAI
PI-1767-020296
Figure 7. Schematic Diagram of a Minimum Parts Count 5 V, 5 W Bias Supply Utilizing the TOP100.
6
F
7 /09
TOP100-4
D2
UG8BT
L1
3.3 µH
7.5 V
R1
39 Ω
U2
NEC2501
D1
UF4004
L2
20 mH
C1
27 µF
200 V
C6
0.1 µF
F1
3.15 A
L
N
DRAIN
C3
120 µF
25 V
C2
680 µF
25 V
VR1
P6KE91
BR1
200 V
VR2
1N5234B
6.2 V
RTN
D3
1N4148
C5
47µF
10 V
C7
1 nF
Y1
T1
SOURCE
CONTROL
U1
TOP101YAI
R2
68 Ω
CIRCUIT PERFORMANCE:
Line Regulation - ±0.5%
(85-132 VAC)
Load Regulation - ±1%
(10-100%)
Ripple Voltage ±50 mV
Meets CISPR-22 Class B
C4
0.1 µF
J1
PI-1692-112895
Figure 8. Schematic Diagram of a 15 W 100/110 VAC Input Power Supply Utilizing the TOP101 and Simple Optocoupler Feedback.
Simple Optocoupler Feedback
The circuit shown in Figure 8 is a 7.5 V,
15 W secondary regulated flyback power
supply using the TOP101 that will
operate from 85 to 132 VAC input
voltage. Improved output voltage
accuracy and regulation over the circuit
of Figure 7 is achieved by using an
optocoupler and secondary referenced
Zener diode. The general operation of
the power stage of this circuit is the same
as that described for Figure 7.
The input voltage is rectified and filtered
by BR1 and C1. L2, C6 and C7 reduce
conducted emission currents. The bias
winding is rectified and filtered by D3
and C4 to create a typical 11 V bias
voltage. Zener diode (VR2) voltage
together with the forward voltage of the
LED in the optocoupler U2 determine
the output voltage. R1, the optocoupler
current transfer ratio, and the TOPSwitch
control current to duty cycle transfer
function set the DC control loop gain.
C5 together with the control pin dynamic
impedance and capacitor ESR establish
a control loop pole-zero pair. C5 also
determines the auto-restart frequency
and filters internal gate drive switching
currents. R2 and VR2 provide minimum
current loading when output current is
low. See DN-11 for more information
regarding low-cost, 15 W power
supplies.
Accurate Optocoupler Feedback
The circuit shown in Figure 9 is a highly
accurate, 15 V, 30 W secondaryregulated flyback power supply that will
operate from 85 to 132 VAC input
voltage. A TL431 shunt regulator
directly senses and accurately regulates
the output voltage. The effective output
voltage can be fine tuned by adjusting
the resistor divider formed by R4 and
R5. Other output voltages are possible
by adjusting the transformer turns ratios
as well as the divider ratio.
The general operation of the input and
power stages of this circuit are the same
as that described for Figures 7 and 8. R3
and C5 tailor frequency response. The
TL431 (U3) regulates the output voltage
by controlling optocoupler LED current
(and TOPSwitch duty cycle) to maintain
an average voltage of 2.5 V at the TL431
input pin. Divider R4 and R5 determine
the actual output voltage. C9 rolls off
the high frequency gain of the TL431 for
stable operation. R1 limits optocoupler
LED current and determines high
frequency loop gain. For more
information, refer to application note
AN-14.
F
7/ 09
7
TOP100-4
D2
MUR610CT
L1
3.3 µH
15 V
VR1
P6KE91
C3
120 µF
25 V
RTN
C1
47 µF
200 V
L2
33 mH
R2
200 Ω
1/2 W
C2
1000 µF
35 V
D1
BYV26B
D3
1N4148
U2
NEC2501
BR1
200 V
C4
0.1 µF
CIRCUIT PERFORMANCE:
Line Regulation - ±0.2%
(85-132 VAC)
Load Regulation - ±0.2%
(10-100%)
Ripple Voltage ±150 mV
Meets CISPR-22 Class B
C6
0.1 µF
F1
3.15 A
R1
510 Ω
T1
R4
49.9 kΩ
C9
0.1 µF
C5
R3
47 µF 6.2 Ω
U3
TL431
DRAIN
L
R5
10 kΩ
SOURCE
CONTROL
N
C7
1 nF
Y1
U1
TOP102YAI
J1
PI-1693-112895
Figure 9. Schematic Diagram of a 30 W 100/110 VAC Input Power Supply Utilizing the TOP102 and Accurate Optocoupler Feedback.
L1
380 µH
PFC OUT
D1
MUR440
VR1
120 V
EMI
FILTER
AC
IN
R1
130 kΩ
BR1
200 V
VR2
120 V
C1
220 nF
200 V
C4
100 µF
DRAIN
SOURCE
TYPICAL PERFORMANCE:
Power Factor = 0.99
THD =5%
D2
1N4936
C2
4.7 µF
R2
200 Ω
R3
3 kΩ
CONTROL
U1
TOP103YAI
R10
6.8 kΩ
C3
220 µF
RTN
PI-1437-042595
Figure 10. Schematic Diagram of a 60 W 110 VAC Input Boost Power Factor Correction Circuit Utilizing the TOP103.
8
F
7/ 09
TOP100-4
General Circuit Operation (cont.)
Boost PFC Pre-regulator
TOPSwitch can also be used as a fixed
frequency, discontinuous mode boost
pre-regulator to improve Power Factor
and reduce Total Harmonic Distortion
(THD) for applications such as power
supplies and electronic ballasts. The
circuit shown in Figure 10 operates from
110 VAC and delivers 60 W at 265 VDC
with typical Power Factor over 0.99 and
THD of 5%. Bridge Rectifier BR1 full
wave rectifies the AC input voltage. L1,
D1, C4, and TOPSwitch make up the
boost power stage. D2 prevents reverse
current through the TOPSwitch body
diode due to ringing voltages generated
by the boost inductance and parasitic
capacitance. R1 generates a precompensation current proportional to
the instantaneous rectified AC input
voltage which directly varies the duty
cycle. C2 filters high frequency
switching currents while having no
filtering effect on the line frequency precompensation current. R2 decouples
the pre-compensation current from the
large filter capacitor C3 to prevent an
averaging effect which would increase
total harmonic distortion. C1 filters
high frequency noise currents which
could cause errors in the precompensation current.
When power is first applied, C3 charges
to typically 5.7 volts before TOPSwitch
starts. C3 then provides TOPSwitch
bias current until the output voltage
becomes regulated. When the output
voltage becomes regulated, series
connected Zener diodes VR1 and VR2
begin to conduct, drive current into the
TOPSwitch control pin, and directly
control the duty cycle. C3 together with
R3 perform low pass filtering on the
feedback signal to prevent output line
frequency ripple voltage from varying
the duty cycle. For more information,
refer to Design Note DN-7.
Under some conditions, externally
provided bias or supply current driven
into the CONTROL pin can hold the
TOPSwitch in one of the 8 auto-restart
cycles indefinitely and prevent starting.
Shorting the CONTROL pin to the
SOURCE pin will reset the TOPSwitch.
To avoid this problem when doing bench
evaluations, it is recommended that the
VC power supply be turned on before the
DRAIN voltage is applied.
Short interruptions of AC power may
cause TOPSwitch to enter the 8-count
auto-restart cycle before starting again.
This is because the input energy storage
capacitors are not completely discharged
and the CONTROL pin capacitance has
not discharged below the pin internal
power-up reset voltage.
Key Application Issues
Keep the SOURCE pin length very short.
Use a Kelvin connection to the SOURCE
pin for the CONTROL pin bypass
capacitor. Use single point grounding
techniques at the SOURCE pin as shown
in Figure 11.
Minimize peak voltage and ringing on
the DRAIN voltage at turn-off. Use a
Zener or TVS Zener diode to clamp the
DRAIN voltage.
Do not plug the TOPSwitch device into
a “hot” IC socket during test. External
CONTROL pin capacitance may deliver
a surge current sufficient to trigger the
shutdown latch which turns the
TOPSwitch off.
Bias/Feedback
Return
C
CONTROL pin currents during autorestart operation are much lower at low
input voltages (< 20 V) which increases
the auto-restart cycle period (see the IC
vs. Drain Voltage Characteristic curve).
High Voltage
Return
S
D
DRAIN
SOURCE
TOP VIEW
Do not bend SOURCE pin
Keep it short
CONTROL
Bypass
Capacitor
For additional applications information
regarding the TOPSwitch family, refer
to AN-14.
Kelvin-connected
bypass capacitor
and/or compensation network
PC Board
Bias/Feedback
Input
In some cases, minimum loading may
be necessary to keep a lightly loaded or
unloaded output voltage within the
desired range due to the minimum ONtime.
Bend DRAIN pin
forward if needed
for creepage
High-voltage Return
Bias/Feedback Input
Bias/Feedback Return
PI-1240-110194
Figure 11. Recommended TOPSwitch Layout.
F
7/ 09
9
TOP100-4
ABSOLUTE MAXIMUM RATINGS(1)
DRAIN Voltage ............................................ -0.3 to 350 V
CONTROL Voltage ..................................... - 0.3 V to 9 V
Storage Temperature ...................................... -65 to 125°C
Operating Junction Temperature(2) ................. -40 to 150°C
Lead Temperature(3) ................................................. 260°C
Thermal Impedance (θJA) ...................................... 70°C/W
Thermal Impedance (θJC)(4) .................................... 2 °C/W
1. Unless noted, all voltages referenced to SOURCE,
T A = 25°C.
2. Normally limited by internal circuitry.
3. 1/16" from case for 5 seconds.
4. Measured at tab closest to plastic interface.
Conditions
Specification
Symbol
(Unless Otherwise Specified)
See Figure 14
SOURCE = 0 V
T j = -40 to 125°C
Min
Typ
Max
Units
CONTROL FUNCTIONS
Output
Frequency
fOSC
IC = 4 mA, Tj = 25˚C
90
100
110
kHz
Maximum
Duty Cycle
DCMAX
IC = I CD1+ 0.5 mA, See Figure 12
64
67
70
%
Minimum
Duty Cycle
DCMIN
IC = 10 mA, See Figure 12
1.0
1.8
3.0
%
IC = 4 mA, Tj = 25˚C
-11
-16
-21
%/mA
PWM
Gain
See Figure 4
PWM Gain
Temperature Drift
See Note 1
External
Bias Current
IB
Dynamic
Impedance
ZC
%/mA/˚C
-0.05
See Figure 4
IC = 4 mA, Tj = 25˚C
1.5
2.5
4
mA
10
15
22
Ω
See Figure 13
Dynamic Impedance
%/˚C
0.18
Temperature Drift
SHUTDOWN/AUTO-RESTART
CONTROL Pin
Charging Current
IC
Charging Current
Temperature Drift
Auto-restart
Threshold Voltage
10
F
7/ 09
VC(AR)
Tj = 25˚C
VC = 0 V
-2.4
-1.9
-1.2
VC = 5 V
-2
-1.5
-0.8
mA
See Note 1
0.4
%/˚C
S1 open
5.7
V
TOP100-4
Conditions
Specification
Symbol
(Unless Otherwise Specified)
See Figure 14
SOURCE = 0 V
Tj = -40 to 125°C
Min
Typ
Max
Units
SHUTDOWN/AUTO-RESTART (cont.)
UV Lockout
Threshold Voltage
S1 open
Auto-restart
Hysteresis Voltage
S1 open
Auto-restart
Duty Cycle
S1 open
5
Auto-restart
Frequency
S1 open
1.2
0.6
4.7
V
1.0
V
8
%
Hz
CIRCUIT PROTECTION
TOP100
di/dt = 160 mA/µs, T j = 25˚C
0.88
1.25
1.50
2.15
2.20
3.10
2.85
4.00
3.30
4.60
TOP101
di/dt = 280 mA/µs, T j = 25˚C
Self-protection
Current Limit
TOP102
ILIMIT
di/dt = 400 mA/µs, T j = 25˚C
A
TOP103
di/dt = 520 mA/µs, T j = 25˚C
TOP104
di/dt = 600 mA/µs, T j = 25˚C
Leading Edge
Blanking Time
tLEB
IC = 4 mA
150
ns
Current Limit
Delay
tILD
IC = 4 mA
100
ns
°C
Thermal Shutdown
Temperature
IC = 4 mA
125
145
Latched Shutdown
Trigger Current
ISD
See Figure 13
25
45
75
mA
Power-up Reset
Threshold Voltage
VC(RESET)
S2 open
2.0
3.3
4.2
V
F
7/ 09
11
TOP100-4
Conditions
Specification
Symbol
(Unless Otherwise Specified)
See Figure 14
SOURCE = 0 V
T j = -40 to 125°C
Min
Typ
Max
Units
OUTPUT
ON-State
Resistance
RDS(ON)
OFF-State
Current
IDSS
Breakdown
Voltage
BVDSS
TOP100
Tj = 25°C
6.4
7.5
ID = 110 mA
Tj = 100°C
10.5
12.4
TOP101
Tj = 25°C
3.6
4.3
ID = 190 mA
Tj = 100°C
6.0
7.1
TOP102
Tj = 25°C
2.6
3.0
ID = 270 mA
Tj = 100°C
4.2
5.0
TOP103
Tj = 25°C
2.0
2.4
ID = 350 mA
Tj = 100°C
3.3
3.9
TOP104
Tj = 25°C
1.7
2.0
ID = 400 mA
Tj = 100°C
2.8
3.3
Device in Latched Shutdown
500
IC = 4 mA, VDS = 280 V, T A = 125°C
Ω
µA
Device in Latched Shutdown
IC = 4 mA, ID = 500 µA, TA = 25°C
V
350
Measured With
Rise
Time
tr
Fall
Time
tf
Figure 8 Schematic
100
ns
50
ns
Measured With
Figure 8 Schematic
SUPPLY
DRAIN Supply
Voltage
Shunt Regulator
Voltage
VC(SHUNT)
See Note 2
36
IC = 4 mA
5.5
Shunt Regulator
Temperature Drift
CONTROL Supply/
Discharge Current
F
7/ 09
5.8
6.1
±50
ICD1
Output MOSFET Enabled
0.6
1.2
V
ppm/˚C
1.6
mA
ICD2
12
V
Output MOSFET Disabled
0.5
0.8
1.1
TOP100-4
Conditions
Specification
Symbol
(Unless Otherwise Specified)
See Figure 14
VS2 = 16 V R1 = 0 Ω
SOURCE = 0 V
Tj = -40 to 125°C
Min
Typ
Max
Units
LOW INPUT VOLTAGE OPERATION (See Note 3)
DRAIN Supply
Voltage
CONTROL Pin
Charging Current
T j = 25°C
Volts
16
See Note 4
VC = 0 V
-2.3
-1.65
-1
mA
VC = 5 V
-1.2
-0.64
-0.28
mA
8
%
Auto-restart
Duty Cycle
S1/Open
4
Auto-restart
Frequency
S1/Open
0.85
Hz
NOTES:
1. For specifications with negative values, a negative temperature coefficient corresponds to an increase in
magnitude with increasing temperature, and a positive temperature coefficient corresponds to a decrease in
magnitude with increasing temperature.
2. It is possible to start up and operate TOPSwitch at DRAIN voltages well below 36 V. Refer to the "Low Input
Voltage" Specification section for details.
3. This section specifies only parameters affected by low input voltage operation (Drain Voltages less than 36 V). All
other parameters remain unchanged.
4. For low input voltage applications, the primary peak current could be set to a lower value than the current limit to
increase efficiency. Refer to the Output Characteristics graph (Drain Current vs. Drain Voltage). The voltage
across the transformer primary during the ON time is the difference between the input voltage and the drain
voltage (VDS(ON)).
For example, if the input voltage is 16 VDC and a TOP104 (3.3A minimum current limit) is used at a primary peak
current of 1A. Then the (VDS(ON)) is 3 V at 100°C and the energizing voltage across the transformer primary is
13 V.
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13
TOP100-4
TYPICAL CONTROL PIN I-V CHARACTERISTIC
90%
90%
DRAIN
VOLTAGE
t
DC = 1
t2
10%
0V
PI-1215-091794
CONTROL Pin Current (mA)
t1
HV
PI-1216-091794
120
t2
100
80
Latched Shutdown
Trigger Current (45 mA)
60
40
Dynamic
1
=
Impedance Slope
20
0
Figure 12. TOPSwitch Duty Cycle Measurement.
0
2
4
6
8
10
CONTROL Pin Voltage (V)
Figure 13. TOPSwitch CONTROL Pin I-V Characteristic.
R1
470 Ω
5W
S2
DRAIN
SOURCE
R2
CONTROL
S1
TOPSwitch
C1
0.1 µF
C2
47 µF
470 Ω
VS1
0-50 V
VS2
40 V
NOTE: This test circuit is not applicable for current limit or output characteristic measurements.
PI-1905-061396
Figure 14. TOPSwitch General Test Circuit.
14
F
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TOP100-4
BENCH TEST PRECAUTIONS FOR EVALUATION OF ELECTRICAL CHARACTERISTICS
The following precautions should be
followed when testing TOPSwitch by
itself outside of a power supply. The
schematic shown in Figure 14 is
suggested for laboratory testing of
TOPSwitch.
When the DRAIN supply is turned on,
the part will be in the auto-restart mode.
that the continuous DRAIN voltage
waveform may be observed. It is
recommended that the VC power supply
be turned on first and the DRAIN power
supply second if continuous drain voltage
waveforms are to be observed. The
12.5% chance of being in the correct
state is due to the 8:1 counter.
The control pin voltage will be oscillating
at a low frequency from 4.7 to 5.7 V and
the DRAIN is turned on every eighth
cycle of the CONTROL pin oscillation.
If the CONTROL pin power supply is
turned on while in this auto-restart mode,
there is only a 12.5% chance that the
control pin oscillation will be in the
correct state (DRAIN active state) so
Typical Performance Characteristics
BREAKDOWN vs. TEMPERATURE
FREQUENCY vs. TEMPERATURE
1.0
PI-1123A-060794
1.2
Output Frequency
(Normalized to 25°C)
PI-176B-051391
1.0
0.8
0.6
0.4
0.2
0.9
0
-50 -25
0
25
50
75 100 125 150
-50 -25
Junction Temperature (°C)
CURRENT LIMIT vs. TEMPERATURE
1.0
25
50
75 100 125 150
0.8
0.6
0.4
0.2
0
IC vs. DRAIN VOLTAGE
2
CONTROL Pin
Charging Current (mA)
PI-1125-041494
Current Limit
(Normalized to 25°C)
1.2
0
Junction Temperature (°C)
PI-1145-103194
Breakdown Voltage (V)
(Normalized to 25°C)
1.1
VC = 5 V
1.6
1.2
0.8
0.4
0
-50 -25
0
25
50
75 100 125 150
Junction Temperature (°C)
0
20
40
60
80
100
Drain Voltage (V)
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15
TOP100-4
Typical Performance Characteristics (cont.)
OUTPUT CHARACTERISTICS
Drain Current (A)
3
2
Scaling Factors:
TOP104 1.00
TOP103 0.87
TOP102 0.67
TOP101 0.47
TOP100 0.27
1
0
Scaling Factors:
TOP104 1.00
TOP103 0.87
TOP102 0.67
TOP101 0.47
TOP100 0.27
100
10
0
2
4
6
8
10
0
80
Drain Voltage (V)
Power (mW)
PI-1694-112895
100
Scaling Factors:
TOP104 1.00
TOP103 0.87
TOP102 0.67
TOP101 0.47
TOP100 0.27
50
0
0
80
160
240
DRAIN Voltage (V)
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160
240
DRAIN Voltage (V)
DRAIN CAPACITANCE POWER
16
PI-1439-042595
DRAIN Capacitance (pF)
TCASE = 25°C
TCASE = 100°C
4
COSS vs. DRAIN VOLTAGE
1000
PI-1747-011796
5
320
320
TOP100-4
Y03A
Plastic TO-220/3
DIM
inches
mm
A
B
C
D
E
F
G
H
J
K
L
M
N
O
P
.460-.480
.400-.415
.236-.260
.240 - REF.
.520-.560
.028-.038
.045-.055
.090-.110
.165-.185
.045-.055
.095-.115
.015-.020
.705-.715
.146-.156
.103-.113
11.68-12.19
10.16-10.54
5.99-6.60
6.10 - REF.
13.21-14.22
.71-.97
1.14-1.40
2.29-2.79
4.19-4.70
1.14-1.40
2.41-2.92
.38-.51
17.91-18.16
3.71-3.96
2.62-2.87
J
B
K
P
C
O
A
N
L
D
E
Notes:
1. Package dimensions conform to
JEDEC specification TO-220 AB for
standard flange mounted, peripheral
lead package; .100 inch lead spacing
(Plastic) 3 leads (issue J, March 1987)
2. Controlling dimensions are inches.
3. Pin numbers start with Pin 1, and
continue from left to right when
viewed from the top.
4. Dimensions shown do not include
mold flash or other protrusions. Mold
flash or protrusions shall not exceed
.006 (.15 mm) on any side.
5. Position of terminals to be
measured at a position .25 (6.35 mm)
from the body.
6. All terminals are solder plated.
* LEADS AND TAB ARE
SOLDER PLATED
F
M
G
H
PI-1848-050696
F
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17
TOP100-4
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability.
Power Integrations does not assume any liability arising from the use of any device or circuit described herein, nor does it
convey any license under its patent rights or the rights of others.
PI Logo and TOPSwitch are registered trademarks of Power Integrations, Inc.
©Copyright 1994, Power Integrations, Inc. 477 N. Mathilda Avenue, Sunnyvale, CA 94086
WORLD HEADQUARTERS
Power Integrations, Inc.
477 N. Mathilda Avenue
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USA
Main:
408•523•9200
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Phone: 408•523•9265
Fax:
408•523•9365
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Phone: 44•(0)•1753•622•208
Fax:
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Phone: 81•(0)•45•471•1021
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Please Contact Customer Service
Phone: 408•523•9265
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1
F
7/ 09
APPLICATIONS FAX
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