TOP258PN

TOP252-262 TOPSwitch-HX Family ® Enhanced EcoSmart , Integrated Off-Line Switcher with Advanced Feature Set and Extended Power Range Product Highlights Lower System Cost, Higher Design Flexibility • Multi-mode operation maximizes efficiency at all loads • New eSIP-7F and eSIP-7C packages • Low thermal impedance junction-to-case (2 °C per watt) • Low height is ideal for adapters where space is limited • Simple mounting using a clip to aid low cost manufacturing • Horizontal eSIP-7F package ideal for ultra low height adapter and monitor applications • Extended package creepage distance from DRAIN pin to adjacent pin and to heat sink • No heatsink required up to 35 W using P, G and M packages with universal input voltage and up to 48 W at 230 VAC • Output overvoltage protection (OVP) is user programmable for latching/non-latching shutdown with fast AC reset • Allows both primary and secondary sensing • Line undervoltage (UV) detection prevents turn-off glitches • Line overvoltage (OV) shutdown extends line surge limit • Accurate programmable current limit • Optimized line feed-forward for line ripple rejection • 132 kHz frequency (254Y-258Y and all E/L packages) reduces transformer and power supply size • Half frequency option for video applications • Frequency jittering reduces EMI filter cost Output Power Table Product5 TOP252PN/GN TOP252MN TOP253PN/GN 15 W TOP253MN TOP254PN/GN 16 W TOP254MN TOP255PN/GN 19 W TOP255MN TOP256PN/GN 21 W TOP256MN TOP257PN/GN 25 W TOP257MN TOP258PN/GN 29 W TOP258MN Table 1. AC IN + DC OUT - ® D V CONTROL TOPSwitch-HX S X F C PI-4510-100206 Figure 1. • • • • • Typical Flyback Application. Heatsink is connected to SOURCE for low EMI Improved auto-restart delivers 600 mW output at 110 VAC input • >500 mW output at 265 VAC input ® Y Package Option for TOP259-261 In order to improve noise-immunity on large TOPSwitch-HX Y package parts, the F pin has been removed (TOP259-261YN are fixed at 66 kHz switching frequency) and replaced with a SIGNAL GROUND (G) pin. This pin acts as a low noise path for the C pin capacitor and the X pin resistor. It is only required for the TOP259-261YN package parts. Description TOPSwitch-HX cost effectively incorporates a 700 V power MOSFET, high voltage switched current source, PWM control, oscillator, thermal shutdown circuit, fault protection and other control circuitry onto a monolithic device. Notes for Table 1: 1. Minimum continuous power in a typical non-ventilated enclosed adapter measured at +50 °C ambient. Use of an external heat sink will increase power capability. 2. Minimum continuous power in an open frame design at +50 °C ambient. 3. Peak power capability in any design at +50 °C ambient. 4. 230 VAC or 110/115 VAC with doubler. 5. Packages: P: DIP-8C, G: SMD-8C, M: SDIP-10C, Y: TO-220-7C, E: eSIP-7C, L: eSIP-7F. See part ordering information. 6. TOP261 and TOP262 have the same current limit set point. In some applications TOP262 may run cooler than TOP261 due to a lower RDS(ON) for the larger device. 7. TOP256E package parts are available with Green (Halogen Free) mold compound. See Part Ordering Information on page 47. Parametrically green material encapsulated E package parts are identical to non-green parts. AC IN + DC OUT - D V CONTROL TOPSwitch-HX S X G C PI-4973-122607 Figure 2. Typical Flyback Application TOP259YN, TOP260YN and TOP261YN. 2 Rev. F 01/09 www.powerint.com TOP252-262 Section List Functional Block Diagram ....................................................................................................................................... 4 Pin Functional Description ...................................................................................................................................... 6 TOPSwitch-HX Family Functional Description ....................................................................................................... 7 CONTROL (C) Pin Operation .................................................................................................................................... 8 Oscillator and Switching Frequency.......................................................................................................................... 8 Pulse Width Modulator ............................................................................................................................................ 9 Maximum Load Cycle .............................................................................................................................................. 9 Error Amplifier .......................................................................................................................................................... 9 On-Chip Current Limit with External Programmability ............................................................................................... 9 Line Under-Voltage Detection (UV).......................................................................................................................... 10 Line Overvoltage Shutdown (OV) ............................................................................................................................ 11 Hysteretic or Latching Output Overvoltage Protection (OVP)................................................................................... 11 Line Feed-Forward with DCMAX Reduction .............................................................................................................. 13 Remote ON/OFF and Synchronization.................................................................................................................... 13 Soft-Start ............................................................................................................................................................... 13 Shutdown/Auto-Restart ......................................................................................................................................... 13 Hysteretic Over-Temperature Protection ................................................................................................................. 13 Bandgap Reference ............................................................................................................................................... 13 High-Voltage Bias Current Source .......................................................................................................................... 13 Typical Uses of FREQUENCY (F) Pin ...................................................................................................................... 15 Typical Uses of VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pins .......................................... 16 Typical Uses of MULTI-FUNCTION (M) Pin ........................................................................................................... 18 Application Examples .............................................................................................................................................. 21 A High Efficiency, 35 W, Dual Output – Universal Input Power Supply ..................................................................... 21 A High Efficiency, 1500 W, 250-380 VDC Input Power Supply ................................................................................ 22 A High Efficiency, 20 W Continuous – 80 W Peak, Universal Input Power Supply ................................................... 23 A High Efficiency, 65 W, Universal Input Power Supply ........................................................................................... 24 Key Application Considerations .............................................................................................................................. 25 TOPSwitch-HX vs.TOPSwitch-GX ....................................................................................................................... . 25 TOPSwitch-HX Design Considerations .................................................................................................................. 26 TOPSwitch-HX Layout Considerations ................................................................................................................... 27 Quick Design Checklist .......................................................................................................................................... 31 Design Tools .......................................................................................................................................................... 31 Product Specifications and Test Conditions .......................................................................................................... 32 Typical Performance Characteristics .................................................................................................................... 39 Package Outlines .................................................................................................................................................... 43 Part Ordering Information ........................................................................................................................................ 47 3 www.powerint.com Rev. F 01/09 TOP252-262 VC 0 CONTROL (C) ZC 1 SHUNT REGULATOR/ ERROR AMPLIFIER + DRAIN (D) INTERNAL SUPPLY - + 5.8 V 4.8 V SOFT START + KPS(UPPER) + 5.8 V INTERNAL UV COMPARATOR VI (LIMIT) IFB CURRENT LIMIT ADJUST ON/OFF ÷ 16 SHUTDOWN/ AUTO-RESTART KPS(LOWER) + VBG + VT MULTIFUNCTION (M) STOP LOGIC HYSTERETIC THERMAL SHUTDOWN CURRENT LIMIT COMPARATOR SOURCE (S) CONTROLLED TURN-ON GATE DRIVER V OVP OV/ UV DCMAX DCMAX STOP SOFT START DMAX CLOCK S R Q LINE SENSE OSCILLATOR WITH JITTER F REDUCTION LEADING EDGE BLANKING F REDUCTION SOFT START IFB PWM IPS(UPPER) IPS(LOWER) OFF KPS(UPPER) KPS(LOWER) SOURCE (S) PI-4508-120307 Figure 3a. Functional Block Diagram (P and G Packages). VC 0 CONTROL (C) ZC 1 SHUNT REGULATOR/ ERROR AMPLIFIER + DRAIN (D) INTERNAL SUPPLY - + 5.8 V 4.8 V SOFT START + KPS(UPPER) + 5.8 V INTERNAL UV COMPARATOR VI (LIMIT) IFB CURRENT LIMIT ADJUST ON/OFF ÷ 16 SHUTDOWN/ AUTO-RESTART STOP LOGIC KPS(LOWER) + EXTERNAL CURRENT LIMIT (X) VOLTAGE MONITOR (V) VBG + VT CURRENT LIMIT COMPARATOR SOURCE (S) CONTROLLED TURN-ON GATE DRIVER 1V HYSTERETIC THERMAL SHUTDOWN V LINE SENSE OVP OV/ UV DCMAX DCMAX STOP SOFT START DMAX CLOCK S R Q OSCILLATOR WITH JITTER F REDUCTION LEADING EDGE BLANKING F REDUCTION SOFT START IFB PWM IPS(UPPER) IPS(LOWER) OFF KPS(UPPER) KPS(LOWER) SOURCE (S) PI-4643-082907 Figure 3b. Functional Block Diagram (M Package). 4 Rev. F 01/09 www.powerint.com TOP252-262 VC 0 CONTROL (C) ZC 1 SHUNT REGULATOR/ ERROR AMPLIFIER + IFB VI (LIMIT) DRAIN (D) INTERNAL SUPPLY - + 5.8 V 4.8 V SOFT START + KPS(UPPER) + 5.8 V INTERNAL UV COMPARATOR CURRENT LIMIT ADJUST ON/OFF ÷ 16 SHUTDOWN/ AUTO-RESTART STOP LOGIC KPS(LOWER) + EXTERNAL CURRENT LIMIT (X) VOLTAGE MONITOR (V) VBG + VT CURRENT LIMIT COMPARATOR SOURCE (S) CONTROLLED TURN-ON GATE DRIVER 1V HYSTERETIC THERMAL SHUTDOWN V LINE SENSE OVP OV/ UV DCMAX DCMAX 66k/132k STOP SOFT START DMAX CLOCK S R Q OSCILLATOR WITH JITTER F REDUCTION FREQUENCY (F) LEADING EDGE BLANKING F REDUCTION SOFT START IFB PWM IPS(UPPER) IPS(LOWER) OFF KPS(UPPER) KPS(LOWER) SOURCE (S) PI-4511-082907 Figure 3c. Functional Block Diagram (TOP254-258 YN Package and all eSIP Packages). VC 0 CONTROL (C) ZC 1 SHUNT REGULATOR/ ERROR AMPLIFIER + DRAIN (D) INTERNAL SUPPLY - + 5.8 V 4.8 V SOFT START + KPS(UPPER) + 5.8 V INTERNAL UV COMPARATOR VI (LIMIT) IFB CURRENT LIMIT ADJUST ON/OFF ÷ 16 SHUTDOWN/ AUTO-RESTART STOP LOGIC KPS(LOWER) + EXTERNAL CURRENT LIMIT (X) VOLTAGE MONITOR (V) VBG + VT CURRENT LIMIT COMPARATOR SOURCE (S) CONTROLLED TURN-ON GATE DRIVER 1V HYSTERETIC THERMAL SHUTDOWN V LINE SENSE OVP OV/ UV DCMAX DCMAX STOP SOFT START DMAX CLOCK S R Q OSCILLATOR WITH JITTER F REDUCTION LEADING EDGE BLANKING SOURCE (S) F REDUCTION SOFT START IFB PWM IPS(UPPER) IPS(LOWER) OFF KPS(UPPER) KPS(LOWER) PI-4974-122607 SIGNAL GROUND (G) Figure 3d. Functional Block Diagram TOP259YN, TOP260YN, TOP261YN. 5 www.powerint.com Rev. F 01/09 TOP252-262 Pin Functional Description DRAIN (D) Pin: High-voltage power MOSFET DRAIN pin. The internal start-up bias current is drawn from this pin through a switched highvoltage current source. Internal current limit sense point for drain current. CONTROL (C) Pin: Error amplifier and feedback current input pin for duty cycle control. Internal shunt regulator connection to provide internal bias current during normal operation. It is also used as the connection point for the supply bypass and auto-restart/ compensation capacitor. EXTERNAL CURRENT LIMIT (X) Pin (Y, M, E and L package): Input pin for external current limit adjustment and remote ON/OFF. A connection to SOURCE pin disables all functions on this pin. VOLTAGE MONITOR (V) Pin (Y & M package only): Input for OV, UV, line feed forward with DCMAX reduction, output overvoltage protection (OVP), remote ON/OFF and device reset. A connection to the SOURCE pin disables all functions on this pin. MULTI-FUNCTION (M) Pin (P & G packages only): This pin combines the functions of the VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) pins of the Y package into one pin. Input pin for OV, UV, line feed forward with DCMAX PI-4711-021308 PI-4983-021308 + RLS 4M VUV = IUV × RLS + VV (IV = IUV) VOV = IOV × RLS + VV (IV = IOV) For RLS = 4 M VUV = 102.8 VDC VOV = 451 VDC DCMAX@100 VDC = 76% DCMAX@375 VDC = 41% C DC Input Voltage D V CONTROL S X RIL 12 k For RIL = 12 k ILIMIT = 61% See Figure 55b for other resistor values (RIL) to select different ILIMIT values. E Package (eSIP-7C) Exposed Pad (Hidden) Internally Connected to SOURCE Pin Y Package (TO-220-7C) Note: Y package for TOP259-261 Figure 5. TOP254-258 Y and All M/E/L Package Line Sense and Externally Set Current Limit. 12345 7 VXCF S D L Package (eSIP-7F) Tab Internally Connected to SOURCE Pin + RLS 4M VUV = IUV × RLS + VV (IV = IUV) VOV = IOV × RLS + VV (IV = IOV) For RLS = 4 M VUV = 102.8 VDC VOV = 451 VDC DCMAX@100 VDC = 76% DCMAX@375 VDC = 41% C 12345 7 V XCSG D Lead Bend Outward from Drawing (Refer to eSIP-7F Package Outline Drawing) DC Input Voltage D V CONTROL 12345 7 VXCF S D M Package V X C D S RIL 12 k X G For RIL = 12 k ILIMIT = 61% See Figure 55b for other resistor values (RIL) to select different ILIMIT values. Y Package (TO-220-7C) 10 S 9 8 7 6 S S S S Tab Internally Connected to SOURCE Pin Note: Y package for TOP254-258 Figure 6. - 1 2 3 5 TOP259-261 Y Package Line Sense and External Current Limit. + VUV = IUV × RLS + VM (IM = IUV) VOV = IOV × RLS + VM (IM = IOV) RLS DC Input Voltage D M CONTROL P and G Package M C 4M 1 2 8 7 6 S S S S For RLS = 4 M VUV = 102.8 VDC VOV = 451 VDC DCMAX@100 VDC = 76% DCMAX@375 VDC = 41% D 4 5 12345 7 VXCS F D PI-4644-091108 C S PI-4712-120307 Figure 7. Figure 4. Pin Configuration (Top View). P/G Package Line Sense. 6 Rev. F 01/09 www.powerint.com TOP252-262 Auto-Restart + For RIL = 12 k ILIMIT = 61% For RIL = 19 k ILIMIT = 37% DC Input Voltage D M CONTROL 78 Duty Cycle (%) Slope = PWM Gain (constant over load range) See Figure 55b for other resistor values (RIL) to select different ILIMIT values. RIL C S PI-4713-021308 CONTROL Current Figure 8. Drain Peak Current To Current Limit Ratio (%) P/G Package Externally Set Current Limit. 100 reduction, output overvoltage protection (OVP), external current limit adjustment, remote ON/OFF and device reset. A connection to SOURCE pin disables all functions on this pin and makes TOPSwitch-HX operate in simple three terminal mode (like TOPSwitch-II). FREQUENCY (F) Pin (TOP254-258Y, and all E and L packages): Input pin for selecting switching frequency 132 kHz if connected to SOURCE pin and 66 kHz if connected to CONTROL pin. The switching frequency is internally set for fixed 66 kHz operation in the P, G, M package and TOP259YN, TOP260YN and TOP261YN. SIGNAL GROUND (G) Pin (TOP259YN, TOP260YN & TOP261YN only): Return for C pin capacitor and X pin resistor. SOURCE (S) Pin: Output MOSFET source connection for high voltage power return. Primary side control circuit common and reference point. 55 25 CONTROL Current Full Frequency Mode 132 Low Frequency Mode Frequency (kHz) 66 Jitter Variable Frequency Mode Multi-Cycle Modulation 30 ICD1 IB IC01 IC02 IC03 ICOFF CONTROL Current PI-4645-041107 TOPSwitch-HX Family Functional Description Like TOPSwitch-GX, TOPSwitch-HX is an integrated switched mode power supply chip that converts a current at the control input to a duty cycle at the open drain output of a high voltage power MOSFET. During normal operation the duty cycle of the power MOSFET decreases linearly with increasing CONTROL pin current as shown in Figure 9. In addition to the three terminal TOPSwitch features, such as the high voltage start-up, the cycle-by-cycle current limiting, loop compensation circuitry, auto-restart and thermal shutdown, the TOPSwitch-HX incorporates many additional functions that reduce system cost, increase power supply performance and design flexibility. A patented high voltage CMOS technology allows both the high-voltage power MOSFET and all the low voltage control circuitry to be cost effectively integrated onto a single monolithic chip. Three terminals, FREQUENCY, VOLTAGE-MONITOR, and EXTERNAL CURRENT LIMIT (available in Y and E/L packages), Figure 9. Control Pin Characteristics (Multi-Mode Operation). two terminals, VOLTAGE-MONITOR and EXTERNAL CURRENT LIMIT (available in M package) or one terminal MULTI-FUNCTION (available in P and G package) have been used to implement some of the new functions. These terminals can be connected to the SOURCE pin to operate the TOPSwitch-HX in a TOPSwitch-like three terminal mode. However, even in this three terminal mode, the TOPSwitch-HX offers many transparent features that do not require any external components: 1. A fully integrated 17 ms soft-start significantly reduces or eliminates output overshoot in most applications by sweeping both current limit and frequency from low to high to limit the peak currents and voltages during start-up. 2. A maximum duty cycle (DCMAX) of 78% allows smaller input storage capacitor, lower input voltage requirement and/or higher power capability. 3. Multi-mode operation optimizes and improves the power supply efficiency over the entire load range while maintaining good cross regulation in multi-output supplies. 7 www.powerint.com Rev. F 01/09 TOP252-262 4. Switching frequency of 132 kHz reduces the transformer size with no noticeable impact on EMI. 5. Frequency jittering reduces EMI in the full frequency mode at high load condition. 6. Hysteretic over-temperature shutdown ensures automatic recovery from thermal fault. Large hysteresis prevents circuit board overheating. 7. Packages with omitted pins and lead forming provide large drain creepage distance. 8. Reduction of the auto-restart duty cycle and frequency to improve the protection of the power supply and load during open loop fault, short circuit, or loss of regulation. 9. Tighter tolerances on I2f power coefficient, current limit reduction, PWM gain and thermal shutdown threshold. The VOLTAGE-MONITOR (V) pin is usually used for line sensing by connecting a 4 MΩ resistor from this pin to the rectified DC high voltage bus to implement line overvoltage (OV), undervoltage (UV) and dual-slope line feed-forward with DCMAX reduction. In this mode, the value of the resistor determines the OV/UV thresholds and the DCMAX is reduced linearly with a dual slope to improve line ripple rejection. In addition, it also provides another threshold to implement the latched and hysteretic output overvoltage protection (OVP). The pin can also be used as a remote ON/OFF using the IUV threshold. The EXTERNAL CURRENT LIMIT (X) pin can be used to reduce the current limit externally to a value close to the operating peak current, by connecting the pin to SOURCE through a resistor. This pin can also be used as a remote ON/OFF input. For the P and G package the VOLTAGE-MONITOR and EXTERNAL CURRENT LIMIT pin functions are combined on one MULTI-FUNCTION (M) pin. However, some of the functions become mutually exclusive. The FREQUENCY (F) pin in the TOP254-258 Y and E/L packages set the switching frequency in the full frequency PWM mode to the default value of 132 kHz when connected to SOURCE pin. A half frequency option of 66 kHz can be chosen by connecting this pin to the CONTROL pin instead. Leaving this pin open is not recommended. In the P, G and M packages and the TOP259-261 Y packages, the frequency is set internally at 66 kHz in the full frequency PWM mode. CONTROL (C) Pin Operation The CONTROL pin is a low impedance node that is capable of receiving a combined supply and feedback current. During normal operation, a shunt regulator is used to separate the feedback signal from the supply current. CONTROL pin voltage VC is the supply voltage for the control circuitry including the MOSFET gate driver. An external bypass capacitor closely connected between the CONTROL and SOURCE pins is required to supply the instantaneous gate drive current. The total amount of capacitance connected to this pin also sets the auto-restart timing as well as control loop compensation. When rectified DC high voltage is applied to the DRAIN pin during start-up, the MOSFET is initially off, and the CONTROL pin capacitor is charged through a switched high voltage current source connected internally between the DRAIN and CONTROL pins. When the CONTROL pin voltage VC reaches approximately 5.8 V, the control circuitry is activated and the soft-start begins. The soft-start circuit gradually increases the drain peak current and switching frequency from a low starting value to the maximum drain peak current at the full frequency over approximately 17 ms. If no external feedback/supply current is fed into the CONTROL pin by the end of the soft-start, the high voltage current source is turned off and the CONTROL pin will start discharging in response to the supply current drawn by the control circuitry. If the power supply is designed properly, and no fault condition such as open loop or shorted output exists, the feedback loop will close, providing external CONTROL pin current, before the CONTROL pin voltage has had a chance to discharge to the lower threshold voltage of approximately 4.8 V (internal supply undervoltage lockout threshold). When the externally fed current charges the CONTROL pin to the shunt regulator voltage of 5.8 V, current in excess of the consumption of the chip is shunted to SOURCE through an NMOS current mirror as shown in Figure 3. The output current of that NMOS current mirror controls the duty cycle of the power MOSFET to provide closed loop regulation. The shunt regulator has a finite low output impedance ZC that sets the gain of the error amplifier when used in a primary feedback configuration. The dynamic impedance ZC of the CONTROL pin together with the external CONTROL pin capacitance sets the dominant pole for the control loop. When a fault condition such as an open loop or shorted output prevents the flow of an external current into the CONTROL pin, the capacitor on the CONTROL pin discharges towards 4.8 V. At 4.8 V, auto-restart is activated, which turns the output MOSFET off and puts the control circuitry in a low current standby mode. The high-voltage current source turns on and charges the external capacitance again. A hysteretic internal supply undervoltage comparator keeps VC within a window of typically 4.8 V to 5.8 V by turning the high-voltage current source on and off as shown in Figure 11. The auto-restart circuit has a divide-by-sixteen counter, which prevents the output MOSFET from turning on again until sixteen discharge/ charge cycles have elapsed. This is accomplished by enabling the output MOSFET only when the divide-by-sixteen counter reaches the full count (S15). The counter effectively limits TOPSwitch-HX power dissipation by reducing the auto-restart duty cycle to typically 2%. Auto-restart mode continues until output voltage regulation is again achieved through closure of the feedback loop. Oscillator and Switching Frequency The internal oscillator linearly charges and discharges an internal capacitance between two voltage levels to create a triangular waveform for the timing of the pulse width modulator. This oscillator sets the pulse width modulator/current limit latch at the beginning of each cycle. The nominal full switching frequency of 132 kHz was chosen to minimize transformer size while keeping the fundamental EMI frequency below 150 kHz. The FREQUENCY pin (available only in TOP254-258 Y and E, L packages), when shorted to the CONTROL pin, lowers the full switching frequency to 66 kHz 8 Rev. F 01/09 www.powerint.com TOP252-262 packages). Duty cycle is reduced from DCMAX through the reduction of the on-time when IC is increased beyond IB. This operation is identical to the PWM control of all other TOPSwitch families. TOPSwitch-HX only operates in this mode if the cycleby-cycle peak drain current stays above kPS(UPPER)*ILIMIT(set), where kPS(UPPER) is 55% (typical) and ILIMIT(set) is the current limit externally set via the X or M pin. Variable Frequency PWM mode: When peak drain current is lowered to kPS(UPPER)* ILIMIT(set) as a result of power supply load reduction, the PWM modulator initiates the transition to variable frequency PWM mode, and gradually turns off frequency jitter. In this mode, peak drain current is held constant at kPS(UPPER)* ILIMIT(set) while switching frequency drops from the initial full frequency of fOSC (132 kHz or 66 kHz) towards the minimum frequency of fMCM(MIN) (30 kHz typical). Duty cycle reduction is accomplished by extending the off-time. Low Frequency PWM mode: When switching frequency reaches fMCM(MIN) (30 kHz typical), the PWM modulator starts to transition to low frequency mode. In this mode, switching frequency is held constant at fMCM(MIN) and duty cycle is reduced, similar to the full frequency PWM mode, through the reduction of the on-time. Peak drain current decreases from the initial value of kPS(UPPER)* ILIMIT(set) towards the minimum value of kPS(LOWER)*ILIMIT(set), where kPS(LOWER) is 25% (typical) and ILIMIT(set) is the current limit externally set via the X or M pin. Multi-Cycle-Modulation mode: When peak drain current is lowered to kPS(LOWER)*ILIMIT(set), the modulator transitions to multicycle-modulation mode. In this mode, at each turn-on, the modulator enables output switching for a period of TMCM(MIN) at the switching frequency of fMCM(MIN) (4 or 5 consecutive pulses at 30 kHz) with the peak drain current of kPS(LOWER)*ILIMIT(set), and stays off until the CONTROL pin current falls below IC(OFF). This mode of operation not only keeps peak drain current low but also minimizes harmonic frequencies between 6 kHz and 30 kHz. By avoiding transformer resonant frequency this way, all potential transformer audible noises are greatly supressed. Maximum Duty Cycle The maximum duty cycle, DCMAX, is set at a default maximum value of 78% (typical). However, by connecting the VOLTAGEMONITOR or MULTI-FUNCTION pin (depending on the package) to the rectified DC high voltage bus through a resistor with appropriate value (4 MΩ typical), the maximum duty cycle can be made to decrease from 78% to 40% (typical) when input line voltage increases from 88 V to 380 V, with dual gain slopes. Error Amplifier The shunt regulator can also perform the function of an error amplifier in primary side feedback applications. The shunt regulator voltage is accurately derived from a temperaturecompensated bandgap reference. The CONTROL pin dynamic impedance ZC sets the gain of the error amplifier. The CONTROL pin clamps external circuit signals to the VC voltage level. The CONTROL pin current in excess of the supply current is separated by the shunt regulator and becomes the feedback current Ifb for the pulse width modulator. PI-4530-041107 fOSC + Switching Frequency fOSC - 4 ms VDRAIN Time Figure 10. Switching Frequency Jitter (Idealized VDRAIN Waveforms). (half frequency), which may be preferable in some cases such as noise sensitive video applications or a high efficiency standby mode. Otherwise, the FREQUENCY pin should be connected to the SOURCE pin for the default 132 kHz. In the M, P and G packages and the TOP259-261 Y package option, the full frequency PWM mode is set at 66 kHz, for higher efficiency and increased output power in all applications. To further reduce the EMI level, the switching frequency in the full frequency PWM mode is jittered (frequency modulated) by approximately ±2.5 kHz for 66 kHz operation or ±5 kHz for 132 kHz operation at a 250 Hz (typical) rate as shown in Figure 10. The jitter is turned off gradually as the system is entering the variable frequency mode with a fixed peak drain current. Pulse Width Modulator The pulse width modulator implements multi-mode control by driving the output MOSFET with a duty cycle inversely proportional to the current into the CONTROL pin that is in excess of the internal supply current of the chip (see Figure 9). The feedback error signal, in the form of the excess current, is filtered by an RC network with a typical corner frequency of 7 kHz to reduce the effect of switching noise in the chip supply current generated by the MOSFET gate driver. To optimize power supply efficiency, four different control modes are implemented. At maximum load, the modulator operates in full frequency PWM mode; as load decreases, the modulator automatically transitions, first to variable frequency PWM mode, then to low frequency PWM mode. At light load, the control operation switches from PWM control to multi-cyclemodulation control, and the modulator operates in multi-cyclemodulation mode. Although different modes operate differently to make transitions between modes smooth, the simple relationship between duty cycle and excess CONTROL pin current shown in Figure 9 is maintained through all three PWM modes. Please see the following sections for the details of the operation of each mode and the transitions between modes. Full Frequency PWM mode: The PWM modulator enters full frequency PWM mode when the CONTROL pin current (IC) reaches IB. In this mode, the average switching frequency is kept constant at fOSC (66 kHz for P, G and M packages and TOP259-261 Y, pin selectable 132 kHz or 66 kHz for Y and E/L 9 www.powerint.com Rev. F 01/09 TOP252-262 ~ ~ ~ ~ VUV ~ ~ ~ ~ ~ ~ VLINE 0V S15 S14 S13 S12 S0 S15 S14 S13 S12 S0 S15 S14 S13 S12 S0 S15 S15 VC 0V 5.8 V 4.8 V ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ VDRAIN 0V ~ ~ VOUT ~ ~ ~ ~ ~ ~ 0V 1 2 3 2 4 PI-4531-121206 Note: S0 through S15 are the output states of the auto-restart counter Figure 11. Typical Waveforms for (1) Power Up (2) Normal Operation (3) Auto-Restart (4) Power Down. On-Chip Current Limit with External Programmability The cycle-by-cycle peak drain current limit circuit uses the output MOSFET ON-resistance as a sense resistor. A current limit comparator compares the output MOSFET on-state drain to source voltage VDS(ON) with a threshold voltage. High drain current causes VDS(ON) to exceed the threshold voltage and turns the output MOSFET off until the start of the next clock cycle. The current limit comparator threshold voltage is temperature compensated to minimize the variation of the current limit due to temperature related changes in RDS(ON) of the output MOSFET. The default current limit of TOPSwitch-HX is preset internally. However, with a resistor connected between EXTERNAL CURRENT LIMIT (X) pin (Y, E/L and M packages) or MULTIFUNCTION (M) pin (P and G package) and SOURCE pin (for TOP259-261 Y, the X pin is connected to the SIGNAL GROUND (G) pin), current limit can be programmed externally to a lower level between 30% and 100% of the default current limit. By setting current limit low, a larger TOPSwitch-HX than necessary for the power required can be used to take advantage of the lower RDS(ON) for higher efficiency/smaller heat sinking requirements. TOPSwitch-HX current limit reduction initial tolerance through the X pin (or M pin) has been improved significantly compare with previous TOPSwitch-GX. With a second resistor connected between the EXTERNAL CURRENT LIMIT (X) pin (Y, E/L and M packages) or MULTI-FUNCTION (M) pin (P and G package) and the rectified DC high voltage bus, the current limit is reduced with increasing line voltage, allowing a true power limiting operation against line variation to be implemented. When using an RCD clamp, this power limiting technique reduces maximum clamp voltage at high line. This allows for higher reflected voltage designs as well as reducing clamp dissipation. The leading edge blanking circuit inhibits the current limit comparator for a short time after the output MOSFET is turned on. The leading edge blanking time has been set so that, if a power supply is designed properly, current spikes caused by primary-side capacitances and secondary-side rectifier reverse recovery time should not cause premature termination of the switching pulse. The current limit is lower for a short period after the leading edge blanking time. This is due to dynamic characteristics of the MOSFET. During startup and fault conditions the controller prevents excessive drain currents by reducing the switching frequency. Line Undervoltage Detection (UV) At power up, UV keeps TOPSwitch-HX off until the input line voltage reaches the undervoltage threshold. At power down, UV prevents auto-restart attempts after the output goes out of regulation. This eliminates power down glitches caused by slow discharge of the large input storage capacitor present in applications such as standby supplies. A single resistor connected from the VOLTAGE-MONITOR pin (Y, E/L and M packages) or MULTI-FUNCTION pin (P and G packages) to the rectified DC high voltage bus sets UV threshold during power up. Once the power supply is successfully turned on, the UV threshold is lowered to 44% of the initial UV threshold to allow extended input voltage operating range (UV low threshold). If the UV low threshold is reached during operation without the power supply losing regulation, the device will turn off and stay off until UV (high threshold) has been reached again. If the power supply loses regulation before reaching the UV low threshold, the device will enter auto-restart. At the end of each auto-restart cycle (S15), the UV comparator is enabled. If the UV high threshold is not exceeded, the MOSFET will be disabled during the next cycle (see Figure 11). The UV feature can be disabled independent of the OV feature. 10 Rev. F 01/09 www.powerint.com TOP252-262 Line Overvoltage Shutdown (OV) The same resistor used for UV also sets an overvoltage threshold, which, once exceeded, will force TOPSwitch-HX to stop switching instantaneously (after completion of the current switching cycle). If this condition lasts for at least 100 μs, the TOPSwitch-HX output will be forced into off state. Unlike with TOPSwitch-GX, however, when the line voltage is back to normal with a small amount of hysteresis provided on the OV threshold to prevent noise triggering, the state machine sets to S13 and forces TOPSwitch-HX to go through the entire autorestart sequence before attempting to switch again. The ratio of OV and UV thresholds is preset at 4.5, as can be seen in Figure 12. When the MOSFET is off, the rectified DC high voltage surge capability is increased to the voltage rating of the MOSFET (700 V), due to the absence of the reflected voltage and leakage spikes on the drain. The OV feature can be disabled independent of the UV feature. In order to reduce the no-load input power of TOPSwitch-HX designs, the V-pin (or M-pin for P Package) operates at very low currents. This requires careful layout considerations when designing the PCB to avoid noise coupling. Traces and components connected to the V-pin should not be adjacent to any traces carrying switching currents. These include the drain, Voltage Monitor and External Current Limit Pin Table* Figure Number Three Terminal Operation Line Undervoltage Line Overvoltage Line Feed-Forward (DCMAX) Output Overvoltage Protection Overload Power Limiting External Current Limit Remote ON/OFF Device Reset *This table is only a partial list of many VOLTAGE MONITOR and EXTERNAL CURRENT LIMIT Pin Configurations that are possible. Table 2. VOLTAGE MONITOR (V) Pin and EXTERNAL CURRENT LIMIT (X) Pin Configuration Options. clamp network, bias winding return or power traces from other converters. If the line sensing features are used, then the sense resistors must be placed within 10 mm of the V-pin to minimize the V-pin node area. The DC bus should then be routed to the line sense resistors. Note that external capacitance must not be connected to the V-pin as this may cause misoperaton of the V pin related functions. Hysteretic or Latching Output Overvoltage Protection (OVP) The detection of the hysteretic or latching output overvoltage protection (OVP) is through the trigger of the line overvoltage threshold. The V-pin or M-pin voltage will drop by 0.5 V, and the controller measures the external attached impedance immediately after this voltage drops. If IV or IM exceeds IOV(LS) (336 μA typical) longer than 100 μs, TOPSwitch-HX will latch into a permanent off state for the latching OVP. It only can be reset if V V or VM goes below 1 V or VC goes below the powerup-reset threshold (VC(RESET)) and then back to normal. If IV or IM does not exceed IOV(LS) or exceeds no longer than 100 μs, TOPSwitch-HX will initiate the line overvoltage and the hysteretic OVP. Their behavior will be identical to the line overvoltage shutdown (OV) that has been described in detail in the previous section. 16 17 18 19 20 21 22 23 24 25 26 27 28 ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ Multi-Function Pin Table* Figure Number Three Terminal Operation Line Undervoltage Line Overvoltage Line Feed-Forward (DCMAX) Output Overvoltage Protection Overload Power Limiting External Current Limit Remote ON/OFF Device Reset *This table is only a partial list of many MULTI-FUNCTIONAL Pin Configurations that are possible. Table 3. MULTI-FUNCTION (M) Pin Configuration Options. 29 30 31 32 33 34 35 36 37 38 39 40 ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ 11 www.powerint.com Rev. F 01/09 TOP252-262 M Pin X Pin IREM(N) (Enabled) Output MOSFET Switching (Disabled) Disabled when supply output goes out of regulation ILIMIT (Default) Current Limit I (Non-Latching) (Latching) IUV V Pin IOV IOV(LS) I DCMAX (78%) Maximum Duty Cycle I VBG Pin Voltage -250 -200 -150 -100 -50 0 25 50 75 100 125 336 I X and V Pins (Y, E, L and M Packages) and M Pin (P and G Packages) Current (μA) Note: This figure provides idealized functional characteristics with typical performance values. Please refer to the parametric table and typical performance characteristics sections of the data sheet for measured data. For a detailed description of each functional pin operation refer to the Functional Description section of the data sheet. PI-4646-071708 Figure 12. MULTI-FUNCTION (P and G package). VOLTAGE MONITOR and EXTERNAL CURRENT LIMIT (Y, E/L and M package) Pin Characteristics. The circuit examples shown in Figures 41, 42 and 43 show a simple method for implementing the primary sensed overvoltage protection. During a fault condition resulting from loss of feedback, output voltage will rapidly rise above the nominal voltage. The increase in output voltage will also result in an increase in the voltage at the output of the bias winding. A voltage at the output of the bias winding that exceeds of the sum of the voltage rating of the Zener diode connected from the bias winding output to the V-pin (or M-pin) and V-pin (or M-pin) voltage, will cause a current in excess of IV or IM to be injected into the V-pin (or M-pin), which will trigger the OVP feature. The primary sensed OVP protection circuit shown in Figures 41, 42 and 43 is triggered by a significant rise in output voltage (and therefore bias winding voltage). If the power supply is operating under heavy load or low input line conditions when an open loop occurs, the output voltage may not rise significantly. Under these conditions, a latching shutdown will not occur until load or line conditions change. Nevertheless, the operation provides the desired protection by preventing significant rise in the output voltage when the line or load conditions do change. Primary side OVP protection with the TOPSwitch-HX in a typical application will prevent a nominal 12 V output from rising above approximately 20 V under open loop conditions. If greater accuracy is required, a secondary sensed OVP circuit is recommended. 12 Rev. F 01/09 www.powerint.com TOP252-262 Line Feed-Forward with DCMAX Reduction The same resistor used for UV and OV also implements line voltage feed-forward, which minimizes output line ripple and reduces power supply output sensitivity to line transients. Note that for the same CONTROL pin current, higher line voltage results in smaller operating duty cycle. As an added feature, the maximum duty cycle DCMAX is also reduced from 78% (typical) at a voltage slightly lower than the UV threshold to 36% (typical) at the OV threshold. DCMAX of 36% at high line was chosen to ensure that the power capability of the TOPSwitch-HX is not restricted by this feature under normal operation. TOPSwitch-HX provides a better fit to the ideal feed-forward by using two reduction slopes: -1% per μA for all bus voltage less than 195 V (typical for 4 MΩ line impedance) and -0.25% per μ A for all bus voltage more than 195 V. This dual slope line feed-forward improves the line ripple rejection significantly compared with the TOPSwitch-GX. Remote ON/OFF TOPSwitch-HX can be turned on or off by controlling the current into the VOLTAGE-MONITOR pin or out from the EXTERNAL CURRENT LIMIT pin (Y, E/L and M packages) and into or out from the MULTI-FUNCTION pin (P and G package, see Figure 12). In addition, the VOLTAGE-MONITOR pin has a 1 V threshold comparator connected at its input. This voltage threshold can also be used to perform remote ON/OFF control. When a signal is received at the VOLTAGE-MONITOR pin or the EXTERNAL CURRENT LIMIT pin (Y, E/L and M packages) or the MULTI-FUNCTION pin (P and G package) to disable the output through any of the pin functions such as OV, UV and remote ON/OFF, TOPSwitch-HX always completes its current switching cycle before the output is forced off. As seen above, the remote ON/OFF feature can also be used as a standby or power switch to turn off the TOPSwitch-HX and keep it in a very low power consumption state for indefinitely long periods. If the TOPSwitch-HX is held in remote off state for long enough time to allow the CONTROL pin to discharge to the internal supply undervoltage threshold of 4.8 V (approximately 32 ms for a 47 μF CONTROL pin capacitance), the CONTROL pin goes into the hysteretic mode of regulation. In this mode, the CONTROL pin goes through alternate charge and discharge cycles between 4.8 V and 5.8 V (see CONTROL pin operation section above) and runs entirely off the high voltage DC input, but with very low power consumption (160 mW typical at 230 VAC with M or X pins open). When the TOPSwitch-HX is remotely turned on after entering this mode, it will initiate a normal start-up sequence with soft-start the next time the CONTROL pin reaches 5.8 V. In the worst case, the delay from remote on to start-up can be equal to the full discharge/charge cycle time of the CONTROL pin, which is approximately 125 ms for a 47 μF CONTROL pin capacitor. This reduced consumption remote off mode can eliminate expensive and unreliable in-line mechanical switches. It also allows for microprocessor controlled turn-on and turn-off sequences that may be required in certain applications such as inkjet and laser printers. Soft-Start The 17 ms soft-start sweeps the peak drain current and switching frequency linearly from minimum to maximum value by operating through the low frequency PWM mode and the variable frequency mode before entering the full frequency mode. In addition to start-up, soft-start is also activated at each restart attempt during auto-restart and when restarting after being in hysteretic regulation of CONTROL pin voltage (VC), due to remote OFF or thermal shutdown conditions. This effectively minimizes current and voltage stresses on the output MOSFET, the clamp circuit and the output rectifier during startup. This feature also helps minimize output overshoot and prevents saturation of the transformer during start-up. Shutdown/Auto-Restart To minimize TOPSwitch-HX power dissipation under fault conditions, the shutdown/auto-restart circuit turns the power supply on and off at an auto-restart duty cycle of typically 2% if an out of regulation condition persists. Loss of regulation interrupts the external current into the CONTROL pin. VC regulation changes from shunt mode to the hysteretic autorestart mode as described in CONTROL pin operation section. When the fault condition is removed, the power supply output becomes regulated, VC regulation returns to shunt mode, and normal operation of the power supply resumes. Hysteretic Over-Temperature Protection Temperature protection is provided by a precision analog circuit that turns the output MOSFET off when the junction temperature exceeds the thermal shutdown temperature (142 °C typical). When the junction temperature cools to below the lower hysteretic temperature point, normal operation resumes, thus providing automatic recovery. A large hysteresis of 75 °C (typical) is provided to prevent overheating of the PC board due to a continuous fault condition. VC is regulated in hysteretic mode, and a 4.8 V to 5.8 V (typical) triangular waveform is present on the CONTROL pin while in thermal shutdown. Bandgap Reference All critical TOPSwitch-HX internal voltages are derived from a temperature-compensated bandgap reference. This voltage reference is used to generate all other internal current references, which are trimmed to accurately set the switching frequency, MOSFET gate drive current, current limit, and the line OV/UV/OVP thresholds. TOPSwitch-HX has improved circuitry to maintain all of the above critical parameters within very tight absolute and temperature tolerances. High-Voltage Bias Current Source This high-voltage current source biases TOPSwitch-HX from the DRAIN pin and charges the CONTROL pin external capacitance during start-up or hysteretic operation. Hysteretic operation occurs during auto-restart, remote OFF and over-temperature shutdown. In this mode of operation, the current source is switched on and off, with an effective duty cycle of approximately 35%. This duty cycle is determined by the ratio of CONTROL pin charge (IC) and discharge currents (ICD1 and ICD2). This current source is turned off during normal operation when the output MOSFET is switching. The effect of the current source switching will be seen on the DRAIN voltage waveform as small disturbances and is normal. 13 www.powerint.com Rev. F 01/09 TOP252-262 Y, E/L and M Package CONTROL (C) 200 A TOPSwitch-HX (Negative Current Sense - ON/OFF, Current Limit Adjustment) VBG + VT EXTERNAL CURRENT LIMIT (X) VOLTAGE MONITOR (V) VREF 1V (Positive Current Sense - Undervoltage, Overvoltage, ON/OFF, Maximum Duty Cycle Reduction, Output Overvoltage Protection) 400 A (Voltage Sense) PI-4714-071408 Figure 13a. VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pin Input Simplified Schematic. P and G Package CONTROL (C) 200 A TOPSwitch-HX (Negative Current Sense - ON/OFF, Current Limit Adjustment) VBG + VT MULTI-FUNCTION (M) VREF (Positive Current Sense - Undervoltage, Overvoltage, Maximum Duty Cycle Reduction, Output Overvoltage Protection) 400 A PI-4715-071408 Figure 13b. MULTI-FUNCTION (M) Pin Input Simplified Schematic. 14 Rev. F 01/09 www.powerint.com TOP252-262 Typical Uses of FREQUENCY (F) Pin + + DC Input Voltage D CONTROL C S F DC Input Voltage D CONTROL C S F PI-2654-071700 PI-2655-071700 Figure 14. Full Frequency Operation (132 kHz). Figure 15. Half Frequency Operation (66 kHz). 15 www.powerint.com Rev. F 01/09 TOP252-262 Typical Uses of VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pins TOP252-258M TOP254-258Y + D C X V + TOP259-261Y S S S S S VXCS F D DC Input Voltage D V CONTROL D SC DC Input Voltage D C SD VXCSG D V CONTROL C S X F PI-4716-020508 C CS D - - S X G PI-4984-020708 Figure 16a. Three Terminal Operation (VOLTAGE MONITOR and EXTERNAL CURRENT LIMIT Features Disabled. FREQUENCY Pin Tied to SOURCE or CONTROL Pin) for TOP254-258 Y Packages. Figure 16b. Three Terminal Operation (VOLTAGE MONITOR and EXTERNAL CURRENT LIMIT Features Disabled for TOP259-261 Y Packages. + eSIP L Package eSIP E Package + VUV = IUV × RLS + VV (IV = IUV) VOV = IOV × RLS + VV (IV = IOV) For RLS = 4 M VUV = 102.8 VDC VOV = 451 VDC DCMAX@100 VDC = 76% DCMAX@375 VDC = 41% D V CONTROL VXC FS D VXC FS D RLS DC Input Voltage 4M DC Input Voltage D V CONTROL C SD C SD C S X F PI-4956-071708 C S PI-4717-120307 - - Figure 16c. Three Terminal Operation (VOLTAGE MONITOR and EXTERNAL CURRENT LIMIT Features Disabled. FREQUENCY Pin Tied to SOURCE or CONTROL Pin) for TOP252-262 L and E Packages. Figure 17. Line-Sensing for Undervoltage, Overvoltage and Line Feed-Forward. + VUV = IUV × RLS + VV (IV = IUV) VOV = IOV × RLS + VV (IV = IOV) For RLS = 4 M VUV = 102.8 VDC VOV = 451 VDC Sense Output Voltage DCMAX @ 100 VDC = 76% DCMAX @ 375 VDC = 41% C S PI-4756-121007 + VUV = IUV × RLS + VV (IV = IUV) VOV = IOV × RLS + VV (IV = IOV) For RLS = 4 M VUV = 102.8 VDC VOV = 451 VDC Sense Output Voltage RLS DC Input Voltage D 4M RLS DC Input Voltage D 4M VROVP ROVP DCMAX @ 100 VDC = 76% DCMAX @ 375 VDC = 41% V CONTROL V CONTROL Reset 10 k QR C S ROVP >3k - - PI-4719-120307 Figure 18. Line-Sensing for Undervoltage, Overvoltage, Line Feed-Forward and Latched Output Overvoltage Protection. Figure 19. Line-Sensing for Undervoltage, Overvoltage, Line Feed-Forward and Hysteretic Output Overvoltage Protection. 16 Rev. F 01/09 www.powerint.com TOP252-262 Typical Uses of VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pins (cont.) + 4M VUV = RLS × IUV + VV (IV = IUV) For Values Shown VUV = 103.8 VDC RLS + 4M VOV = IOV × RLS + VV (IV = IOV) For Values Shown VOV = 457.2 VDC RLS DC Input Voltage D DC Input Voltage D 40 k V CONTROL 55 k V CONTROL 1N4148 C 6.2 V C S PI-4720-120307 - - S PI-4721-120307 Figure 20. Line Sensing for Undervoltage Only (Overvoltage Disabled). Figure 21. Line-Sensing for Overvoltage Only (Undervoltage Disabled). Maximum Duty Cycle Reduced at Low Line and Further Reduction with Increasing Line Voltage. + For RIL = 12 k ILIMIT = 61% For RIL = 19 k ILIMIT = 37% + RLS 2.5 M ILIMIT = 100% @ 100 VDC ILIMIT = 53% @ 300 VDC TOP259-261YN would use the G pin as the return for RIL. D CONTROL DC Input Voltage D CONTROL See Figure 55b for other resistor values (RIL). C DC Input Voltage C S X RIL TOP259-261YN would use the G pin as the return for RIL. S X RIL 6k PI-4723-011008 PI-4722-021308 - Figure 22. External Set Current Limit. Figure 23. Current Limit Reduction with Line Voltage. + QR can be an optocoupler output or can be replaced by a manual switch. TOP259-261YN would use the G pin as the return for QR. CONTROL + QR can be an optocoupler output or can be replaced by a manual switch. For RIL = 12 k DC Input Voltage D DC Input Voltage ILIMIT = 61% D CONTROL For RIL = 19 k C C S QR X ON/OFF 47 K PI-2625-011008 ILIMIT = 37% TOP259-261YN would use the G pin as the return for QR. S X RIL - - QR 16 k ON/OFF PI-4724-011008 Figure 24. Active-on (Fail Safe) Remote ON/OFF. Figure 25. Active-on Remote ON/OFF with Externally Set Current Limit. 17 www.powerint.com Rev. F 01/09 TOP252-262 Typical Uses of VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pins (cont.) PI-4726-021308 + RLS 4M VUV = IUV × RLS + VV (IV = IUV) VOV = IOV × RLS + VV (IV = IoV) DCMAX@100 VDC = 76% DCMAX@375 VDC = 41% QR can be an optocoupler output or can be replaced by a manual switch. C + RLS 4M VUV = IUV x RLS + VV (IV = IUV) VOV = IOV x RLS + VV (IV = IoV) For RLS = 4 M VUV = 102.8 VDC VOV = 451 VDC DCMAX @ 100 VDC = 76% DCMAX @ 375 VDC = 41% C DC Input Voltage D V CONTROL DC Input Voltage D V CONTROL TOP259-261YN would use the G pin as the return for QR. For RIL = 12 k ILIMIT = 61% S X RIL QR 16 k - ON/OFF PI-4725-011008 TOP259-261YN would use the G pin as the return for RIL. S X For RIL = 12 k ILIMIT = 61% See Figure 55b for other resistor values (RIL) to select different ILIMIT values. - RIL 12 k Figure 26. Active-on Remote ON/OFF with Line-Sense and External Current Limit. Figure 27. Line Sensing and Externally Set Current Limit. + VUV = IUV × RLS + VV (IV = IUV) VOV = IOV × RLS + VV (IV = IOV) For RLS = 4 M VUV = 102.8 VDC VOV = 451 VDC Sense Output Voltage DCMAX @ 100 VDC = 76% DCMAX @ 375 VDC = 41% C S PI-4756-121007 RLS DC Input Voltage D 4M V CONTROL Reset 10 k QR - Figure 28. Line-Sensing for Undervoltage, Overvoltage, Line Feed-Forward and Latched Output Overvoltage Protection with Device Reset. Typical Uses of MULTI-FUNCTION (M) Pin + D C M + VUV = IUV × RLS + VM (IM = IUV) VOV = IOV × RLS + VM (IM = IOV) RLS 4M For RLS = 4 M VUV = 102.8 VDC VOV = 451 VDC DCMAX @ 100 VDC = 76% DCMAX @ 375 VDC = 41% D M CONTROL DC Input Voltage D M CONTROL D S S S S DC Input Voltage S C C S PI-4727-061207 C S PI-4728-120307 - - Figure 29. Three Terminal Operation (MULTI-FUNCTION Features Disabled). Figure 30. Line Sensing for Undervoltage, Overvoltage and Line Feed-Forward. 18 Rev. F 01/09 www.powerint.com TOP252-262 Typical Uses of MULTI-FUNCTION (M) Pin (cont.) VUV = IUV × RLS + VM (IM = IUV) VOV = IOV × RLS + VM (IM = IOV) For RLS = 4 M VUV = 102.8 VDC VOV = 451 VDC Sense Output Voltage + VUV = IUV × RLS + VM (IM = IUV) VOV = IOV × RLS + VM (IM = IOV) For RLS = 4 M VUV = 102.8 VDC VOV = 451 VDC Sense Output Voltage DCMAX @ 100 VDC = 76% DCMAX @ 375 VDC = 41% C S PI-4729-120307 + RLS DC Input Voltage D 4M RLS DC Input Voltage D 4M VROVP ROVP M CONTROL M CONTROL DCMAX @ 100 VDC = 76% DCMAX @ 375 VDC = 41% C ROVP >3k - - S PI-4730-120307 Figure 31. Line Sensing for Undervoltage, Overvoltage, Line Feed-Forward and Latched Output Overvoltage Protection. Figure 32. Line Sensing for Undervoltage, Overvoltage, Line Feed-Forward and Hysteretic Output Overvoltage Protection. + 4M VUV = RLS × IUV + VM (IM = IUV) For Values Shown VUV = 103.8 VDC RLS + 4M RLS DC Input Voltage D VOV = IOV × RLS + VM (IM = IOV) For Values Shown VOV = 457.2 VDC DC Input Voltage D 40 k M CONTROL 55 k 1N4148 M CONTROL 6.2 V C S PI-4731-120307 C S PI-4732-120307 - - Figure 33. Line Sensing for Undervoltage Only (Overvoltage Disabled). Figure 34. Line Sensing for Overvoltage Only (Undervoltage Disabled). Maximum Duty Cycle Reduced at Low Line and Further Reduction with Increasing Line Voltage. + For RIL = 12 k ILIMIT = 61% + ILIMIT = 100% @ 100 VDC ILIMIT = 53% @ 300 VDC RLS For RIL = 19 k ILIMIT = 37% 2.5 M DC Input Voltage D M CONTROL See Figures 55b for other resistor values (RIL) to select different ILIMIT values. DC Input Voltage D M CONTROL RIL C S PI-4733-021308 RIL 6k C S PI-4734-092107 - - Figure 35. Externally Set Current Limit (Not Normally Required – See M Pin Operation Description). Figure 36. Current Limit Reduction with Line Voltage (Not Normally Required – See M Pin Operation Description). 19 www.powerint.com Rev. F 01/09 TOP252-262 Typical Uses of MULTI-FUNCTION (M) Pin (cont.) + QR can be an optocoupler output or can be replaced by a manual switch. + QR can be an optocoupler output or can be replaced by a manual switch. For RIL = 12 k DC Input Voltage D M CONTROL DC Input Voltage RIL C D M CONTROL ILIMIT = 61% For RIL = 19 k ILIMIT = 37% C QR ON/OFF ON/OFF 47 k - S PI-2519-040501 16 k QR S PI-4735-092107 - Figure 37. Active-on (Fail Safe) Remote ON/OFF. Figure 38. Active-on Remote ON/OFF with Externally Set Current Limit (see M Pin Operation Description). + QR can be an optocoupler output or can be replaced by a manual switch. + VUV = IUV × RLS + VM (IM = IUV) VOV = IOV × RLS + VM (IM = IOV) For RLS = 4 M VUV = 102.8 VDC VOV = 451 VDC Sense Output Voltage DCMAX @ 100 VDC = 76% DCMAX @ 375 VDC = 41% C S PI-4757-120307 RLS DC Input Voltage ON/OFF 7k QR RMC D M CONTROL 4M DC Input Voltage 24 k RMC = 2RIL Reset 10 k QR D M CONTROL RIL 12 k S C - PI-4736-060607 Figure 39. Active-off Remote ON/OFF with Externally Set Current Limit (see M Pin Operation Description). Figure 40. Line-Sensing for Undervoltage, Overvoltage, Line Feed-Forward and Latched Output Overvoltage Protection with Device Reset. 20 Rev. F 01/09 www.powerint.com TOP252-262 Application Examples A High Efficiency, 35 W, Dual Output - Universal Input Power Supply The circuit in Figure 41 takes advantage of several of the TOPSwitch-HX features to reduce system cost and power supply size and to improve efficiency. This design delivers 35 W total continuous output power from a 90 VAC to 265 VAC input at an ambient of 50 ºC in an open frame configuration. A nominal efficiency of 84% at full load is achieved using TOP258P. With a DIP-8 package, this design provides 35 W continuous output power using only the copper area on the circuit board underneath the part as a heat sink. The different operating modes of the TOPSwitch-HX provide significant improvement in the no-load, standby, and light load performance of the power supply as compared to the previous generations of the TOPSwitch. Resistors R3 and R4 provide line sensing, setting line UV at 100 VDC and line OV at 450 VDC. Diode D5, together with resistors R6, R7, capacitor C6 and TVS VR1, forms a clamp network that limits the drain voltage of the TOPSwitch after the integrated MOSFET turns off. TVS VR1 provides a defined maximum clamp voltage and typically only conducts during fault conditions such as overload. This allows the RCD clamp (R6, R7, C6 and D5) to be sized for normal operation, thereby maximizing efficiency at light load. Should the feedback circuit fail, the output of the power supply may exceed regulation limits. This increased voltage at output will also result in an increased voltage at the output of the bias C6 3.9 nF 1 kV C7 2.2 nF 250 VAC winding. Zener VR2 will break down and current will flow into the “M” pin of the TOPSwitch initiating a hysteretic overvoltage protection with automatic restart attempts. Resistor R5 will limit the current into the M pin to < 336 μ A, thus setting hysteretic OVP. If latching OVP is desired, the value of R5 can be reduced to 20 Ω. The output voltage is controlled using the amplifier TL431. Diode D9, capacitor C20 and resistor R16 form the soft finish circuit. At startup, capacitor C20 is discharged. As the output voltage starts rising, current flows through the optocoupler diode inside U2A, resistor R13 and diode D9 to charge capacitor C20. This provides feedback to the circuit on the primary side. The current in the optocoupler diode U2A gradually decreases as the capacitor C20 becomes charged and the control amplifier IC U3 becomes operational. This ensures that the output voltage increases gradually and settles to the final value without any overshoot. Resistor R16 ensures that the capacitor C20 is maintained charged at all times after startup, which effectively isolates C20 from the feedback circuit after startup. Capacitor C20 discharges through R16 when the supply shuts down. Resistors R20, R21 and R18 form a voltage divider network. The output of this divider network is primarily dependent on the divider circuit formed using R20 and R21 and will vary to some extent for changes in voltage at the 15 V output due to the connection of resistor R18 to the output of the divider network. Resistor R19 and Zener VR3 improve cross regulation in case only the 5 V output is loaded, which results in the 15 V output operating at the higher end of the specification. R11 33 C12 470 pF 100 V C13 680 F 25 V R12 33 C14 C15 680 F L2 220 F 25 V 3.3 H 25 V L3 3.3 H C18 220 F 10 V D1 1N4937 D2 1N4007 R6 22 k 2W T1 2 EER28 7 VR1 P6KE200A 3 R7 20 1/2 W D5 FR106 11 C16 470 pF 100 V D7 SB560 +12 V, 2A RTN +5 V, 2.2 A 4 9 6 D8 SB530 RTN C10 10 F 50 V C17 2200 F 10 V C11 2.2 nF 250 VAC VR3 BZX55B8V2 8.2 V 2% D3 1N4937 L1 6.8 mH D4 1N4007 R3 2.0 M R4 2.0 M C4 100 F 400 V R10 D6 FR106 4.7 5 R19 10 R1 1M R2 1M R13 330 R5 5.1 k VR2 1N5250B 20 V R14 22 C19 1.0 F 50 V R15 1k F1 3.15 A L E N 90 - 265 VAC C3 220 nF 275 VAC RT1 10 O t D TOPSwitch-HX U1 CONTROL TOP258PN C M R8 6.8 C9 47 F 16 V U2B PS25011-H-A R16 10 k U2A PS25011-H-A R17 10 k R18 196 k 1% R20 12.4 k 1% S C8 100 nF 50 V D9 1N4148 C21 220 nF 50 V C20 10 F 50 V U3 TL431 2% R21 10 k 1% PI-4747-020508 Figure 41. 35 W Dual Output Power Supply using TOP258PN. 21 www.powerint.com Rev. F 01/09 TOP252-262 A High Efficiency, 150 W, 250 – 380 VDC Input Power Supply The circuit shown in Figure 42 delivers 150 W (19 V @ 7.7 A) at 84% efficiency using a TOP258Y from a 250 VDC to 380 VDC input. A DC input is shown, as typically at this power level a power factor correction stage would precede this supply, providing the DC input. Capacitor C1 provides local decoupling, necessary when the supply is remote from the main PFC output capacitor. The flyback topology is still usable at this power level due to the high output voltage, keeping the secondary peak currents low enough so that the output diode and capacitors are reasonably sized. In this example, the TOP258YN is at the upper limit of its power capability. Resistors R3, R6 and R7 provide output power limiting, maintaining relatively constant overload power with input voltage. Line sensing is implemented by connecting a 4 MΩ resistor from the V pin to the DC rail. Resistors R4 and R5 together form the 4 MΩ line sense resistor. If the DC input rail rises above 450 VDC, then TOPSwitch-HX will stop switching until the voltage returns to normal, preventing device damage. Due to the high primary current, a low leakage inductance transformer is essential. Therefore, a sandwich winding with a copper foil secondary was used. Even with this technique, the leakage inductance energy is beyond the power capability of a simple Zener clamp. Therefore, R1, R2 and C3 are added in parallel to VR1 and VR3, two series TVS diodes being used to reduce dissipation. During normal operation, very little power is dissipated by VR1 and VR3, the leakage energy instead being dissipated by R1 and R2. However, VR1 and VR3 are essential to limit the peak drain voltage during start-up and/or overload conditions to below the 700 V rating of the TOPSwitch-HX MOSFET. The schematic shows an additional turn-off snubber circuit consisting of R20, R21, R22, D5 and C18. This reduces turn-off losses in the TOPSwitch-HX. The secondary is rectified and smoothed by D2, D3 and C5, C6, C7 and C8. Two windings are used and rectified with separate diodes D2 and D3 to limit diode dissipation. Four capacitors are used to ensure their maximum ripple current specification is not exceeded. Inductor L1 and capacitors C15 and C16 provide switching noise filtering. Output voltage is controlled using a TL431 reference IC and R15, R16 and R17 to form a potential divider to sense the output voltage. Resistor R12 and R24 together limit the optocoupler LED current and set overall control loop DC gain. Control loop compensation is achieved using components C12, C13, C20 and R13. Diode D6, resistor R23 and capacitor C19 form a soft finish network. This feeds current into the control pin prior to output regulation, preventing output voltage overshoot and ensuring startup under low line, full load conditions. Sufficient heat sinking is required to keep the TOPSwitch-HX device below 110 °C when operating under full load, low line and maximum ambient temperature. Airflow may also be required if a large heat sink area is not acceptable. 250 - 380 VDC F1 4A RT1 O 5t R2 R1 68 k 68 k 2W 2W C3 4.7 nF 1 kV D1 BYV26C 4 VR1, VR3 P6KE100A C1 22 F 400 V 1 2.2 nF 250 VAC C4 R14 22 0.5 W C14 47 pF 1 kV C5-C8 820 F 25 V L1 3.3 H C15-C16 820 F 25 V +19 V, 7.7 A 13,14 D2 MBR20100CT 11 12 D3 MBR20100CT R6 4.7 M R4 2.0 M R7 4.7 M R5 2.0 RTN 9,10 7 D4 1N4148 5 T1 EI35 C9 10 F 50 V R23 15 k 0.125 W U2 PC817A R11 C12 1k 4.7 nF 0.125 W 50 V U2 PC817B R10 6.8 C10 47 F 10 V C19 10 F 50 V R20 1.5 k 2W R18 22 0.5 W R8 4.7 C17 47 pF 1 kV R12 240 0.125 W C20 1.0 F 50 V R21 1.5 k 2W D5 1N4937 R19 4.7 TOPSwitch-HX U1 TOP258YN C VR2 1N5258B 36 V R24 30 0.125 W R16 31.6 k 1% R17 562 1% C13 100 nF 50 V D V CONTROL R22 1.5 k 2W S X F R3 8.06 k 1% C18 120 pF 1 kV C11 100 nF 50 V D6 1N4148 U3 TL431 2% R13 56 k 0.125 W R15 4.75 k 1% PI-4795-092007 Figure 42. 150 W, 19 V Power Supply using TOP258YN. 22 Rev. F 01/09 www.powerint.com TOP252-262 A High Efficiency, 20 W continuous – 80 W Peak, Universal Input Power Supply The circuit shown in Figure 43 takes advantage of several of TOPSwitch-HX features to reduce system cost and power supply size and to improve power supply efficiency while delivering significant peak power for a short duration. This design delivers continuous 20 W and peak 80 W at 32 V from an 90 VAC to 264 VAC input. A nominal efficiency of 82% at full load is achieved using TOP258MN. The M-package part has an optimized current limit to enable design of power supplies capable of delivering high power for a short duration. Resistor R12 sets the current limit of the part. Resistors R11 and R14 provide line feed forward information that reduces the current limit with increasing DC bus voltage, thereby maintaining a constant overload power level with increasing line voltage. Resistors R1 and R2 implement the line undervoltage and overvoltage function and also provide feed forward compensation for reducing line frequency ripple at the output. The overvoltage feature inhibits TOPSwitch-HX switching during a line surge extending the high voltage withstand to 700 V without device damage. The snubber circuit comprising of VR7, R17, R25, C5 and D2 limits the maximum drain voltage and dissipates energy stored in the leakage inductance of transformer T1. This clamp configuration maximizes energy efficiency by preventing C5 from discharging below the value of VR7 during the lower frequency operating modes of TOPSwitch-HX. Resistor R25 damps high frequency ringing for reduced EMI. A combined output overvoltage and over power protection circuit is provided via the latching shutdown feature of TOPSwitch-HX and R20, C9, R22 and VR5. Should the bias winding output voltage across C13 rise due to output overload or an open loop fault (opto coupler failure), then VR5 conducts triggering the latching shutdown. To prevent false triggering due to short duration overload, a delay is provided by R20, R22 and C9. To reset the supply following a latching shutdown, the V pin must fall below the reset threshold. To prevent the long reset delay associated with the input capacitor discharging, a fast AC reset circuit is used. The AC input is rectified and filtered by D13 and C30. While the AC supply is present, Q3 is on and Q1 is off, allowing normal device operation. However when AC is removed, Q1 pulls down the V pin and resets the latch. The supply will then return to normal operation when AC is again applied. Transistor Q2 provides an additional lower UV threshold to the level programmed via R1, R2 and the V pin. At low input AC voltage, Q2 turns off, allowing the X pin to float and thereby disabling switching. A simple feedback circuit automatically regulates the output voltage. Zener VR3 sets the output voltage together with the voltage drop across series resistor R8, which sets the DC gain of the circuit. Resistors R10 and C28 provide a phase boost to improve loop bandwidth. Diodes D6 and D7 are low-loss Schottky rectifiers, and capacitor C20 is the output filter capacitor. Inductor L3 is a common mode choke to limit radiated EMI when long output cables are used and the output return is connected to safety earth ground. Example applications where this occurs include PC peripherals, such as inkjet printers. C8 1 nF 250 VAC R19 C26 68 100 pF 0.5 W 1 kV C20 330 F 50 V L2 3.3 H D8 1N4007 D9 1N4007 VR7 BZY97C150 150 V R11 3.6 M R17 1k 0.5 W R25 100 2 9 5 3 1 10 C31 22 F 50 V L3 32 V 625 mA, 2.5 APK D6-D7 STPS3150 47 H C29 220 nF 50 V RTN t D11 1N4007 D10 1N4007 o RT1 10 C3 120 F 400 V R1 2M NC 4 C5 10 nF 1 kV T1 EF25 C13 10 F 50 V D5 LL4148 C10 1 nF 250 VAC R10 56 C28 330 nF 50 V L1 5.3 mH D13 1N4007 R23 1M R24 1M R3 2M F1 3.15 A R4 2M 90 - 264 VAC R15 1k C30 100 nF 400 V R26 68 k R21 1M 0.125 W R2 2M R14 3.6 M D2 FR107 R8 1.5 k C1 220 nF 275 VAC D V CONTROL C VR5 1N5250B 20 V R22 2M C9 1F 100 V R20 130 k U2A PC817D VR3 1N5255B 28 V R9 2k PI-4833-092007 S X R6 6.8 Q1 2N3904 Q3 2N3904 R18 39 k R12 7.5 k 1% Q2 2N3904 TOPSwitch-HX U4 TOP258MN C6 100 nF 50 V C7 47 F 16 V Figure 43. 20 W Continuous, 80 W Peak, Universal Input Power Supply using TOP258MN. 23 www.powerint.com Rev. F 01/09 TOP252-262 A High Efficiency, 65 W, Universal Input Power Supply The circuit shown in Figure 44 delivers 65 W (19 V @ 3.42 A) at 88% efficiency using a TOP260EN operating over an input voltage range of 90 VAC to 265 VAC. Capacitors C1 and C6 and inductors L1 and L2 provide common mode and differential mode EMI filtering. Capacitor C2 is the bulk filter capacitor that ensures low ripple DC input to the flyback converter stage. Capacitor C4 provides decoupling for switching currents reducing differential mode EMI. In this example, the TOP260EN is used at reduced current limit to improve efficiency. Resistors R5, R6 and R7 provide power limiting, maintaining relatively constant overload power with input voltage. Line sensing is implemented by connecting a 4 MΩ impedance from the V pin to the DC rail. Resistors R3 and R4 together form the 4 MΩ line sense resistor. If the DC input rail rises above 450 VDC, then TOPSwitch-HX will stop switching until the voltage returns to normal, preventing device damage. This circuit features a high efficiency clamp network consisting of diode D1, zener VR1, capacitor C5 together with resistors R8 and R9. The snubber clamp is used to dissipate the energy of the leakage reactance of the transformer. At light load levels, very little power is dissipated by VR1 improving efficiency as compared to a conventional RCD clamp network. The secondary output from the transformer is rectified by diode D2 and filtered by capacitors C13 and C14. Ferrite Bead L3 and capacitors C15 form a second stage filter and effectively reduce the switching noise to the output. Output voltage is controlled using a LM431 reference IC. Resistor R19 and R20 form a potential divider to sense the output voltage. Resistor R16 limits the optocoupler LED current and sets the overall control loop DC gain. Control loop compensation is achieved using C18 and R21. The components connected to the control pin on the primary side C8, C9 and R15 set the low frequency pole and zero to further shape the control loop response. Capacitor C17 provides a soft finish during startup. Optocoupler U2 is used for isolation of the feedback signal. Diode D4 and capacitor C10 form the bias winding rectifier and filter. Should the feedback loop break due to a defective component, a rising bias winding voltage will cause the zener VR2 to break down and trigger the over voltage protection which will inhibit switching. An optional secondary side over voltage protection feature which offers higher precision (as compared to sensing via the bias winding) is implemented using VR3, R18 and U3. Excess voltage at the output will cause current to flow through the optocoupler U3 LED which in turn will inject current in the V-pin through resistor R13, thereby triggering the over voltage protection feature. C6 2.2 nF 250 VAC C5 VR1 2.2 nF BZY97C180 1 kV 180 V 3KBP08M BR1 R8 100 R3 2.0 M R5 5.1 M R9 1k 6 3 D1 DL4937 2 L1 12 mH C2 120 F 400 V D4 BAV19WS R4 2.0 M R2 2.2 M R6 6.8 M D5 BAV19WS C4 100 nF 400 V D3 BAV19WS TOPSwitch-HX U1 V TOP260EN CONTROL C C12 1 nF R16 100 V 33 C13 C14 470 F 470 F 25 V 25 V D2 MBR20100CT RTN C10 R10 22 F 50 V 73.2 k VR2 1N5248B 18 V C11 100 nF 50 V R11 2M U3B PC357A U3A PC357A U2B LTY817C U2A LTY817C VR3 BZX79-C22 22 V L3 Ferrite Bead C15 47 F 25 V T1 4 RM10 FL1 19 V, 3.42 A 5 FL2 R1 2.2 M C7 100 nF 25 V R12 5.1 k R16 680 R18 47 F1 4A L E N 90 - 265 VAC C1 330 nF 275 VAC D R13 5.1 R14 100 R15 6.8 C9 47 F 16 V D6 1N4148 C18 100 nF R19 68.1 k S X F C3 470 pF 250 VAC L2 Ferrite Bead R7 15 k 1% C8 100 nF 50 V C16 1F 50 V C17 33 F 35 V U4 LM431 2% R21 1k R20 10 k PI-4998-021408 Figure 44. 65 W, 19 V Power Supply Using TOP260EN. 24 Rev. F 01/09 www.powerint.com TOP252-262 Key Application Considerations TOPSwitch-HX vs. TOPSwitch-GX Table 4 compares the features and performance differences between TOPSwitch-HX and TOPSwitch-GX. Many of the new TOPSwitch-HX vs. TOPSwitch-GX Function EcoSmart TOPSwitch-GX TOPSwitch-HX TOPSwitch-HX Advantages • Improved efficiency over load (e.g. at 25% load features eliminate the need for additional discrete components. Other features increase the robustness of design, allowing cost savings in the transformer and other power components. Linear frequency reduction to Multi-mode operation with 30 kHz (@ 132 kHz) for linear frequency reduction to duty cycles < 10% 30 kHz (@ 132 kHz) and multi-cycle modulation (virtually no audible noise) point) • Improved standby efficiency • Improved no-load consumption Output Overvoltage Protection (OVP) Not available User programmable primary or secondary hysteretic or latching OVP Dual slope reduction with lower, more accurate onset point 66 kHz • Protects power supply output during open loop fault • Maximum design flexibility Line Feed-Forward with Duty Cycle Reduction Linear reduction • Improved line ripple rejection • Smaller DC bus capacitor Switching Frequency DIP-8 Package 132 kHz • Increased output power for given MOSFET size due to higher efficiency 3.0 Ω (TOP246P) 1.8 Ω (TOP258P) Lowest MOSFET On Resistance in DIP-8 Package I2f Trimming • Increased output power in designs without external heatsink Not available -10% / +20% • Increased output power for given core size • Reduced over-load power Auto-restart Duty Cycle 5.6% 2% • Reduced delivered average output power during open loop faults Frequency Jitter ±4 kHz @ 132 kHz ±2 kHz @ 66 kHz 130 °C to 150 °C 30%-100% of ILIMIT ±5 kHz @ 132 kHz ±2.5 kHz @ 66 kHz 135 °C to 150 °C • Reduced EMI filter cost Thermal Shutdown External Current Limit • Increased design margin 30%-100% of ILIMIT, additional • Reduced tolerances when current limit is set trim at 0.7 × ILIMIT externally 25 μA (4 MΩ sense impedance) Line UV Detection Threshold 50 μA (2 MΩ sense impedance) • Reduced dissipation for lower no-load consumption Soft-Start 10 ms duty cycle and current 17 ms sweep through multilimit ramp mode characteristic • Reduced peak current and voltage component stress at startup • Smooth output voltage rise Table 4. Comparison Between TOPSwitch-GX and TOPSwitch-HX. 25 www.powerint.com Rev. F 01/09 TOP252-262 TOPSwitch-HX Design Considerations Power Table The data sheet power table (Table 1) represents the maximum practical continuous output power based on the following conditions: 1. 12 V output. 2. Schottky or high efficiency output diode. 3. 135 V reflected voltage (VOR) and efficiency estimates. 4. A 100 VDC minimum for 85-265 VAC and 250 VDC minimum for 230 VAC. 5. Sufficient heat sinking to keep device temperature ≤100 °C. 6. Power levels shown in the power table for the M/P package device assume 6.45 cm2 of 610 g/m2 copper heat sink area in an enclosed adapter, or 19.4 cm2 in an open frame. The provided peak power depends on the current limit for the respective device. TOPSwitch-HX Selection Selecting the optimum TOPSwitch-HX depends upon required maximum output power, efficiency, heat sinking constraints, system requirements and cost goals. With the option to externally reduce current limit, an Y, E/L or M package TOPSwitch-HX may be used for lower power applications where higher efficiency is needed or minimal heat sinking is available. Input Capacitor The input capacitor must be chosen to provide the minimum DC voltage required for the TOPSwitch-HX converter to maintain regulation at the lowest specified input voltage and maximum output power. Since TOPSwitch-HX has a high DCMAX limit and an optimized dual slope line feed forward for ripple rejection, it is possible to use a smaller input capacitor. For TOPSwitch-HX, a capacitance of 2 μF per watt is possible for universal input with an appropriately designed transformer. Primary Clamp and Output Reflected Voltage VOR A primary clamp is necessary to limit the peak TOPSwitch-HX drain to source voltage. A Zener clamp requires few parts and takes up little board space. For good efficiency, the clamp Zener should be selected to be at least 1.5 times the output reflected voltage VOR, as this keeps the leakage spike conduction time short. When using a Zener clamp in a universal input application, a VOR of less than 135 V is recommended to allow for the absolute tolerances and temperature variations of the Zener. This will ensure efficient operation of the clamp circuit and will also keep the maximum drain voltage below the rated breakdown voltage of the TOPSwitch-HX MOSFET. A high VOR is required to take full advantage of the wider DCMAX of TOPSwitch-HX. An RCD clamp provides tighter clamp voltage tolerance than a Zener clamp and allows a VOR as high as 150 V. RCD clamp dissipation can be minimized by reducing the external current limit as a function of input line voltage (see Figures 23 and 36). The RCD clamp is more cost effective than the Zener clamp but requires more careful design (see Quick Design Checklist). Output Diode The output diode is selected for peak inverse voltage, output current, and thermal conditions in the application (including 26 Rev. F 01/09 heat sinking, air circulation, etc.). The higher DCMAX of TOPSwitch-HX, along with an appropriate transformer turns ratio, can allow the use of a 80 V Schottky diode for higher efficiency on output voltages as high as 15 V (see Figure 41). Bias Winding Capacitor Due to the low frequency operation at no-load, a 10 μF bias winding capacitor is recommended. Soft-Start Generally, a power supply experiences maximum stress at start-up before the feedback loop achieves regulation. For a period of 17 ms, the on-chip soft-start linearly increases the drain peak current and switching frequency from their low starting values to their respective maximum values. This causes the output voltage to rise in an orderly manner, allowing time for the feedback loop to take control of the duty cycle. This reduces the stress on the TOPSwitch-HX MOSFET, clamp circuit and output diode(s), and helps prevent transformer saturation during start-up. Also, soft-start limits the amount of output voltage overshoot and, in many applications, eliminates the need for a soft-finish capacitor. EMI The frequency jitter feature modulates the switching frequency over a narrow band as a means to reduce conducted EMI peaks associated with the harmonics of the fundamental switching frequency. This is particularly beneficial for average detection mode. As can be seen in Figure 45, the benefits of jitter increase with the order of the switching harmonic due to an increase in frequency deviation. Devices in the P, G or M package and TOP259-261YN operate at a nominal switching frequency of 66 kHz. The FREQUENCY pin of devices in the TOP254-258 Y and E packages offer a switching frequency option of 132 kHz or 66 kHz. In applications that require heavy snubber on the drain node for reducing high frequency radiated noise (for example, video noise sensitive applications such as VCRs, DVDs, monitors, TVs, etc.), operating at 66 kHz will reduce snubber loss, resulting in better efficiency. Also, in applications where transformer size is not a concern, use of the 66 kHz option will provide lower EMI and higher efficiency. Note that the second harmonic of 66 kHz is still below 150 kHz, above which the conducted EMI specifications get much tighter. For 10 W or below, it is possible to use a simple inductor in place of a more costly AC input common mode choke to meet worldwide conducted EMI limits. Transformer Design It is recommended that the transformer be designed for maximum operating flux density of 3000 Gauss and a peak flux density of 4200 Gauss at maximum current limit. The turns ratio should be chosen for a reflected voltage (VOR) no greater than 135 V when using a Zener clamp or 150 V (max) when using an RCD clamp with current limit reduction with line voltage (overload protection). For designs where operating current is significantly lower than the default current limit, it is recommended to use an externally set current limit close to the operating peak current to reduce peak flux density and peak power (see Figures 22 and 35). In most applications, the tighter current limit tolerance, higher switching frequency and soft-start features of TOPSwitch-HX contribute to a smaller transformer when compared to TOPSwitch-GX. www.powerint.com TOP252-262 PI-2576-010600 80 70 60 50 40 30 20 -10 0 -10 -20 0.15 1 EN55022B (QP) EN55022B (AV) 10 30 Frequency (MHz) Figure 45a. Fixed Frequency Operation Without Jitter. 70 60 TOPSwitch-HX (with jitter) Amplitude (dB V) 50 40 30 20 -10 0 -10 -20 0.15 1 EN55022B (QP) EN55022B (AV) 10 30 PI-2577-010600 80 Primary Side Connections Use a single point (Kelvin) connection at the negative terminal of the input filter capacitor for the TOPSwitch-HX SOURCE pin and bias winding return. This improves surge capabilities by returning surge currents from the bias winding directly to the input filter capacitor. The CONTROL pin bypass capacitor should be located as close as possible to the SOURCE and CONTROL pins, and its SOURCE connection trace should not be shared by the main MOSFET switching currents. All SOURCE pin referenced components connected to the MULTIFUNCTION (M-pin), VOLTAGE MONITOR (V-pin) or EXTERNAL CURRENT LIMIT (X-pin) pins should also be located closely between their respective pin and SOURCE. Once again, the SOURCE connection trace of these components should not be shared by the main MOSFET switching currents. It is very critical that SOURCE pin switching currents are returned to the input capacitor negative terminal through a separate trace that is not shared by the components connected to CONTROL, MULTI-FUNCTION, VOLTAGE MONITOR or EXTERNAL CURRENT LIMIT pins. This is because the SOURCE pin is also the controller ground reference pin. Any traces to the M, V or X pins should be kept as short as possible and away from the DRAIN trace to prevent noise coupling. VOLTAGE MONITOR resistors (R1 and R2 in Figures 46, 47, 48, R3 and R4 in Figure 49, and R14 in Figure 50) should be located close to the M or V pin to minimize the trace length on the M or V pin side. Resistors connected to the M, V or X pin should be connected as close to the bulk cap positive terminal as possible while routing these connections away from the power switching circuitry. In addition to the 47 μF CONTROL pin capacitor, a high frequency bypass capacitor in parallel may be used for better noise immunity. The feedback optocoupler output should also be located close to the CONTROL and SOURCE pins of TOPSwitch-HX. Y-Capacitor The Y-capacitor should be connected close to the secondary output return pin(s) and the positive primary DC input pin of the transformer. Heat Sinking The tab of the Y package (TO-220C) and E package (eSIP-7C) and L package (eSIP-7F) are internally electrically tied to the SOURCE pin. To avoid circulating currents, a heat sink attached to the tab should not be electrically tied to any primary ground/source nodes on the PC board. When using a P (DIP-8), G (SMD-8) or M (DIP-10) package, a copper area underneath the package connected to the SOURCE pins will act as an effective heat sink. On double sided boards, topside and bottom side areas connected with vias can be used to increase the effective heat sinking area. In addition, sufficient copper area should be provided at the anode and cathode leads of the output diode(s) for heat sinking. In Figures 46 to 50 a narrow trace is shown between the output rectifier and output filter capacitor. This trace acts as a thermal relief between the rectifier and filter capacitor to prevent excessive heating of the capacitor. Amplitude (dB V) Frequency (MHz) Figure 45b. TOPSwitch-HX Full Range EMI Scan (132 kHz With Jitter) With Identical Circuitry and Conditions. Standby Consumption Frequency reduction can significantly reduce power loss at light or no load, especially when a Zener clamp is used. For very low secondary power consumption, use a TL431 regulator for feedback control. A typical TOPSwitch-HX circuit automatically enters MCM mode at no load and the low frequency mode at light load, which results in extremely low losses under no-load or standby conditions. High Power Designs The TOPSwitch-HX family contains parts that can deliver up to 333 W. High power designs need special considerations. Guidance for high power designs can be found in the Design Guide for TOPSwitch-HX (AN-43). TOPSwitch-HX Layout Considerations The TOPSwitch-HX has multiple pins and may operate at high power levels. The following guidelines should be carefully followed. 27 www.powerint.com Rev. F 01/09 TOP252-262 Isolation Barrier Optional PCB slot for external heatsink in contact with SOURCE pins VR1 C2 R4 Y1Capacitor C6 T1 C10 R9 Input Filter Capacitor J1 + R3 Output Rectifier Output Filter Capacitor D1 D3 Transformer S D U1 C M C3 R1 R2 D2 R13 R14 R6 R7 R11 U3 C9 R12 R10 R8 JP2 U2 C4 R8 C5 C8 J2 S C1 JP1 S S C7 HV - L1 Maximize hatched copper areas ( ) for optimum heat sinking VR2 Figure 46. Layout Considerations for TOPSwitch-HX Using P-Package. DC + Out PI-4753-070307 Isolation Barrier C2 Optional PCB slot for external heatsink in contact with SOURCE pins VR1 R6 R5 Y1Capacitor C6 T1 R12 Input Filter Capacitor J1 + HV - Output Rectifier Output Filter Capacitor L1 D1 D3 Transformer S S S U1 S S D C X V C4 R8 C3 R10 R1 R3 R2 R4 VR2 R9 D2 R11 JP2 U2 C7 C1 JP1 R7 C5 C9 R14 U3 R15 R16 R17 R13 C8 J2 Maximize hatched copper areas ( ) for optimum heat sinking - DC + Out Figure 47. Layout Considerations for TOPSwitch-HX Using M-Package. PI-4752-070307 28 Rev. F 01/09 www.powerint.com TOP252-262 Isolation Barrier C2 R4 T1 VR1 Y1Capacitor C6 R12 C10 D1 J1 + HV C1 JP1 R7 R1 R2 R8 HS1 Transformer S U1 F C X V C4 R10 C5 D2 R11 JP2 U2 VR2 R12 - DC + Out Figure 48. Layout Considerations for TOPSwitch-HX Using TOP254-258 Y-Package. U3 C9 D D3 C7 L1 Input Filter Capacitor R3 Output Rectifier Output Filter Capacitor R13 C8 R16 R14 R9 R3 R4 J2 R15 R17 PI-4751-070307 Isolation Barrier C6 R7 T1 D5 C16 R12 Y1Capacitor C7 Input Filter Capacitor J1 + HV C4 HS1 VR1 R6 Output Filter Capacitor D8 Transformer D S G C U5 V C8 C17 R3 JP1 R11 R14 R4 R22 R8 R10 R15 R9 R5 VR2 C9 D6 C10 U4 C21 R21 JP2 U2 R20 C18 L3 X R17 R13 J2 - DC + Out Figure 49. Layout Considerations for TOPSwitch-HX Using TOP259-261 Y-Package. PI-4977-021408 29 www.powerint.com Rev. F 01/09 TOP252-262 Isolation Barrier Y1Capacitor C7 C16 R12 Input Filter Capacitor J1 + HV C4 HS1 R6 D5 C6 R7 T1 D8 H52 U1 C8 C R4 V R3 R11 R5 R14 VR2 R9 JP2 U2 R15 R17 R13 R21 - DC + Out D6 C9 R10 C10 U4 C21 C19 R20 J2 C18 S D F X R8 R22 L3 C17 VR1 Transformer Output Rectifier Output Filter Capacitor PI-4975-022108 Figure 50a. Layout Considerations for TOPSwitch-HX Using E-Package and Operating at 66 kHz. Isolation Barrier Y1Capacitor C7 C16 R12 Input Filter Capacitor J1 + HV C4 HS1 R6 D5 C6 R7 T1 D8 H52 Output Rectifier C8 C R4 S D F X U1 C9 VR1 R22 Transformer C17 L3 Output Filter Capacitor V R3 R11 R8 R5 R14 VR2 D6 R10 C10 U4 C21 C19 R20 J2 C18 R9 JP2 U2 R15 R17 R13 R21 - DC + Out PI-4976-091608 Figure 50b. Layout Considerations for TOPSwitch-HX Using E-Package and Operating at 132 kHz. 30 Rev. F 01/09 www.powerint.com TOP252-262 Isolation Barrier Y1Capacitor C7 C16 C6 Input Filter Capacitor J1 + HV JP1 C4 R6 VR1 R7 T1 R12 D8 HS2 Transformer R22 X Y U1 R14 R3 R11 R8 C9 C10 D6 HS1 R10 VR2 Note: Components U1, R8, C8, C9 and R22 are under heat sink HS1. R9 JP2 U2 R15 R17 R13 R21 J2 U4 C21 C19 R20 C18 R4 R5 D5 F CS C8 L3 D C17 Output Rectifier Output Filter Capacitor - DC + Out Figure 50c. Layout Considerations for TOPSwitch-HX Using L-Package and Operating at 132 kHz. PI-5216-091508 Quick Design Checklist In order to reduce the no-load input power of TOPSwitch-HX designs, the V-pin (or M-pin for P Package) operates at very low current. This requires careful layout considerations when designing the PCB to avoid noise coupling. Traces and components connected to the V-pin should not be adjacent to any traces carrying switching currents. These include the drain, clamp network, bias winding return or power traces from other converters. If the line sensing features are used, then the sense resistors must be placed within 10 mm of the V-pin to minimize the V pin node area. The DC bus should then be routed to the line sense resistors. Note that external capacitance must not be connected to the V-pin as this may cause misoperaton of the V pin related functions. As with any power supply design, all TOPSwitch-HX designs should be verified on the bench to make sure that components specifications are not exceeded under worst-case conditions. The following minimum set of tests is strongly recommended: 1. Maximum drain voltage – Verify that peak VDS does not exceed 675 V at highest input voltage and maximum overload output power. Maximum overload output power occurs when the output is overloaded to a level just before the power supply goes into auto-restart (loss of regulation). 2. Maximum drain current – At maximum ambient temperature, maximum input voltage and maximum output load, verify drain current waveforms at start-up for any signs of transformer saturation and excessive leading edge current spikes. TOPSwitch-HX has a leading edge blanking time of 220 ns to prevent premature termination of the ON-cycle. Verify that the leading edge current spike is below the allowed current limit envelope (see Figure 53) for the drain current waveform at the end of the 220 ns blanking period. 3. Thermal check – At maximum output power, both minimum and maximum voltage and ambient temperature; verify that temperature specifications are not exceeded for TOPSwitch-HX, transformer, output diodes and output capacitors. Enough thermal margin should be allowed for the part-to-part variation of the RDS(ON) of TOPSwitch-HX, as specified in the data sheet. The margin required can either be calculated from the values in the parameter table or it can be accounted for by connecting an external resistance in series with the DRAIN pin and attached to the same heat sink, having a resistance value that is equal to the difference between the measured RDS(ON) of the device under test and the worst case maximum specification. Design Tools Up-to-date information on design tools can be found at the Power Integrations website: www.powerint.com 31 www.powerint.com Rev. F 01/09 TOP252-262 Absolute Maximum Ratings(2) DRAIN Peak Voltage .................................................................. -0.3 V to 700 V DRAIN Peak Current: TOP252 ................................................................ 0.68 A DRAIN Peak Current: TOP253 ................................................................. 1.37 A DRAIN Peak Current: TOP254 ................................................................ 2.08 A DRAIN Peak Current: TOP255 .................................................................2.72 A DRAIN Peak Current: TOP256 ................................................................ 4.08 A DRAIN Peak Current: TOP257 ................................................................ 5.44 A DRAIN Peak Current: TOP258 ................................................................ 6.88 A DRAIN Peak Current: TOP259 ................................................................. 7.73 A DRAIN Peak Current: TOP260 ................................................................ 9.00 A DRAIN Peak Current: TOP261 ............................................................... 11.10 A DRAIN Peak Current: TOP262 ............................................................... 11.10 A CONTROL Voltage ............................................................................-0.3 V to 9 V CONTROL Current ...................................................................................... 100 mA Thermal Impedance Thermal Impedance: Y Package: (θJA) .................................................................. 80 °C/W(1) (θJC) ............................................... .....................2 °C/W(2) P, G and M Packages: (θJA) .........................................70 °C/W(3); 60 °C/W(4) (θJC) ............................................... .................. 11 °C/W(5) E /L Package: (θJA) ................................................................105 °C/W(1) (θJC) ............................................... .....................2 °C/W(2) Notes: 1. Free standing with no heatsink. 2. Measured at the back surface of tab. 3. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad. 4. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad. 5. Measured on the SOURCE pin close to plastic interface. VOLTAGE MONITOR Pin Voltage ............................................-0.3 V to 9 V CURRENT LIMIT Pin Voltage ................................................-0.3 V to 4.5 V MULTI-FUNCTION Pin Voltage .................................................-0.3 V to 9 V FREQUENCY Pin Voltage ...........................................................-0.3 V to 9 V Storage Temperature ...........................................................-65 °C to 150 °C Operating Junction Temperature................................... -40 °C to 150 °C Lead Temperature(1) ......................................................................................260 °C Notes: 1. 1/16 in. from case for 5 seconds. 2. Maximum ratings specified may be applied one at a time without causing permanent damage to the product. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect product reliability. Parameter Symbol Conditions SOURCE = 0 V; TJ = -40 to 125 °C See Figure 54 (Unless Otherwise Specified) FREQUENCY Pin Connected to SOURCE TOP252-258Y TOP255-262L TOP252-262E FREQUENCY Pin Connected to CONTROL TOP252-258Y TOP255-262L TOP252-262E TOP252-258P/G/M TOP259-261Y 132 kHz Operation 66 kHz Operation Min Typ Max Units Control Functions 119 132 145 Switching Frequency in Full Frequency Mode (average) fOSC TJ = 25 °C kHz 59.4 66 72.6 59.4 66 ±5 ±2.5 250 72.6 kHz Hz 83 % Frequency Jitter Frequency Jitter Modulation Rate Maximum Duty Cycle Δf fM DCMAX tSOFT DCreg IC = ICD1 IV ≤ IV(DC) or IM ≤ IM(DC) or VV, VM = 0 V IV or IM = 95 μA 75 30 78 Soft-Start Time PWM Gain PWM Gain Temperature Drift External Bias Current TJ = 25 °C TJ = 25 °C TOP252-255 TOP256-258 TOP259-262 See Note A -31 -27 -25 17 -25 -22 -20 -0.01 0.9 1.0 1.1 1.5 1.6 1.7 2.1 2.2 2.4 -20 -17 -15 ms %/mA %/mA/°C mA IB 66 kHz Operation TOP252-255 TOP256-258 TOP259-262 32 Rev. F 01/09 www.powerint.com TOP252-262 Parameter Symbol Conditions SOURCE = 0 V; TJ = -40 to 125 °C (Unless Otherwise Specified) Min Typ Max Units Control Functions (cont.) External Bias Current IB 132 kHz Operation TOP252-255 TOP256-258 TOP259-262 TOP252-255 TOP256-258 TOP259-262 TOP252-255 TOP256-258 TOP259-262 1.0 1.3 1.6 1.6 1.9 2.2 4.4 4.7 5.1 4.6 5.1 6.0 18 0.18 7 kPS(UPPER) kPS(LOWER) fMCM(MIN) TJ = 25 °C See Note B TJ = 25 °C See Note B TJ = 25 °C 50 55 25 60 2.2 2.5 2.9 5.8 6.1 6.5 6.0 6.5 7.4 22 mA 66 kHz Operation CONTROL Current at 0% Duty Cycle IC(OFF) 132 kHz Operation Dynamic Impedance Dynamic Impedance Temperature Drift CONTROL Pin Internal Filter Pole Upper Peak Current to Set Current Limit Ratio Lower Peak Current to Set Current Limit Ratio Multi-CycleModulation Switching Frequency Minimum Multi-CycleModulation On Period Shutdown/Auto-Restart Control Pin Charging Current Charging Current Temperature Drift Auto-Restart Upper Threshold Voltage Auto-Restart Lower Threshold Voltage Auto-Restart Hysteresis Voltage Auto-Restart Duty Cycle Auto-Restart Frequency Line Undervoltage Threshold Current and Hysteresis (M or V Pin) Line Overvoltage Threshold Current and Hysteresis (M or V Pin) VC(AR)U VC(AR)L IC(CH) TJ = 25 °C ZC mA IC = 4 mA; TJ = 25 °C, See Figure 52 10 Ω %/°C kHz % % 30 kHz TMCM(MIN) TJ = 25 °C 135 μs VC = 0 V VC = 5 V See Note A -5.0 -3.0 -3.5 -1.8 0.5 -1.0 -0.6 mA %/°C 5.8 V 4.5 4.8 5.1 V Multi-Function (M), Voltage Monitor (V) and External Current Limit (X) Inputs VC(AR)hyst DC(AR) f(AR) Threshold IUV TJ = 25 °C Hysteresis Threshold IOV TJ = 25 °C Hysteresis 107 22 0.8 1.0 2 0.5 25 14 112 4 117 27 4 V % Hz μA μA μA μA 33 www.powerint.com Rev. F 01/09 TOP252-262 Parameter Symbol Conditions SOURCE = 0 V; TJ = -40 to 125 °C (Unless Otherwise Specified) Min Typ Max Units Multi-Function (M), Voltage Monitor (V) and External Current Limit (X) Inputs Output Overvoltage Latching Shutdown Threshold Current V or M Pin Reset Voltage Remote ON/OFF Negative Threshold Current and Hysteresis (M or X Pin) V or M Pin Short Circuit Current X or M Pin Short Circuit Current V or M Pin Voltage (Positive Current) V or M Pin Voltage Hysteresis (Positive Current) X or M Pin Voltage (Negative Current) Maximum Duty Cycle Reduction Onset Threshold Current IOV(LS) VV(TH) or VM(TH) IREM (N) IV(SC) or IM(SC) IX(SC) or IM(SC) VV or VM TJ = 25 °C Hysteresis TJ = 25 °C VX, VM = 0 V VV, VM = VC Normal Mode Auto-Restart Mode IV or IM = IUV IV or IM = IOV TOP252-TOP257 TOP258-TOP262 IV or IM = IOV IX or IM = -50 μA IX or IM = -150 μA IC ≥ IB, TJ = 25 °C IV(DC) < IV