PS12801AZN-0

PC 1602-F OUTLINE DIMENSION & BLOCK DIAGRAM 42.2 2.5 5.7 6.0 4- 1.0 79.0 73.0 61.0 56.21 2-R1.25 1.5 44.0 0.5 A K 23.6 15.6 2.15 15.8 25.0 36.0 16.0 11.5 H1 H2 14 16- 1.0 P2.54 x 15=38.1 1 16 15 2.5 10.2 4.0 2- 2.5 76.0 84.0 0.5 3.55 DB7 DB0 E R/W RS Vss Vdd Vo LCD CONTROLLER LSI COM 16 LCD PANEL 0.56 4.0 1.8 4.1 2.96 SEG 40 0.04 SEG 40 5.56 5.94 0.66 SEGMENT DRIVER A K BACKLIGHT The tolerance unless classified 0.3mm MECHANICAL SPECIFICATION Overall Size View Area Dot Size Dot Pitch 84.0 x 44.0 61.0 x 15.8 0.56 x 0.66 0.60 x 0.70 Module W /O B/L EL B/L LED B/L H2 / H1 5.1 / 9.7 5.1 / 9.7 9.4 / 14.0 PIN ASSIGNMENT Pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol Vss Vdd Vo RS R/W E DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 A K Function Power supply(GND) Power supply(+) Contrast Adjust Register select signal Data read / write Enable signal Data bus line Data bus line Data bus line Data bus line Data bus line Data bus line Data bus line Data bus line Power supply for LED B/L (+) Power supply for LED B/L ( ) ABSOLUTE MAXIMUM RATING Symbol Condition Vdd-Vss 25oC 25oC LCD driving supply voltage Vdd-Vee Input voltage 25oC Vin Item Supply for logic voltage Min. -0.3 -0.3 -0.3 0.04 CONTROL SIGNALS 4 Max. Units V 7 13 V Vdd+0.3 V ELECTRICAL CHARACTERISTICS Item Symbol Condition Min. Typical Max. Units 2.7 5.5 25oC Power supply voltage Vdd-Vss V Top N WNW NW V 7.9 V -20oC 7.1 7.5 LCD operation voltage Vop V V 50oC 4.6 3.8 4.4 V 70oC 6.3 V 5.7 6 3 Vdd=5V 2 mA 40 VB/L=4.2V mA 120 VB/L=4.2V mA 4.5 5.1 5.3 25oC 4.1 6.1 4.7 6.4 4.9 6.7 0oC LCM current consumption (No B/L) Idd LED/edge LED/array Backlight current consumption LCD option: STN, TN, FSTN Backlight Option: LED,EL Backlight feature, other Specs not available on catalog is under request. CODING SYSTEM FOR LCD MODULE PC1602 1 NO 1 P C 2 G S T 08.16.20.24 ... 3 120.122.128 ... 01.02.03.04 ... 4 32.64.128 ... A B D E F L 5 M N O P S U W R 6 Y Z None (*1) 7 N S 2 3 4 5 6 7 Cod e va lu e Character Graphic Engineer sample Total solution Characters per line (for character modules) Row dots (for graphic modules) Lines (for character modules) Column dots (for graphic modules) Without backlight EL backlight, Blue-green EL backlight, Yellow-green EL backlight, White CCFL backlight, White LED backlight, Yellow-green LED backlight, Amber LED backlight, Red LED backlight, Orange LED backlight, Pure-green LED backlight, Green LED backlight, Blue LED backlight, White Standard (through hole, cable, connector and etc.) Straight pin-header Right angle pin-header TN positive, Gray TN negative, Blue STN positive, Gray LCD mode (Type + Color) Backlight mode (Type + Color) Characters per line or row dots Lines or column dots Module type 8 9 Des cr ip tio n 10 11 Type Brand Powertip products Connecting type U 7 M F T 8 0~Z 00~ZZ NN A STN positive , Yellow-green STN negative , Blue FSTN positive , White FSTN negative , Black Series number IC manufacturer / character pattern /total solution series number Without controller Model name LCD mode (Type+Color) 9 *2 Reflective Reflective Reflective Reflective /Normal temp. /Normal temp. /6:00 direction /12:00 direction D G J B 10 E H K C F I L 11 No code value 01~ZZ /Extended temp. /6:00 direction /Extended temp. /12:00 direction /6:00 direction /12:00 direction Polarizer type/ LCD Temperature range/ Viewing direction Transflective /Noraml temp. Transflective /Noraml temp. Transflective /Extended temp. /6:00 direction Transflective /Extended temp. /12:00 direction Transmissive /Normal temp. Transmissive /Normal temp. Transmissive /Extended temp. Transmissive /Extended temp. Standard product Special code Character EA EB EC EH HH S4/S8 M: MOTOROLA LSI N: NOVATECH LSI O: OKI LSI P: PHILIPS LSI N4/N8 HO/HA/HC H2/HB/HC/HU SO S5/S6 S3 SH NO N5/N6/NI N3 NH WA W B/W 5 AO /6:00 direction /12:00 direction /6:00 direction /12:00 direction Version (*1) Without code value (*2) Character Pattern English / Japanese English / Europe English / France English / Russia English / Chinese English / Hebrew Note: A: APANPEC LSI E: ESPON LSI H: HITACHI LSI J : JRC LSI Graphic JA JB YA TA E4 R: SHARP LSI S: SUMSUNG LSI T: TOSHIBA LSI U: UMC GROUP LSI W : SITRONIX LSI Y : SANYO LSI (*3) Check with our sales for available combinations. CODING SYSTEM FOR OTHER PRODUCTS PD 1 NO 1 2 CODE PD IN05300,IN05500... VA L UE 2 DESCRIPTION TYPE Products Types Powertip design product Product characteristic NOTE:The code value and length of product characteristic are unlimited Powertip Technology, Inc. Page 1 of 2 PROFILE NEWS TECHNICAL PRODUCTS STOCKING SALES CONTACT DISTRIBUTOR NETWORK US Typtical/Electrical Characteristics of LCD Modules Optical Characteristics Of LCD Modules Electrical Characteristics Of LCD Modules Optical Characteristics Of LCD Modules http://www.powertipusa.com/char.htm 11/10/2004 Powertip Technology, Inc. Page 2 of 2 Electrical Characteristics Of LCD Modules © 2001, All rights reserved. Powertip Technology, Inc. 18 Technology Drive, STE 161, Irvine, CA 92618 Phone: (949) 585-9888, Fax: (949) 585-9889 sales@powertipusa.com http://www.powertipusa.com/char.htm 11/10/2004 Powertip Technology, Inc. Page 1 of 3 PROFILE NEWS TECHNICAL PRODUCTS STOCKING SALES CONTACT DISTRIBUTOR NETWORK US Backlight options for LCD modules EL Backlight CCFL Backlight LED Backlight EL Backlight Precautions For Handling LCD Modules Flat surface light source offers simple and even illumination over large area. Max.1.3mm thickness ( Max. 1.5mm for lead portion ) Wide driving condition, 601,000Hz at 150V AC Max. With inverter, step-up voltage from 1.5V battery is available. Emitted colors are blue-green, yellow-green and white. Operating characteristics of PC2002-A SERIES is 110V, 400Hz, 8mA, ( Ta=20°C, 60% RHæ) Temperature Range: Operating 0°C~ +50°C Storage -20°C~ +60°C Inverter for EL Backlight Drive: Requires an inverter to operate the EL panel with a battery or DC power supply. Low inverter loss and high light efficiency since it is designed for EL backlight. Constant power consumption during operation, given temperature change for extended hours. This is characterized by the constant supply current, which minimizes the brightness change of the EL panel. CCFL Backlight( Cold Cathode Fluorescent Lamp ) http://www.powertipusa.com/bl.htm 12/10/2004 Powertip Technology, Inc. Page 2 of 3 Bright white color of light source offers clear and even illumination over large viewing area. Features: High Brightness Long life time. Low Power consumption White color emitted Direct Illumination Suitable for multi-color and / or dot matrix LCDP. Edge Illumination Thin structure type of even illumination emits light from tube like light source over a large area. Precaution Inverter for CCFL use output high pressure AC current. Therefore, please pay attention when you handleinverter and power supply cable of LCD backlight. LED Backlight Long life, low power consumption and requires a simple power supply. Available colors are red, green and orange, available in array type illumination or edge illumination. Features: Low driving voltage ( DC ) and does not require an inverter. Long life of 100,000 hours ( average ) No noise occurrence. Various colors available in red, green and orange etc. (multi-color by alternative switch is also available) Operating characteristics of PC2002-A series is 4.2V, 210mA, 250cd/m Array Illumination A grid array of leaÍs provide even illumination. http://www.powertipusa.com/bl.htm 12/10/2004 Powertip Technology, Inc. Page 3 of 3 Edge Illumination Combination LED with a light guide offers a thin structure type of illumination. © 2001, All rights reserved. Powertip Technology, Inc. 18 Technology Drive, STE 161, Irvine, CA 92618 Phone: (949) 585-9888, Fax: (949) 585-9889 sales@powertipusa.com http://www.powertipusa.com/bl.htm 12/10/2004 Powertip Technology, Inc. Page 1 of 3 PROFILE NEWS TECHNICAL PRODUCTS STOCKING SALES CONTACT DISTRIBUTOR NETWORK US Power Supply Reset The internal reset circuit will be operating properly when the following power supply conditions are satisfied. If it is not operating properly, please perform the initial setting along with the instruction. Measuring Item Power Supply RISE Time Power Supply OFF Time Reset function Initialization made by internal reset circuit Standard Value Unit Min. 0.1 1 Typ. --------Max. 10 ----mS mS Symbol Condition trse toff --------- The HD44780 automatically initializes (resets) when power is supplied (builtin internal reset circuit). The following instructions are executed during initialization. The busy flag (BF) is kept in busy state until initialization ends. (BF=1) The busy state is 10ms after Vdd reaches 4.5V. 1. Display clear 2. Function set DL=1:8 bit long interface data DL=0:4 bit F=0:5 * 7 dots character font N=1:2 lines N=0:1 line 3. Display ON/OFF control D=0:Display OFF C=0:Cursor OFF B=0:Blink OFF 4. Entry mode set 1/D= 1:+1(increment) S=0:No shift Note: When the power supply conditions, using internal reset circuit is not satisfied, the internal reset circuit will not function properly and initialization will not be performed.Please initialize using the MPU along with the instruction set. http://www.powertipusa.com/ps.htm 11/10/2004 Powertip Technology, Inc. Page 2 of 3 Initialization along with instruction If power supply conditions are not satisfied, for the proper operation of the internal reset circuit, it is necessary to initialize using the instructions. Please use the following procedures. http://www.powertipusa.com/ps.htm 11/10/2004 Powertip Technology, Inc. Page 3 of 3 © 2001, All rights reserved. Powertip Technology, Inc. 18 Technology Drive, STE 161, Irvine, CA 92618 Phone: (949) 585-9888, Fax: (949) 585-9889 sales@powertipusa.com http://www.powertipusa.com/ps.htm 11/10/2004 Powertip Technology, Inc. Page 1 of 3 PROFILE NEWS TECHNICAL PRODUCTS STOCKING SALES CONTACT DISTRIBUTOR NETWORK US Interface With MPU Example of interfacing to an 8-bit MPU(Z80) Example of interfacing to a 4-bit MPU If interface data is 4-bits long If interface data is 8-bits long Example of interfacing to an 8-bit MPU(Z80) Example of interface to a 4-bit MPU Interface to a 4-bit MPU can be made through the I/O port of the 4-bit MPU. If there are sufficient I/O ports, data can be transferred at 8-bit cycles, however, if there are not, data transfer can be accomplished by two cycles of 4-bit transfers (select interface as 4-bits long). Please take into account that 2 cycles of the BF check will be necessary and the timing sequence will prove to be complicated. http://www.powertipusa.com/mpu.htm 11/10/2004 Powertip Technology, Inc. Page 2 of 3 Features: 1. Interface to an 8-bit or 4-bit MPU is available. 2. 192 types of alphanumerics, symbols and special characters can be displayed with the multi built-in character generator(ROM). 3. Other preferred characters can be displayed by character generator(RAM) 4. Various instructions may be programmed. Clear display Cursor at home On/Off cursor Blink character Shift display Shift cursor Read/write display data, etc. 5. Compact and light weight design which can easily be integrated into end products. 6. single power supply +5V drive(except for extended temp. type). 7. Low power consumption. Interface between data bus line and 4-bit or 8-bit MPU is available. Data transfer requires two cycles in case of a 4-bit MPU, and once in case of an 8-bit MPU. If Interface Data Is 4-bit long Data transfer is accomplished through 4 bus lines from DB4 to DB7.(while the rest of 4 bus lines from DB0 to DB3 are not used.) Data transfer is completed when 4-bits of data is transferred twice.(upper 4-bits of data, then lower 4bits of data.) http://www.powertipusa.com/mpu.htm 11/10/2004 Powertip Technology, Inc. Page 3 of 3 If Interface Data Is 8-bits Long Data transfer is made through all 8 bus lines from DB0 to DB7. © 2001, All rights reserved. Powertip Technology, Inc. 18 Technology Drive, STE 161, Irvine, CA 92618 Phone: (949) 585-9888, Fax: (949) 585-9889 sales@powertipusa.com http://www.powertipusa.com/mpu.htm 11/10/2004 Powertip Technology, Inc. Page 1 of 2 PROFILE NEWS TECHNICAL PRODUCTS STOCKING SALES CONTACT DISTRIBUTOR NETWORK US Standard Character Pattern Character Pattern (WB) Character Pattern (HC) Character Pattern (NI) Character Pattern (JA) Character Pattern (SO,WA) Character Pattern Character Pattern (N5) Character Pattern Character Pattern (N4) Character Pattern (TA) Character Pattern (NH) Character Pattern (YA) http://www.powertipusa.com/pat.htm 11/10/2004 Powertip Technology, Inc. Page 2 of 2 © 2001, All rights reserved. Powertip Technology, Inc. 18 Technology Drive, STE 161, Irvine, CA 92618 Phone: (949) 585-9888, Fax: (949) 585-9889 sales@powertipusa.com http://www.powertipusa.com/pat.htm 11/10/2004 Powertip USA Page 1 of 6 PROFILE NEWS TECHNICAL PRODUCTS STOCKING SALES CONTACT DISTRIBUTOR NETWORK US Q&A 1. Adjusting the contrast of a character LCD module. There are two means of adjusting the contrast: Please refer to the following drawing: 1. Internal: J2 short, add the appropriate resister to R7 for contrast control. 2. External: J1 short, R7=0, By adding a VR the contrast can be controlled externally. Please note the following diagram: 2. Connecting and powering the backlight. There are two means of connecting and powering the backlight. Please refer to the below diagrams: http://www.powertipusa.com/qa.htm 11/10/2004 Powertip USA Page 2 of 6 1. PINS 1 & 2 (Vdd & Vss): J3 short, by adding a resistor on R9. 2. PINS 15 & 16: J4 short, by adding a resistor on R8. NOTE: The brightness can be controlled by the value of R8 or R9. 3. Reference table for establishing the relationship between the temperature range, viewing direction and type of polarizer: 4. Differences between a driver IC, a controller IC and a controller/driver IC: Driver IC: There are two types of driver IC's. One is a "common" driver and the other a "segment" driver. Common drivers output signals to create the rows or number of lines while the segment drivers output the necessary signals to create the characters or columns. Controller IC: This IC receives data written in ASCII or JIS code from the MPU and stores this data in RAM. This data is then converted into a serial character pattern and transferred to the LCD driver IC. Driver/Controller IC: It is most commonly found in a graphics module. It receives data from the MPU and stores it in RAM. It accepts commands directly from the MPU for both the common and segment drivers. 5. Following is the minimum dot size and pitch on the LCD, the ITO line on the LCD and the elastomer (zebra) connector: ITEM LCD Dots LCD ITO lines Rubber Connectors Heat Seal Dots or Lines 0.22mm S=0.075, C=0.08mm 0.025mm 0.09mm Gaps 0.02mm 0.03mm 0.025mm 0.09mm 6. Advantages and disadvantages of backlight versions: http://www.powertipusa.com/qa.htm 11/10/2004 Powertip USA Page 3 of 6 7. Comparison between TN, STN and FSTN technologies: ITEM TN STN FSTN Contrast Ratio 3 2 1 View Angle 3 2 1 COST 3 2 1 Remarks: with 1 being the best or most expensive and 3 the worst or least expensive. 8. Differences between reflective, transflective and transmissive displays Reflective: Such display includes a diffuser. This layer reflects the light that enters the front of the display. Reflective displays require ambient light for the light source since there is no backlight. Transflective: As type of backing which is bonded to the rear polarizer. Enables light to pass through the back, as well as reflecting light from the front. Transmissive: A type of LCD which does not have a reflector or transflector laminated to the rear polarizer. A backlight must be used with this type of LCD configuration. The most common is a transmissive negative image. 9. Considerations for attaining a 3.0 Volt LCD module: IC: Choose the ICs that can be driven at 3.3V or less. Below is a list of IC's that can accomplish this requirement: Controller: KS0066U 2.7 ~ 5.5V KS0070B 2.7 ~ 5.5V HD44780U 2.7 ~ 5.5V Driver: http://www.powertipusa.com/qa.htm 11/10/2004 Powertip USA Page 4 of 6 KS0065 2.7 ~ 5.5V KS0063 2.7 ~ 5.5V SED1181 5.0V min. LCD panel: The driving voltage for most all LCD panels is above 3.3V. It is necessary to then add a "negative voltage" IC on the PCB of the module or to the customer's motherboard to raise the voltage. A couple of NV generators is as follows: NV IC: SCI7661 3X with temperature compensation. SCI7660 2X, dice font available (at a much less expensive cost). If a NV IC must be incorporated onto the module PCB, there is apt to be two possible considerations: 1. Tooling cost 2. The PCB is too small to accommodate the NV IC. If there is not sufficient space, a possible solution would be to replace one controller with a driver, with single controller (such as replacing a KS0066(U) & KS0065(B) with a KS0070). The per unit cost will be a little greater but it will save overall space on the PCB and eliminate having to re-tool the PCB. Some TAB IC's such as SED1560 series include a power circuit, which can amplify the input voltage to drive the LCD. In this case it is not necessary to add a NV IC to raise the voltage. C. Backlight: CCFL & EL: These backlight options require an inverter. The inverter chosen cannot exceed 3.3 Volts. LED: In an attempt to achieve this 3.3V requirement it is necessary to use an edge-lit LED. Note this edge-lit LED will still consume a large current. 10. Reference to Viewing angle: Viewing Angle is the direction by which the display will look best. This is established during the manufacturing process and can not be changed by rotating the polarizer. Viewing direction is specified in terms of a clock position, such as 6:00 & 12:00. Please refer to the following drawing: http://www.powertipusa.com/qa.htm 11/10/2004 Powertip USA Page 5 of 6 11. Clarification to the term "rainbow" effect: This refers to a red and green circle or rainbow on the LCD glass. The LCD panel under uneven pressure causes this problem from the bezel. It is very common in LCD modules and normally it will not affect the performance or the appearance of the display when operational. 12. Pin assignments for a Character module: Example of a standard 14-pin character module: PIN 1: Vss PIN 2: Vdd PIN 3: Vo PIN 4: RS PIN 5: R/W PIN 6: Enable PIN 7 ~ 14: DB0 ~ DB7 13. What is temperature compensation and why is required A LCD operating voltage varies at different temperatures. The operating voltage must rise as temperature lowers or the contrast will degrade. Conversely, the operating temperature must fall as the temperature rises or the contrast will degrade. For this reason it is often a requirement, with graphics modules, to control the input voltage accordingly. The temperature compensation circuit is the circuit that controls the input voltage as the temperature changes. This temperature compensation circuit can be located on the LCD module or on the customer's motherboard. 14. Troubleshooting a LED backlit module in which the display is turning dark: This problem is more than likely caused by the temperature rise from the LED backlight. In this case the LED backlight has consumed too much of the power. When the temperature rises, the VLCD becomes lower causing the input voltage to be too high. The result is a poor contrast and the display becoming too dark. The solution would be to lower the power consumption of the LED. This can be accomplished by raising the value of R8 or R9 to reduce the current to the LED backlight. 15. How to control the LED backlight on a 14-pin module: Short J2, the Vdd is controlling the input to the LED backlight. In addition, it is necessary to place a current limiting resistor to lower the voltage from 5V to 4.2V. Note: If the LED is drawing too much current, it may cause the Vdd † Vo too low and the contrast becomes poor. If this should occur increasing the value of R9 should decrease the current draw to the LED backlight or another approach would be to increase the voltage input to the LCD by decreasing the value of R7. 16. Examples of the current consumption of an LED backlit, EL backlit and the LCD for the following modules: http://www.powertipusa.com/qa.htm 11/10/2004 Powertip USA Page 6 of 6 Products PC1602-F PC2002-B PC2004-A PC4004-A LCM 1.3mA 1.8mA 1.8mA 2.2mA LED 120mA 200mA 260mA 440mA EL 3.26mA 5.3mA 7.2mA 7.5mA 17. Following is the Vop range for a Character and Graphics LCD module: LCD Type Character Graphic Vop for N.T. 4.2 ~ 4.8V 5.5 ~ 26V Vop for W.T. 5 ~ 9V 6 ~ 28V Note: N.T. = normal temperature W.T.= wide temperature © 2001, All rights reserved. Powertip Technology, Inc. 18 Technology Drive, STE 161, Irvine, CA 92618 Phone: (949) 585-9888, Fax: (949) 585-9889 sales@powertipusa.com http://www.powertipusa.com/qa.htm 11/10/2004 ST Sitronix Features !" #" #" #" #" 5 x 8 and 5 x 11 dot matrix possible Low power operation support: -- 2.7 to 5.5V Wide range of LCD driver power -- 3.0 to 10V #" Correspond to high speed MPU bus interface -- 2 MHz (when VCC = 5V) #" 4-bit or 8-bit MPU interface enabled #" 80 x 8-bit display RAM (80 characters max.) #" 13,200-bit character generator ROM for a total of 240 character fonts(5 x 8 dot or 5 x 11 dot) #" 64 x 8-bit character generator RAM -- 8 character fonts (5 x 8 dot) -- 4 character fonts (5 x 11 dot) #" 16-common x 40-segment liquid crystal display driver ST7066U Dot Matrix LCD Controller/Driver #" Programmable duty cycles -- 1/8 for one line of 5 x 8 dots with cursor -- 1/11 for one line of 5 x 11 dots & cursor -- 1/16 for two lines of 5 x 8 dots & cursor #" Wide range of instruction functions: Display clear, cursor home, display on/off, cursor on/off, display character blink, cursor shift, display shift #" Pin function compatibility with HD44780, KS0066 and SED1278 #" Automatic reset circuit that initializes the controller/driver after power on #" Internal oscillator with external resistors #" Low power consumption #" QFP80 and Bare Chip available Description !" The ST7066U dot-matrix liquid crystal display controller and driver LSI displays alphanumeric, Japanese kana characters, and symbols. It can be configured to drive a dot-matrix liquid crystal display under the control of a 4- or 8-bit microprocessor. Since all the functions such as display RAM, character generator, and liquid crystal driver, required for driving a dot-matrix liquid crystal display are internally provided on one chip, a minimal system can be interfaced with this controller/driver. The ST7066U has pin function compatibility with the HD44780, KS0066 and SED1278 that allows the user to easily replace it with an ST7066U. The ST7066U character generator ROM is extended to generate 240 5x8(5x11) dot character fonts for a total of 240 different character fonts. The low power supply (2.7V to 5.5V) of the ST7066U is suitable for any portable battery-driven product requiring low power dissipation. The ST7066U LCD driver consists of 16 common signal drivers and 40 segment signal drivers which can extend display size by cascading segment driver ST7065 or ST7063. The maximum display size can be either 80 characters in 1-line display or 40 characters in 2-line display. A single ST7066U can display up to one 8-character line or two 8-character lines. Product Name ST7066U-0A ST7066U-0B ST7066U-0E Support Character English / Japan English / European English / European V2.0 1/42 2001/03/01 ST7066U ST7066 Serial Specification Revision History Version Date Description 1.7 1. Added 8051 Example Program Code(Page 21,23) 2. Added Annotated Flow Chart : 2000/10/31 “BF cannot be checked before this instruction” 3. Changed Maximum Ratings Power Supply Voltage:+5.5V →+7.0V(Page 28) 2000/11/14 Added QFP Pad Configuration(Page 5) 2000/11/30 1. Moved QFP Package Dimensions(Page 39) to Page 5 2. Changed DC Characteristics Ratings(Page 32,33) 1.8 1.8a 2.0 2001/03/01 Transition to ST7066U V2.0 2/42 2001/03/01 ST7066U !" lock Diagram B OSC1 OSC2 CL1 CL2 M Timing generator D Reset circuit Instruction register(IR) CPG Instruction decoder RS RW E Display data RAM (DDRAM) 80x8 bits 16-bit shift register Common signal driver COM1 to COM16 MPU interface Address counter 40-bit shift register 40-bit latch circuit Segment signal driver SEG1 to SEG40 DB4 to DB7 Input/ output buffer Data register (DR) LCD drive voltage selector DB0 to DB3 Busy flag Character generator RAM (CGRAM) 64 bytes GND Character generator ROM (CGROM) 13,200 bits Cursor and blink controller Parallel/serial converter and attribute circuit Vcc V1 V2 V3 V4 V5 V2.0 3/42 2001/03/01 ST7066U !" ad Arrangement P SEG31 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG09 SEG08 SEG07 SEG06 SEG05 SEG04 SEG03 SEG02 SEG01 GND OSC1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 SEG39 SEG40 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM09 COM08 COM07 COM06 COM05 COM04 COM03 COM02 COM01 DB7 DB6 DB5 DB4 DB3 DB2 ST7066U 62 61 60 59 58 57 (0,0) 56 55 54 53 Chip Size : 2300x3000μm Coordinate : Pad Center Origin : Chip Center Min Pad Pitch : 120μm Pad Size : 96x96μm 52 51 50 49 48 47 46 45 44 43 42 25 OSC2 26 V1 27 V2 28 V3 29 V4 30 V5 31 CL1 32 CL2 33 Vcc 3 M 35 D 36 RS 37 R/W 38 E 39 DB0 40 DB1 41 Substrate Connect to VDD. V2.0 4/42 2001/03/01 ST7066U !" ackage Dimensions P V2.0 5/42 2001/03/01 ST7066U !" Configuration(80 QFP) Pad S 2 3 8 0 S 2 4 7 9 S 2 5 7 8 S 2 6 7 7 S 2 7 7 6 S 2 8 7 5 S 2 9 7 4 S 3 0 7 3 S 3 1 7 2 S 3 2 7 1 S 3 3 7 0 S 3 4 6 9 S 3 5 6 8 S 3 6 6 7 S 3 7 6 6 S 3 8 6 5 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S09 S08 S07 S06 S05 S04 S03 S02 S01 GND OSC1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 S39 S40 C16 C15 C14 C13 C12 C11 C10 C09 C08 C07 C06 C05 C04 C03 C02 C01 DB7 DB6 DB5 DB4 DB3 DB2 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 41 O S C 2 V 1 V 2 V 3 V 4 V 5 C L 1 C L 2 V C C MD R S RE W D B 0 D B 1 V2.0 6/42 2001/03/01 ST7066U !" Pad Location Pad No. Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 GND OSC1 OSC2 V1 V2 V3 V4 V5 CL1 CL2 Vcc M D RS RW E DB0 DB1 Coordinates X -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -1040 -910 -780 -660 -540 -420 -300 -180 -60 60 180 300 420 540 660 780 910 Y 1400 1270 1140 1020 900 780 660 540 420 300 180 60 -60 -180 -300 -420 -540 -660 -780 -900 -1020 -1140 -1270 -1400 -1400 -1400 -1400 -1400 -1400 -1400 -1400 -1400 -1400 -1400 -1400 -1400 -1400 -1400 -1400 -1400 Pad No. Function 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 DB2 DB3 DB4 DB5 DB6 DB7 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 X 1040 1040 1040 1040 1040 1040 1040 1040 1040 1040 1040 1040 1040 1040 1040 1040 1040 1040 1040 1040 1040 1040 1040 1040 910 780 660 540 420 300 180 60 -60 -180 -300 -420 -540 -660 -780 -910 Y -1400 -1270 -1140 -1020 -900 -780 -660 -540 -420 -300 -180 -60 60 180 300 420 540 660 780 900 1020 1140 1270 1400 1400 1400 1400 1400 1400 1400 1400 1400 1400 1400 1400 1400 1400 1400 1400 1400 V2.0 7/42 2001/03/01 ST7066U !" Function Pin Name RS Number 1 I/O Interfaced with I MPU Function Select registers. 0: Instruction register (for write) Busy flag: address counter (for read) 1: Data register (for write and read) Select read or write. 0: Write 1: Read Starts data read/write. Four high order bi-directional tristate data bus pins. Used for data transfer and receive between the MPU and the ST7066U. DB7 can be used as a busy flag. Four low order bi-directional tristate data bus pins. Used for data transfer and receive between the MPU and the ST7066U. These pins are not used during 4-bit operation. Clock to latch serial data D sent to the extension driver Clock to shift serial data D Switch signal for converting the liquid crystal drive waveform to AC Character pattern data corresponding to each segment signal Common signals that are not used are changed to non-selection waveform. COM9 to COM16 are non-selection waveforms at 1/8 duty factor and COM12 to COM16 are non-selection waveforms at 1/11 duty factor. Segment signals Power supply for LCD drive VCC - V5 = 10 V (Max) VCC : 2.7V to 5.5V, GND: 0V When crystal oscillation is performed, a resistor must be connected externally. When the pin input is an external clock, it must be input to OSC1. R/W E DB4 to DB7 1 1 4 I I I/O MPU MPU MPU DB0 to DB3 4 I/O MPU CL1 CL2 M D 1 1 1 1 O O O O Extension driver Extension driver Extension driver Extension driver COM1 to COM16 SEG1 to SEG40 V1 to V5 VCC , GND OSC1, OSC2 16 O LCD 40 5 2 2 O - LCD Power supply Power supply Oscillation resistor clock Note: 1. Vcc>=V1>=V2>=V3>=V4>=V5 must be maintained 2. Two clock options: R=91KΩ(Vcc=5V) R=75KΩ(Vcc=3V) OSC1 R OSC2 Clock input OSC1 OSC2 V2.0 8/42 2001/03/01 ST7066U !" Function Description #" System Interface This chip has all two kinds of interface type with MPU : 4-bit bus and 8-bit bus. 4-bit bus or 8-bit bus is selected by DL bit in the instruction register. During read or write operation, two 8-bit registers are used. One is data register (DR), the other is instruction register(IR). The data register(DR) is used as temporary data storage place for being written into or read from DDRAM/CGRAM, target RAM is selected by RAM address setting instruction. Each internal operation, reading from or writing into RAM, is done automatically. So to speak, after MPU reads DR data, the data in the next DDRAM/CGRAM address is transferred into DR automatically. Also after MPU writes data to DR, the data in DR is transferred into DDRAM/CGRAM automatically. The Instruction register(IR) is used only to store instruction code transferred from MPU. MPU cannot use it to read instruction data. To select register, use RS input pin in 4-bit/8-bit bus mode. RS R/W L L H H L H L H Operation Instruction Write operation (MPU writes Instruction code into IR) Read Busy Flag(DB7) and address counter (DB0 ~ DB6) Data Write operation (MPU writes data into DR) Data Read operation (MPU reads data from DR) Table 1. Various kinds of operations according to RS and R/W bits. #" Busy Flag (BF) W hen BF = "High”, it indicates that the internal operation is being processed. So during this time the next instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation), through DB7 port. Before executing the next instruction, be sure that BF is not High. #" Address Counter (AC) Address Counter(AC) stores DDRAM/CGRAM address, transferred from IR. After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1. When RS = "Low" and R/W = "High", AC can be read through DB0 ~ DB6 ports. V2.0 9/42 2001/03/01 ST7066U #" Display Data RAM (DDRAM) Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its extended capacity is 80 x 8 bits, or 80 characters. The area in display data RAM (DDRAM) that is not used for display can be used as general data RAM. See Figure 1 for the relationships between DDRAM addresses and positions on the liquid crystal display. The DDRAM address (ADD ) is set in the address counter (AC) as hexadecimal. $" 1-line display (N = 0) (Figure 2) W hen there are fewer than 80 display characters, the display begins at the head position. For example, if using only the ST7066U, 8 characters are displayed. See Figure 3. When the display shift operation is performed, the DDRAM address shifts. See Figure 3. High Order bits Low Order bits Example: DDRAM Address 4F 1 0 0 1 1 1 1 AC AC6 AC5 AC4 AC3 AC2 AC1 AC0 Figure 1 DDRAM Address Display Position 1 (Digit) 00 DDRAM Address 2 3 4 5 6 78 79 80 01 02 03 04 05 ……………….. 4D 4E 4F Figure 2 1-Line Display Display Position DDRAM Address 1 2 3 4 5 6 7 8 00 01 02 03 04 05 06 07 For Shift Left 01 02 03 04 05 06 07 08 For Shift Right 4F 00 01 02 03 04 05 06 Figure 3 1-Line by 8-Character Display Example $" 2-line display (N = 1) (Figure 4) Case 1: When the number of display characters is less than 40 × 2 lines, the two lines are displayed from the head. Note that the first line end address and the second line start address are not consecutive. For example, when just the ST7066U is used, 8 characters × 2 lines are displayed. See Figure 5. V2.0 10/42 2001/03/01 ST7066U When display shift operation is performed, the DDRAM address shifts. See Figure 5. Display Position 1 2 3 4 5 6 38 39 40 00 DDRAM Address 40 (hexadecimal) 01 41 02 42 03 43 04 44 05 45 ……………….. ……………….. 25 65 26 66 27 67 Figure 4 2-Line Display Display Position DDRAM Address 1 2 3 4 5 6 7 8 00 40 01 41 02 42 03 43 04 44 05 45 06 46 07 47 For Shift Left 01 41 02 42 03 43 04 44 05 45 06 46 07 47 08 48 For Shift Right 27 67 00 40 01 41 02 42 03 43 04 44 05 45 06 46 Figure 5 2-Line by 8-Character Display Example Case 2: For a 16-character × 2-line display, the ST7066U can be extended using one 40-output extension driver. See Figure 6. When display shift operation is performed, the DDRAM address shifts. See Figure 6. Display 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Position 00 DDRAM Address 40 01 41 02 42 03 43 04 44 05 45 06 46 07 47 08 48 09 49 0A 4A 0B 0C 0D 0E 4B 4C 4D 4E 0F 4F For Shift Left 01 41 02 42 03 43 04 44 05 45 06 46 07 47 08 48 09 49 0A 4A 0B 0C 0D 0E 4B 4C 4D 4E 0F 4F 10 50 For Shift Right 27 67 00 40 01 41 02 42 03 43 04 44 05 45 06 46 07 47 08 48 09 49 0A 4A 0B 0C 0D 0E 4B 4C 4D 4E Figure 6 2-Line by 16-Character Display Example V2.0 11/42 2001/03/01 ST7066U #" Character Generator ROM (CGROM) The character generator ROM generates 5 x 8 dot or 5 x 11 dot character patterns from 8-bit character codes. It can generate 240 5 x 8 dot character patterns. User-defined character patterns are also available by mask-programmed ROM. #" Character Generator RAM (CGRAM) In the character generator RAM, the user can rewrite character patterns by program. For 5 x 8 dots, eight character patterns can be written, and for 5 x 11 dots, four character patterns can be written. W rite into DDRAM the character codes at the addresses shown as the left column of Table 4 to show the character patterns stored in CGRAM. See Table 5 for the relationship between CGRAM addresses and data and display patterns. Areas that are not used for display can be used as general data RAM. #" Timing Generation Circuit T he timing generation circuit generates timing signals for the operation of internal circuits such as DDRAM, CGROM and CGRAM. RAM read timing for display and internal operation timing by MPU access are generated separately to avoid interfering with each other. Therefore, when writing data to DDRAM, for example, there will be no undesirable interference, such as flickering, in areas other than the display area. #" LCD Driver Circuit LCD Driver circuit has 16 common and 40 segment signals for LCD driving. Data from CGRAM/CGROM is transferred to 40 bit segment latch serially, and then it is stored to 40 bit shift latch. When each common is selected by 16 bit common register, segment data also output through segment driver from 40 bit segment latch. In case of 1-line display mode, COM1 ~ COM8 have 1/8 duty or COM1 ~ COM11 have 1/11duty , and in 2-line mode, COM1 ~ COM16 have 1/16 duty ratio. #" Cursor/Blink Control Circuit It can generate the cursor or blink in the cursor/blink control circuit. The cursor or the blink appears in the digit at the display data RAM address set in the address counter. V2.0 12/42 2001/03/01 ST7066U Table 4 Correspondence between Character Codes and Character Patterns (ROM Code: 0A) V2.0 13/42 2001/03/01 ST7066U Table 4(Cont.) (ROM Code: 0B) V2.0 14/42 2001/03/01 ST7066U Table 4(Cont.) (ROM Code: 0E) V2.0 15/42 2001/03/01 ST7066U Character Code (DDRAM Data) b7 b6 b5 b4 b3 b2 0 0 0 0 00000 0 0 0 0 0 0 0 00000 0 0 0 b1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CGRAM Address b0 b5 b4 b3 b2 0 0 0 0 0 0 0 0 000 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 001 1 1 1 1 1 1 1 1 b1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Character Patterns (CGRAM Data) b0 b7 b6 b5 b4 0 1 1 0 0 0 1 0 --0 0 1 0 0 0 1 0 0 1 1 1 0 1 1 1 --0 1 1 1 0 1 1 0 b3 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 b2 1 1 1 1 1 1 1 0 1 0 0 1 1 0 0 0 b1 1 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 b0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 Table 5 Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character patterns (CGRAM Data) Notes: 1. Character code bits 0 to 2 correspond to CGRAM address bits 3 to 5 (3 bits: 8 types). 2. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and its display is formed by a logical OR with the cursor. Maintain the 8th line data, corresponding to the cursor display position, at 0 as the cursor display. If the 8th line data is 1, 1 bits will light up the 8th line regardless of the cursor presence. 3. Character pattern row positions correspond to CGRAM data bits 0 to 4 (bit 4 being at the left). 4. As shown Table 5, CGRAM character patterns are selected when character code bits 4 to 7 are all 0. However, since character code bit 3 has no effect, the R display example above can be selected by either character code 00H or 08H. 5. 1 for CGRAM data corresponds to display selection and 0 to non-selection. “-“: Indicates no effect. V2.0 16/42 2001/03/01 ST7066U !" Instructions There are four categories of instructions that: #" Designate ST7066U functions, such as display format, data length, etc. #" Set internal RAM addresses #" Perform data transfer with internal RAM #" Others Instruction Table: Instruction Code Instruction Clear Display Return Home RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description W rite "20H" to DDRAM. and set DDRAM address to "00H" from AC Set DDRAM address to "00H" from AC and return cursor to its original position if shifted. The contents of DDRAM are not changed. Sets cursor move direction and specifies display shift. These operations are performed during data write and read. D=1:entire display on C=1:cursor on B=1:cursor position on Set cursor moving and display shift control bit, and the direction, without changing DDRAM data. DL:interface data is 8/4 bits N:number of line is 2/1 F:font size is 5x11/5x8 Set CGRAM address in address counter Description Time (270KHz) 0 0 0 0 0 0 0 0 0 1 1.52 ms 0 0 0 0 0 0 0 0 1 x 1.52 ms Entry Mode Set Display ON/OFF Cursor or Display Shift Function Set Set CGRAM address Set DDRAM address Read Busy flag and address W rite data to RAM Read data from RAM 0 0 0 0 0 0 0 1 I/D S 37 us 0 0 0 0 0 0 1 D C B 37 us 0 0 0 0 0 1 S/C R/L x x 37 us 0 0 0 0 1 DL N F x x 37 us 37 us 37 us 0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0 0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0 0 1 BF 1 0 D7 1 1 D7 Set DDRAM address in address counter W hether during internal operation or not can be AC6 AC5 AC4 AC3 AC2 AC1 AC0 known by reading BF. The contents of address counter can also be read. W rite data into internal D6 D5 D4 D3 D2 D1 D0 RAM (DDRAM/CGRAM) Read data from internal D6 D5 D4 D3 D2 D1 D0 RAM (DDRAM/CGRAM) 0 us 37 us 37 us Note: Be sure the ST7066U is not in the busy state (BF = 0) before sending an instruction from the MPU to the ST7066U. If an instruction is sent without checking the busy flag, the time between the first instruction and next instruction will take much longer than the instruction time itself. Refer to Instruction Table for the list of each instruction execution time. V2.0 17/42 2001/03/01 ST7066U !" Instruction Description #" Clear Display RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Code 0 0 0 0 0 0 0 0 0 1 Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H" into AC (address counter). Return cursor to the original status, namely, bring the cursor to the left edge on first line of the display. Make entry mode increment (I/D = "1"). #" Return Home RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Code 0 0 0 0 0 0 0 0 1 x Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return cursor to its original site and return display to its original status, if shifted. Contents of DDRAM does not change. #" Entry Mode Set RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Code 0 0 0 0 0 0 0 1 I/D S Set the moving direction of cursor and display. $" I/D : Increment / decrement of DDRAM address (cursor or blink) W hen I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1. When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1. * CGRAM operates the same as DDRAM, when read from or write to CGRAM. $" S: Shift of entire display W hen DDRAM read (CGRAM read/write) operation or S = "Low", shift of entire display is not performed. If S = "High" and DDRAM write operation, shift of entire display is performed according to I/D value (I/D = "1" : shift left, I/D = "0" : shift right). S H H I/D H L Description Shift the display to the left Shift the display to the right V2.0 18/42 2001/03/01 ST7066U #" Display ON/OFF RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Code 0 0 0 0 0 0 1 D C B Control display/cursor/blink ON/OFF 1 bit register. $" D : Display ON/OFF control bit W hen D = "High", entire display is turned on. When D = "Low", display is turned off, but display data is remained in DDRAM. $" C : Cursor ON/OFF control bit W hen C = "High", cursor is turned on. When C = "Low", cursor is disappeared in current display, but I/D register remains its data. $" B : Cursor Blink ON/OFF control bit W hen B = "High", cursor blink is on, that performs alternate between all the high data and display character at the cursor position. When B = "Low", blink is off. #" Cursor or Display Shift RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Code 0 0 0 0 0 1 S/C R/L x x W ithout writing or reading of display data, shift right/left cursor position or display. This instruction is used to correct or search display data. During 2-line mode display, cursor moves to the 2nd line after 40th digit of 1st line. Note that display shift is performed simultaneously in all the line. When displayed data is shifted repeatedly, each line shifted individually. When display shift is performed, the contents of address counter are not changed. S/C L L H H R/L L H L H Description Shift cursor to the left Shift cursor to the right Shift display to the left. Cursor follows the display shift AC Value AC=AC-1 AC=AC+1 AC=AC Shift display to the right. Cursor follows the display shift AC=AC #" Function Set Code RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 DL N F x x V2.0 19/42 2001/03/01 ST7066U $" DL : Interface data length control bit W hen DL = "High", it means 8-bit bus mode with MPU. When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select 8-bit or 4-bit bus mode. When 4-bit bus mode, it needs to transfer 4-bit data by two times. $" N : Display line number control bit W hen N = "Low", it means 1-line display mode. When N = "High", 2-line display mode is set. $" F : Display font type control bit W hen F = "Low", it means 5 x 8 dots format display mode When F = "High", 5 x11 dots format display mode. N L L H F L H x No. of Display Lines Character Font Duty Factor 1 1 2 5x8 5x11 5x8 1/8 1/11 1/16 #" Set CGRAM Address RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Code 0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address to AC. This instruction makes CGRAM data available from MPU. #" Set DDRAM Address RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Code 0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address to AC. This instruction makes DDRAM data available from MPU. When 1-line display mode (N = 0), DDRAM address is from "00H" to "4FH". In 2-line display mode (N = 1), DDRAM address in the 1st line is from "00H" to "27H", and DDRAM address in the 2nd line is from "40H" to "67H". V2.0 20/42 2001/03/01 ST7066U #" Read Busy Flag and Address RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Code 0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 W hen BF = “High”, indicates that the internal operation is being processed.So during this time the next instruction cannot be accepted. The address Counter (AC) stores DDRAM/CGRAM addresses, transferred from IR. After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1. #" Write Data to CGRAM or DDRAM RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Code 1 0 D7 D6 D5 D4 D3 D2 D1 D0 W rite binary 8-bit data to DDRAM/CGRAM. The selection of RAM from DDRAM, CGRAM, is set by the previous address set instruction : DDRAM address set, CGRAM address set. RAM set instruction can also determine the AC direction to RAM. After write operation, the address is automatically increased/decreased by 1, according to the entry mode. #" Read Data from CGRAM or DDRAM RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Code 1 1 D7 D6 D5 D4 D3 D2 D1 D0 Read binary 8-bit data from DDRAM/CGRAM. The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not performed before this instruction, the data that read first is invalid, because the direction of AC is not determined. If you read RAM data several times without RAM address set instruction before read operation, you can get correct RAM data from the second, but the first data would be incorrect, because there is no time margin to transfer RAM data. In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set instruction : it also transfer RAM data to output data register. After read operation address counter is automatically increased/decreased by 1 according to the entry mode. After CGRAM read operation, display shift may not be executed correctly. * In case of RAM write operation, after this AC is increased/decreased by 1 like read operation. In this time, AC indicates the next address position, but you can read only the previous data by read instruction. V2.0 21/42 2001/03/01 ST7066U !" Reset Function Initializing by Internal Reset Circuit An internal reset circuit automatically initializes the ST7066U when the power is turned on. The following instructions are executed during the initialization. The busy flag (BF) is kept in the busy state until the initialization ends (BF = 1). The busy state lasts for 40 ms after VCC rises to 4.5 V. 1. Display clear 2. Function set: DL = 1; 8-bit interface data N = 0; 1-line display F = 0; 5x8 dot character font 3. Display on/off control: D = 0; Display off C = 0; Cursor off B = 0; Blinking off 4. Entry mode set: I/D = 1; Increment by 1 S = 0; No shift Note: If the electrical characteristics conditions listed under the table Power Supply Conditions Using Internal Reset Circuit are not met, the internal reset circuit will not operate normally and will fail to initialize the ST7066U. For such a case, initialization must be performed by the MPU as explain by the following figure. V2.0 22/42 2001/03/01 ST7066U !" Initializing by Instruction #" 8-bit Interface (fosc=270KHz) POWER ON W ait time >40mS After Vcc >4.5V Function set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 N F X X BF cannot be checked before this instruction. W ait time >37uS Function set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 N F X X BF cannot be checked before this instruction. W ait time >37uS Display ON/OFF control RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 D C B W ait time >37uS Display clear RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 1 W ait time >1.52mS Entry mode set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 I/D S Initialization end V2.0 23/42 2001/03/01 ST7066U $" Initial Program Code Example For 8051 MPU(8 Bit Interface): ;--------------------------------------------------------------------------------INITIAL_START: CALL DELAY40mS MOV CALL CALL MOV CALL CALL MOV CALL CALL MOV CALL CALL A,#38H ;FUNCTION SET WRINS_NOCHK ;8 bit,N=1,5*7dot DELAY37uS A,#38H ;FUNCTION SET WRINS_NOCHK ;8 bit,N=1,5*7dot DELAY37uS A,#0FH WRINS_CHK DELAY37uS A,#01H WRINS_CHK DELAY1.52mS ;DISPLAY ON ;CLEAR DISPLAY MOV A,#06H ;ENTRY MODE SET CALL WRINS_CHK ;CURSOR MOVES TO RIGHT CALL DELAY37uS ;--------------------------------------------------------------------------------MAIN_START: XXXX XXXX XXXX XXXX . . . . ;--------------------------------------------------------------------------------WRINS_CHK: CALL CHK_BUSY WRINS_NOCHK: CLR RS ;EX:Port 3.0 CLR RW ;EX:Port 3.1 SETB E ;EX:Port 3.2 MOV P1,A ;EX:Port 1=Data Bus CLR E MOV P1,#FFH ;For Check Busy Flag RET ;--------------------------------------------------------------------------------CHK_BUSY: ;Check Busy Flag CLR RS SETB RW SETB E JB P1.7,$ CLR E RET V2.0 24/42 2001/03/01 ST7066U #" 4-bit Interface (fosc=270KHz) POWER ON W ait time >40mS After Vcc >4.5V Function set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 X X X X W ait time >37uS BF cannot be checked before this instruction. Function set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 X X X X 0 0 N F X X X X X X W ait time >37uS BF cannot be checked before this instruction. Function set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 X X X X 0 0 N F X X X X X X W ait time >37uS BF cannot be checked before this instruction. Display ON/OFF control RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 X X X X 0 0 1 D C B X X X X W ait time >37uS Display clear RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 X X X X 0 0 0 0 0 1 X X X X W ait time >1.52mS Entry mode set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 X X X X 0 0 0 1 I/D S X X X X Initialization end V2.0 25/42 2001/03/01 ST7066U $" Initial Program Code Example For 8051 MPU(4 Bit Interface): ;------------------------------------------------------------------INITIAL_START: CALL DELAY40mS MOV CALL CALL MOV CALL CALL MOV CALL CALL MOV CALL CALL MOV CALL CALL A,#38H WRINS_ONCE DELAY37uS ;FUNCTION SET ;8 bit,N=1,5*7dot A,#28H ;FUNCTION SET WRINS_NOCHK ;4 bit,N=1,5*7dot DELAY37uS A,#28H ;FUNCTION SET WRINS_NOCHK ;4 bit,N=1,5*7dot DELAY37uS A,#0FH WRINS_CHK DELAY37uS A,#01H WRINS_CHK DELAY1.52mS ;DISPLAY ON ;CLEAR DISPLAY MOV A,#06H ;ENTRY MODE SET CALL WRINS_CHK CALL DELAY37uS ;------------------------------------------------------------------MAIN_START: XXXX XXXX XXXX XXXX . . . . . . . . . . ;------------------------------------------------------------------WRINS_CHK: CALL CHK_BUSY WRINS_NOCHK: PUSH A ANL A,#F0H CLR RS ;EX:Port 3.0 CLR RW ;EX:Port 3.1 SETB E ;EX:Port 3.2 MOV P1,A ;EX:Port1=Data Bus CLR E POP A SWAP A WRINS_ONCE: ANL A,#F0H CLR RS CLR RW SETB E MOV P1,A CLR E MOV P1,#FFH ;For Check Bus Flag RET ;------------------------------------------------------------------CHK_BUSY: ;Check Busy Flag PUSH A MOV P1,#FFH $1 CLR RS SETB RW SETB E MOV A,P1 CLR E MOV P1,#FFH CLR RS SETB RW SETB E NOP CLR E JB A.7,$1 POP A RET . . V2.0 26/42 2001/03/01 ST7066U !" Interfacing to the MPU The ST7066U can send data in either two 4-bit operations or one 8-bit operation, thus allowing interfacing with 4or 8-bit MPU. #" For 4-bit interface data, only four bus lines (DB4 to DB7) are used for transfer. Bus lines DB0 to DB3 are disabled. The data transfer between the ST7066U and the MPU is completed after the 4-bit data has been transferred twice. As for the order of data transfer, the four high order bits (for 8-bit operation, DB4 to DB7) are transferred before the four low order bits (for 8-bit operation, DB0 to DB3). The busy flag must be checked (one instruction) after the 4-bit data has been transferred twice. Two more 4-bit operations then transfer the busy flag and address counter data. $" Example of busy flag check timing sequence RS R/W E Internal operation Functioning DB7 IR7 IR3 AC3 Not Busy AC3 IR7 IR3 Instruction write Busy flag check Busy flag check Instruction write $" Intel 8051 interface 16 COM1 to COM16 P1.0 to P1.3 4 DB4 to DB7 P3.0 P3.1 P3.2 Intel 8051 Serial RS R/W E SEG1 to SEG40 40 ST7066U V2.0 27/42 2001/03/01 ST7066U #" For 8-bit interface data, all eight bus lines (DB0 to DB7) are used. $" Example of busy flag check timing sequence RS R/W E Internal operation Functioning DB7 Data Busy Busy Not Busy Data Instruction write Busy flag check Busy flag check Busy flag check Instruction write $" Intel 8051 interface 16 COM1 to COM16 P1.0 to P1.7 8 DB0 to DB7 P3.0 P3.1 P3.2 Intel 8051 Serial RS R/W E SEG1 to SEG40 40 ST7066U V2.0 28/42 2001/03/01 ST7066U !" Supply Voltage for LCD Drive There are different voltages that supply to ST7066U’s pin (V1 - V5) to obtain LCD drive waveform. The relations of the bias, duty factor and supply voltages are shown as below: Duty Factor 1/8, 1/11 1/16 Bias Supply Voltage V1 V2 V3 V4 V5 1/4 Vcc - 1/4VLCD Vcc - 1/2VLCD Vcc - 1/2VLCD Vcc - 3/4VLCD Vcc - VLCD 1/5 Vcc - 1/5VLCD Vcc - 2/5VLCD Vcc - 3/5VLCD Vcc - 4/5VLCD Vcc- VLCD VCC(+5V) VCC(+5V) VCC R V1 V2 V3 V4 R V5 1/4 bias (1/8, 1/11 duty cycle) VR R VLCD R VCC R V1 V2 V3 V4 R V5 1/5 bias (1/16 duty cycle) VR R VLCD R -5V -5V V2.0 29/42 2001/03/01 ST7066U !" Timing Characteristics #" Writing data from MPU to ST7066U VIH1 RS VIL1 tAS tAH RW tPW tf E tr tDSW tH tAH DB0-DB7 Valid data tC #" Reading data from ST7066U to MPU VIH1 RS VIL1 tAS tAH RW tPW tf E tDDR tr Valid data tC tH tAH DB0-DB7 V2.0 30/42 2001/03/01 ST7066U #" Interface Timing with External Driver tct VOH2 CL1 tCWH tCWH VOL2 CL2 tCST tCWL tct D tDH tSU M tDM V2.0 31/42 2001/03/01 ST7066U !" Characteristics AC (TA = 25℃, VCC = 2.7V) Symbol Characteristics fOSC OSC Frequency Test Condition Internal Clock Operation R = 75KΩ External Clock Operation Min. Typ. Max. 190 270 350 Unit KHz fEX External Frequency Duty Cycle - 125 45 - 270 50 - 410 55 0.2 KHz % µs TR,TF Rise/Fall Time Write Mode (Writing data from MPU to ST7066U) TC TPW TR,TF TAS TAH TDSW TH Enable Cycle Time Pin E 1200 460 0 10 80 10 25 ns ns ns ns ns ns ns Enable Pulse Width Pin E Enable Rise/Fall Time Pin E Address Setup Time Pins: RS,RW,E Address Hold Time Data Setup Time Data Hold Time Pins: RS,RW,E Pins: DB0 - DB7 Pins: DB0 - DB7 Read Mode (Reading Data from ST7066U to MPU) TC TPW TR,TF TAS TAH TDDR TH Enable Cycle Time Pin E 1200 480 0 10 10 25 320 ns ns ns ns ns ns ns Enable Pulse Width Pin E Enable Rise/Fall Time Pin E Address Setup Time Pins: RS,RW,E Address Hold Time Data Setup Time Data Hold Time Pins: RS,RW,E Pins: DB0 - DB7 Pins: DB0 - DB7 Interface Mode with LCD Driver(ST7065) TCWH TCWL TCST TSU TDH TDM Clock Pulse with High Pins: CL1, CL2 Clock Pulse with Low Pins: CL1, CL2 Clock Setup Time Data Setup Time Data Hold Time M Delay Time Pins: CL1, CL2 Pin: D Pin: D Pin: M 800 800 500 300 300 0 2000 ns ns ns ns ns ns V2.0 32/42 2001/03/01 ST7066U !" Characteristics AC (TA = 25℃, VCC = 5V) Symbol Characteristics fOSC OSC Frequency Test Condition Internal Clock Operation R = 91KΩ External Clock Operation Min. Typ. Max. 190 270 350 Unit KHz fEX External Frequency Duty Cycle - 125 45 - 270 50 - 410 55 0.2 KHz % µs TR,TF Rise/Fall Time Write Mode (Writing data from MPU to ST7066U) TC TPW TR,TF TAS TAH TDSW TH Enable Cycle Time Pin E 1200 140 0 10 40 10 25 ns ns ns ns ns ns ns Enable Pulse Width Pin E Enable Rise/Fall Time Pin E Address Setup Time Pins: RS,RW,E Address Hold Time Data Setup Time Data Hold Time Pins: RS,RW,E Pins: DB0 - DB7 Pins: DB0 - DB7 Read Mode (Reading Data from ST7066U to MPU) TC TPW TR,TF TAS TAH TDDR TH Enable Cycle Time Pin E 1200 140 0 10 10 25 100 ns ns ns ns ns ns ns Enable Pulse Width Pin E Enable Rise/Fall Time Pin E Address Setup Time Pins: RS,RW,E Address Hold Time Data Setup Time Data Hold Time Pins: RS,RW,E Pins: DB0 - DB7 Pins: DB0 - DB7 Interface Mode with LCD Driver(ST7065) TCWH TCWL TCST TSU TDH TDM Clock Pulse with High Pins: CL1, CL2 Clock Pulse with Low Pins: CL1, CL2 Clock Setup Time Data Setup Time Data Hold Time M Delay Time Pins: CL1, CL2 Pin: D Pin: D Pin: M 800 800 500 300 300 0 2000 ns ns ns ns ns ns V2.0 33/42 2001/03/01 ST7066U !" Absolute Maximum Ratings Characteristics Power Supply Voltage LCD Driver Voltage Input Voltage Operating Temperature Storage Temperature Symbol VCC VLCD VIN TA TSTO Value -0.3 to +7.0 VCC-10.0 to VCC+0.3 -0.3 to VCC+0.3 -40 C to + 90 C -55 C to + 125 C o o o o !" Characteristics DC ( TA = 25℃ , VCC = 2.7 V – 4.5 V ) Symbol Characteristics VCC VLCD ICC Operating Voltage LCD Voltage Power Supply Current Input High Voltage (Except OSC1) Input Low Voltage (Except OSC1) Input High Voltage (OSC1) Input Low Voltage (OSC1) Output High Voltage (DB0 - DB7) Output Low Voltage (DB0 - DB7) Output High Voltage (Except DB0 - DB7) Output Low Voltage (Except DB0 - DB7) Common Resistance Segment Resistance Input Leakage Current Pull Up MOS Current Test Condition VCC-V5 fOSC = 270KHz VCC=3.0V - Min. Typ. Max. 2.7 3.0 0.1 4.5 10.0 0.25 Unit V V mA VIH1 0.7Vcc - VCC V VIL1 - - 0.3 - 0.6 V VIH2 - 0.7Vcc - VCC V VIL2 - 0.75 Vcc - - 0.2Vcc V VOH1 IOH = -0.1mA - - V VOL1 IOL = 0.1mA - 0.2Vcc V VOH2 IOH = -0.04mA 0.8VCC - VCC V VOL2 RCOM RSEG ILEAK IPUP IOL = 0.04mA VLCD = 4V, Id = 0.05mA VLCD = 4V, Id = 0.05mA VIN = 0V to VCC VCC = 3V -1 -10 2 2 -50 0.2VCC 20 30 1 -120 V KΩ KΩ µA µA V2.0 34/42 2001/03/01 ST7066U !" Characteristics DC ( TA = 25℃, VCC = 4.5 V - 5.5 V ) Symbol Characteristics VCC VLCD ICC Operating Voltage LCD Voltage Power Supply Current Input High Voltage (Except OSC1) Input Low Voltage (Except OSC1) Input High Voltage (OSC1) Input Low Voltage (OSC1) Output High Voltage (DB0 - DB7) Output Low Voltage (DB0 - DB7) Output High Voltage (Except DB0 - DB7) Output Low Voltage (Except DB0 - DB7) Common Resistance Segment Resistance Input Leakage Current Pull Up MOS Current Test Condition VCC-V5 fOSC = 270KHz VCC=5.0V - Min. Typ. Max. 4.5 3.0 0.2 5.5 10.0 0.5 Unit V V mA VIH1 0.7Vcc - VCC V VIL1 - -0.3 - 0.6 V VIH2 - VCC-1 - VCC V VIL2 - - - 1.0 V VOH1 IOH = -0.1mA 3.9 - VCC V VOL1 IOL = 0.1mA - - 0.4 V VOH2 IOH = -0.04mA 0.9VCC - VCC V VOL2 RCOM RSEG ILEAK IPUP IOL = 0.04mA VLCD = 4V, Id = 0.05mA VLCD = 4V, Id = 0.05mA VIN = 0V to VCC VCC = 5V -1 -50 2 2 -110 0.1VCC 20 30 1 -180 V KΩ KΩ µA µA V2.0 35/42 2001/03/01 ST7066U !" LCD Frame Frequency #" Assume the oscillation frequency is 270KHZ, 1 clock cycle time = 3.7us, 1/16 duty; 1/5 bias,1 frame = 3.7us x 200 x 16 = 11840us=11.8ms(84.7Hz) 200 clocks 1 2 3 4 16 1 2 3 4 16 1 2 3 4 16 Vcc V1 V2 COM1 V3 V4 V5 Vcc V1 V2 COM2 V3 V4 V5 Vcc V1 V2 COM16 V3 V4 V5 Vcc V1 V2 SEGx off V3 V4 V5 Vcc V1 V2 SEGx on V3 V4 V5 1 frame V2.0 36/42 2001/03/01 ST7066U #" Assume the oscillation frequency is 270KHZ, 1 clock cycle time = 3.7us, 1/11 duty; 1/4 bias,1 frame = 3.7us x 400 x 11 = 16280us=16.3ms (61.3Hz) 400 clocks 1 2 3 4 11 1 2 3 4 11 1 2 3 4 11 Vcc V1 COM1 V2 V3 V4 V5 Vcc V1 COM2 V2 V3 V4 V5 Vcc V1 COM11 V2 V3 V4 V5 Vcc V1 SEGx off V2 V3 V4 V5 Vcc V1 SEGx on V2 V3 V4 V5 1 frame V2.0 37/42 2001/03/01 ST7066U #" Assume the oscillation frequency is 270KHZ, 1 clock cycle time = 3.7us, 1/8 duty; 1/4 bias,1 frame = 3.7us x 400 x 8 = 11840us=11.8ms (84.7Hz) 400 clocks 1 2 3 4 8 1 2 3 4 8 1 2 3 4 8 Vcc V1 COM1 V2 V3 V4 V5 Vcc V1 COM2 V2 V3 V4 V5 Vcc V1 COM8 V2 V3 V4 V5 Vcc V1 SEGx off V2 V3 V4 V5 Vcc V1 SEGx on V2 V3 V4 V5 1 frame V2.0 38/42 2001/03/01 ST7066U !" Pad Configuration I/O VCC PMOS VCC PMOS VCC PMOS NMOS NMOS Input PAD:E(No Pull up) VCC PMOS VCC Input PAD:RS,R/W(With Pull up) NMOS Output PAD:CL1,CL2,M,D VCC PMOS PMOS VCC VCC Enable PMOS NMOS Data NMOS I/O PAD:DB0-DB7 V2.0 39/42 2001/03/01 ST7066U !" LCD and ST7066U Connection 1. 5x8 dots, 8 characters x 1 line (1/4 bias, 1/8 duty) ST7066U COM1 . . . . . . . . COM8 SEG1 . . . . . SEG40 LCD Panel: 8 Characters x 1 line 2. 5x11 dots, 8 characters x 1 line (1/4 bias, 1/11 duty) ST7066U COM1 . . . . . . . . . . . COM11 SEG1 . . . . . . . . . . SEG40 LCD Panel: 8 Characters x 1 line V2.0 40/42 2001/03/01 ST7066U 3. 5x8 dots, 8 characters x 2 line (1/5 bias, 1/16 duty) COM1 . . . . . . . . COM8 COM9 . . . . . . . . COM16 SEG1 . . . . . . . . . . SEG40 LCD Panel: 8 Characters x 2 line 4. 5x8 dots, 16 characters x 1 line (1/5 bias, 1/16 duty) COM1 . . . . . . . . COM8 SEG1 . . . . . . SEG40 COM9 . . . . . . . . COM16 ST7066U ST7066U LCD Panel: 16 Characters x 1 line V2.0 41/42 2001/03/01 Dot Matrix LCD Panel Com 1-16 DL1 VDD FCS SHL1 SHL2 VSS VEE V1 V2 V3 Seg 1-40 Seg 1-40 DR2 DL2 DR1 DL1 VDD FCS CL1 CL2 M SHL1 SHL2 VSS VEE V4 V5 V6 V1 V2 Seg 1-40 DR2 DL2 DR1 ST7065 ST7065 CL1 CL2 M V3 V4 V5 V6 ST7066U VCC GND CL2 CL1 !" Application Circuit M V1 V2 V3 V4 DB0-DB7 V5 Regsister Vcc(+5V) Regsister Regsister Regsister Regsister VR ST7066U -V or GND To MPU VR=10K~30Kohm V2.0 Note:Regsister=2.2K~10K ohm 42/42 2001/03/01