05018
LCD05C
thru
LCD24C
LOW CAPACITANCE TVS ARRAY
APPLICATIONS
✔ Ethernet - 10/100 Base T ✔ RS-458 ✔ xDSL & ATM ✔ SCSI & USB ✔ Audio/Video I/O Ports
IEC COMPATIBILITY ( EN61000-4)
✔ 61000-4-2 (ESD): Air - 15kV, Contact - 8kV ✔ 61000-4-4 (EFT): 40A - 5/50ns ✔ 61000-4-5 (Surge): 24A, 8/20µs Level 2 (Line-Ground) & Level 3 (Line-Line)
16 PIN DIP
FEATURES
✔ 800 Watts Peak Pulse Power per Line (tp=8/20µs) ✔ Bidirectional Configuration ✔ ESD Protection > 40 kilovolts ✔ Available in 5 Voltage Types: 5V to 24V ✔ Standard Dual-In-Line Package ✔ Protects up to 8 Lines ✔ Low Capacitance: 15pF ✔ RoHS Compliant
MECHANICAL CHARACTERISTICS
✔ ✔ ✔ ✔ Molded 16 Pin Dual-In-Line (DIP) Package Weight 1.2 grams (Approximate) Available in Lead-Free Pure-Tin Plating(Annealed) Solder Reflow Temperature: Pure-Tin - Sn, 100: 260-270°C ✔ Consult Factory for Leaded Device Availability ✔ Flammability Rating UL 94V-0 ✔ Packaging: 25 Pieces Per Tube ✔ Marking: Logo, Part Number, Date Code & Pin One Defined By Dot on Top of Package
PIN CONFIGURATION
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
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DEVICE CHARACTERISTICS
MAXIMUM RATINGS @ 25°C Unless Otherwise Specified
PARAMETER
Peak Pulse Power (tp = 8/20µs) - See Figure 1 Operating Temperature Storage Temperature
SYMBOL
PPP TL TSTG
VALUE
800 -55 to 150 -55 to 150
UNITS
Watts °C °C
ELECTRICAL CHARACTERISTICS PER LINE
PART NUMBER (See Note 1) RATED STAND-OFF VOLTAGE MINIMUM BREAKDOWN VOLTAGE MAXIMUM CLAMPING VOLTAGE (See Fig. 2) @ IP = 1A VC VOLTS 9.8 12.3 19.0 25.5 40.0
@ 25°C Unless Otherwise Specified MAXIMUM LEAKAGE CURRENT MAXIMUM CAPACITANCE TEMPERATURE COEFFICIENT OF V(BR) qV(BR) mV/°C
MAXIMUM CLAMPING VOLTAGE (See Fig. 2)
V WM VOLTS LCD05C LCD08C LCD12C LCD15C LCD24C 5.0 8.0 12.0 15.0 24.0
@ 1mA V(BR) VOLTS 6.0 8.5 13.3 16.7 26.7
@8/20µs VC @ IPP 24V @ 45A 25.5V @ 40A 32V @ 34A 38V @ 27A 48V @ 22A
@VWM ID µA 100 10 4 4 4
0V @ 1 MHz C pF 15 15 15 15 15
3 9 16 17 26
Note 1: Tested on pin pairs 1 & 16, 2 & 15, 3 &14, 4 & 13, 5 & 12, 6 & 11, 7 & 10 and 8 & 9.
10,000
PPP - Peak Pulse Power - Watts
FIGURE 1 PEAK PULSE POWER VS PULSE TIME
IPP - Peak Pulse Current - % of IPP
120 100 80 60 40 20 0 tf
FIGURE 2 PULSE WAVE FORM
Peak Value IPP TEST WAVEFORM PARAMETERS tf = 8µs td = 20µs
800W 8/20µs Waveform 1,000
e-t
100
td = t I /2 PP
10 0.1
1
10 100 td - Pulse Duration - µs
1,000
10,000
0
5
10
15 20 t - Time - µs
25
30
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LCD24C
GRAPHS
FIGURE 3 POWER DERATING CURVE
100 80
% Of Rated Power
Peak Pulse Power 8/20µs
60
40 20 Average Power 0 0 25 50 75 100 125 TL - Lead Temperature - °C 150
FIGURE 4 OVERSHOOT & CLAMPING VOLTAGE FOR LCD05C
25
5 Volts per Division
15
5
-5
-15 ESD Test Pulse: 12 kilovolt, 1/30ns (waveform)
FIGURE 5 TYPICAL CLAMPING VOLTAGE VS PEAK PULSE CURRENT FOR LCD05C
16
VC - Clamping Voltage - Volts
12
8
4
0 0 2 4 6 8 10 12 IPP - Peak Pulse Current - Amps 14 16 18
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LCD24C
APPLICATION NOTE
The LCD Series are low capacitance, bidirectional TVS arrays that are designed to protect I/O or high speed data lines from the damaging effects of ESD or EFT. This product series has a surge capability of 800 Watts PPP per line for an 8/20µs waveshape and offers ESD protection > 40kV. BIDIRECTIONAL COMMON-MODE CONFIGURATION (Figure 1) Ideal for use in USB applications, the LCD Series provides up to eight (8) lines of protection in a common-mode configuration as depicted in Figure 1. Circuit connectivity is as follows: ✔ Pins 2, 3, 4, 5, 6, and 7 are connected to ground. ✔ Pins 15 and 14 connected to Port #1 D- and D+. ✔ Pins 13 and 12 connected to Port #2 D+ and D-. ✔ Pins 11 and 10 connected to Port #3 D+ and D-.
Figure1. Typical Common- Mode USB Protection Circuit
PORT #1 D+
USB OUTPUT CONNECTOR
USB OUTPUT CONNECTOR
PORT #2 D+ D-
CIRCUIT BOARD LAYOUT RECOMMENDATIONS Circuit board layout is critical for Electromagnetic Compatibility (EMC) protection. The following guidelines are recommended: ✔ The protection device should be placed near the input terminals or connectors. By placing the TVS close to the connectors, the device will divert the transient current immediately before it can be coupled into the nearby traces. The path length between the TVS devices and the protected line should be minimized All conductive loops including power and ground loops should be minimized The transient current return path to ground should be kept as short as possible to reduce parasitic inductance. Ground planes should be used whenever possible. For Multilayer PCBs, use ground vias.
D16 15 14 13
USB IC
1
USB OUTPUT CONNECTOR
2
3
4
USB OUTPUT CONNECTOR
D+ D12 PORT #3 1 1 10 9
D+ DPORT #4
✔ ✔ ✔
5
6
7
8
✔
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LCD24C
16 PIN DIP PACKAGE OUTLINE & DIMENSIONS
PACKAGE OUTLINE 16 PIN DIP
A
DIMENSIONS
Orientation Dot (Pin #1) B C F F J 12 Places H L K 16 Places I 12 Places
DIM A B C D E F G H I J K L
MILLIMETERS MIN MAX 7.37 6.10 0.25 0° 0.51 3.17 0.84 TYP 0.38 2.54 TYP
INCHES MIN MAX
G D 16 Places E
0.780 19.8 0.290 0.310 7.87 0.240 0.260 6.60 0.010 0.020 0.50 0° 10° 10° 0.020 0.200 5.08 0.125 0.070 1.78 0.84 TYP 0.033 TYP 0.033 TYP 0.015 0.021 0.53 2.54 TYP 0.100 TYP 0.100 TYP
NOTES: 1. Dimensions are exclusive of mold flash and metal burrs. BULK ORDERING NOMENCLATURE: 1. No Suffix = Product Shipped in Tubes of 25 pcs per Tube. 2. Suffix - LF = Lead-Free, Pure-Tin Plating, i.e., LCD05C-LF.
Outline & Dimensions: Rev 1 - 11/01, 06003
COPYRIGHT © ProTek Devices 2007 SPECIFICATIONS: ProTek reserves the right to change the electrical and or mechanical characteristics described herein without notice (except JEDEC). DESIGN CHANGES: ProTek reserves the right to discontinue product lines without notice, and that the final judgement concerning selection and specifications is the buyer’s and that in furnishing engineering and technical assistance, ProTek assumes no responsibility with respect to the selection or specifications of such products.
ProTek Devices 2929 South Fair Lane, Tempe, AZ 85282 Tel: 602-431-8101 Fax: 602-431-2288 E-Mail: sales@protekdevices.com Web Site: www.protekdevices.com
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