FS8170

FS8170 2.5 GHz Low Power Phase-locked Loop IC Princeton Technology Corp. reserves the right to change the product described in this datasheet. All information contained in this datasheet is subject to change without prior notice. Princeton Technology Corp. assumes no responsibility for the use of any circuits shown in this datasheet. Description The FS8170 IC is a serial data input, fully programmable phase-locked loop with a 2.5 GHz prescaler for use in the local oscillator subsystem of radio transceivers. Multi-modulus division ratios of 32/33 and 64/65 are selectable thru serial programming to enable pulse swallowing operation. When combined with an external VCO, the FS8170 becomes the core of a very low power frequency synthesizer well-suited for mobile communication applications, such as 2.4 GHz ISM-band wireless data links and cellular GSM and PCS. The FS8170 is also pin compatible with Fujitsu’s MB15E07SL IC. Features Maximum input frequency: 2.5 GHz Supply voltage range from 2.4 V to 3.6 V Low current consumption in locked state: 3.5 mA typ. (VCC = VP = 2.7 V, TA = +25 °C) 4.0 mA typ. (VCC = VP = 3.0 V, TA= +25 °C) 10 µA max. in asynchronous power-down mode Digitally-filtered lock detect output 18-bit programmable input frequency divider using ÷ 32/33/64/65 multi-modulus prescaler with divide ratio range from 992 to 65631 for ÷ 32/33 mode and from 4032 to 131135 for ÷ 64/65 mode 14-bit programmable reference frequency divider with divide ratio range from 3 to 16383 Programmable charge pump current: 1.5 mA or 6 mA Pin compatible with Fujitsu MB15E07, MB15E07L, MB15E07SL 16 pin, plastic TSSOP (0.65 mm pitch) Package and Pin Assignment 16 pin, plastic TSSOP (dimensions in mm) XIN XOUT VP VCC DO VSS XFIN FIN 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 φR φP FOLD ZC EN LE DATA CLK HiMARK FS8170 Page 1 July 2005 FS8170 Pin Descriptions Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name XIN XOUT VP VCC DO VSS XFIN FIN CLK DATA LE EN ZC FOLD φP φR I/O I O — — O — I I I I I I I O O O Description Reference crystal oscillator or external clock input with internally biased amplifier Reference crystal oscillator output Power supply voltage for the charge pump Power supply voltage Single-ended charge pump output Ground Complementary input for prescaler (normally ac-bypassed via a capacitor) VCO frequency input with internally biased input amplifier Shift register clock input Serial data input Load enable signal input Power-down control Forced high-impedance control for the charge pump Multiplexed CMOS level output (see Functional Description section for programming information) Phase comparator N-channel open drain output for an external charge pump Phase comparator CMOS inverter output for an external charge pump Functional Block Diagram FIN XFIN N-PRESCALER N-COUNTER φR φP N-LATCH DATA CLK LE EN XIN XOUT CONTROL LOGIC SHIFT REGISTER PFD CHARGE PUMP DO ZC R-LATCH LOCK DETECTOR LD MUX FOLD OSC R-COUNTER Page 2 July 2005 FS8170 Absolute Maximum Ratings VSS = 0 V Parameter Supply voltage range Input voltage range Output voltage range Storage temperature range Soldering temperature range Soldering time range ESD rating (human body mode) Symbol VCC VP VFIN VO VDO TSTG TSLD tSLD Rating VSS – 0.3 to VSS + 4.0 VCC to 6.0 VSS – 0.5 to VDD + 0.5 VSS to VCC VSS to VP –55 to 125 260 4 3500 Unit V V V V V °C °C s eV Recommended Operating Conditions VSS = 0 V Value Parameter Symbol min. VCC Supply voltage range VP Operating temperature TA Vcc –40 – 25 5.5 80 V °C 2.4 typ. 3.0 max. 3.6 V Unit Page 3 July 2005 FS8170 Electrical Characteristics (VCC = VP = 3.0 V, VSS = 0 V, TA = –40 to 85 °C unless otherwise noted) Value Parameter Symbol Condition min. typ. max. Unit GENERAL Power supply current consumption Standby current consumption FIN operating frequency XIN operating frequency Input sensitivity XIN input voltage swing ICC,total ICC,standby fFIN fXIN PFIN VXIN 50 Ω measurement system fin = 2.5 GHz ZC = “H” or open VFIN = 0.3 Vpk-pk sinusoid 50 3 -15 0.5 4 10 2500 40 +2 VCC mA µA MHz MHz dBm Vpk-pk CHARGE PUMP IDOsource RF charge pump output current IDOsink IDOsource IDOsink VDO = VP/2, CS bit = “H” VDO = VP/2, CS bit = “H” VDO = VP/2, CS bit = “L” VDO = VP/2, CS bit = “L” -6 6 -1.5 1.5 mA mA mA mA DIGITAL INTERFACE (DATA, CLK, LE, PS, ZC) High-level input voltage Low-level input voltage High-level input current Low-level input current XIN logic HIGH input current XIN logic LOW input current φP logic LOW output voltage φP logic LOW output current φR logic HIGH output voltage φR logic LOW output voltage φR logic HIGH output current φR logic LOW output current VIH VIL IIH IIL IIH,XIN IIL,XIN VOL IOL VOH VOL IOH IOL VIH = VCC = 3.6V VIL = 0 V, VCC = 3.6V VIH = VDD VIL = 0 V Open drain output Open drain output VCC = VP = 3.0 V, IOH = –1 mA VCC = VP = 3.0 V, IOL = 1 mA VCC = VP = 3.0 V VCC = VP = 3.0 V 1 1 VCC – 0.4 0.4 –1 –100 0.4 –1 –1 0.8×VCC 0.2×VCC V V µA µA µA µA V mA V V mA mA 1 1 100 Page 4 July 2005 FS8170 Electrical Characteristics (VCC = VP = 3.0 V, VSS = 0 V, TA = –40 to 85 °C unless otherwise noted) Value Parameter Symbol Condition min. FOLD logic HIGH output voltage FOLD logic LOW output voltage FOLD logic HIGH output current FOLD logic LOW output current VOH VOL VOH VOL VCC = VP = 3.0 V, IOH = –1 mA VCC = VP = 3.0 V, IOL = 1 mA VCC = VP = 3.0 V VCC = VP = 3.0 V 1 VCC – 0.4 0.4 –1 typ. max. V V mA mA Unit MICROWIRE TIMING DATA to CLK setup time DATA to CLK hold time CLK to LE setup time CLK to LE hold time LE Pulse width tSU1 tHOLD1 tSU2 tHOLD2 tEW 10 10 20 30 50 ns ns ns ns ns Page 5 July 2005 FS8170 Functional Description Programmable Input Frequency Divider The VCO output to the FIN pin is divided by the programmable divider and then internally output to the phase/frequency detector (PFD) as fV. The programmable input frequency divider consists of a multi-modulus (selectable ÷ 32/33 or ÷ 64/65 (M/M+1)) prescaler and a 18-bit N-counter, which is further comprised of a 7-bit swallow A-counter, and a 11-bit main B-counter. The total divide ratio, N, is related to values for M, A, and B through the relation N = (M + 1) × A + M × (B – A) = M × B + A, with B ≥ A . The minimum programmable divisor for continuous counting is given by M × ( M – 1 ) , and is 32 × ( 32 – 1 ) = 992 for the ÷ 32/33 prescaler mode, and is 64 × ( 64 – 1 ) = 4032 for the ÷ 64/65 mode. Hence, the valid total divide ratio range for the input divider is N = 992 to 65631 for the ÷ 32/33 mode and N = 4032 to 131135 for the ÷ 64/65 mode. Programmable Reference Frequency Divider The crystal oscillator output is divided by the programmable reference divider and then internally output to the PFD as fR. The programmable reference frequency divider consists of a 14-bit reference R-counter. Becasue of its specific design, the minimum acceptable divisor for R is 3, and hence the total divide ratio, R, ranges from 3 to 16383. Shift Register Configuration The divide ratios for the input and reference dividers are input using a 19-bit serial interface consisting of separate clock (CLK), data (DATA), and load enable (LE) lines. The format of the serial data is shown in Table 1. The data on the DATA line is written to the shift register on the rising edge of the CLK signal and is input with MSB first, and the last bit is used as the latch select control bit. The data on the DATA line should be changed on the falling edge of CLK, and LE should be held LOW while data is being written to the shift register. Data is transferred from the shift register to one of the frequency divider latches when LE is set HIGH. When the latch select control bit is set LOW, data is loaded to the 18-bit N-counter latch, and when the latch select control bit is set HIGH, the 4 MSBs are recognized as CS, LDS, FC, SW, respectively, and the next 14 data bits are loaded to the 14-bit R-counter latch. The definition of the 4 MSBs will be described in Table 5 and 6. Note that LDS should be set LOW for normal operation. Also, serial input data timing waveforms are shown in Fig. 1. Page 6 July 2005 FS8170 Fig. 1 – Serial data input waveforms DATA tSU1 tSU2 tHOLD1 CLK LE CONTROL BIT 8 7 6 5 4 3 2 1 DATA CLK LE MSB 19 18 17 16 15 14 13 12 11 10 9 Parameter tSU1 tSU2 tHOLD1 Min. 10 20 10 Typ. – – – Max. – – – Unit ns ns ns LSB MSB Table 1: Serial data input format 1 2 A 1 R 1 3 A 2 R 2 4 A 3 R 3 5 A 4 R 4 6 A 5 R 5 7 A 6 R 6 8 A 7 R 7 9 N 1 R 8 10 N 2 R 9 11 N 3 R 10 12 N 4 R 11 13 N 5 R 12 14 N 6 R 13 15 N 7 R 14 16 N 8 S W 17 N 9 F C 18 N 10 L D S 19 N 11 C S C B CB A1 to A7 N1 to N11 R1 to R14 SW FC LDS CS Control bit for selecting the 0:N or 1: R latch Control bits for setting the divide ratio of the programmable swallow counter (0 to 127) Control bits for setting the divide ratio of the programmable main counter (3 to 2047) Control bits for setting the divide ratio of the programmable reference counter (3 to 16383) Control bit for setting the divide ratio of the prescaler (32/33 or 64/65) Control bit for setting the polarity of the phase/frequency detector Control bit for selecting the output for the FOLD pin Control bit for setting the charge pump current level Page 7 July 2005 FS8170 Table 2: Binary 7-bit data format for swallow counter Divide ratio (A) 0 1 . 127 A 7 0 0 . 1 A 6 0 0 . 1 A 5 0 0 . 1 A 4 0 0 . 1 A 3 0 0 . 1 A 2 0 0 . 1 A 1 0 1 . 1 Table 3: Binary 11-bit data format for main counter Divide ratio (B) 3 4 . 2047 N 11 0 0 . 1 N 10 0 0 . 1 N 9 0 0 . 1 N 8 0 0 . 1 N 7 0 0 . 1 N 6 0 0 . 1 N 5 0 0 . 1 N 4 0 0 . 1 N 3 0 1 . 1 N 2 1 0 . 1 N 1 1 0 . 1 Table 4: Binary 14-bit data format for reference counter Divide ratio (R) 3 4 . 16383 R 14 0 0 . 1 R 13 0 0 . 1 R 12 0 0 . 1 R 11 0 0 . 1 R 10 0 0 . 1 R 9 0 0 . 1 R 8 0 0 . 1 R 7 0 0 . 1 R 6 0 0 . 1 R 5 0 0 . 1 R 4 0 0 . 1 R 3 0 1 . 1 R 2 1 0 . 1 R 1 1 0 . 1 Table 5: Data format for 3 optional bits Bit SW CS LDS H 32/33 + 6 mA FO signal L 64/65 + 1.5 mA LD signal Description Prescaler dual-modulus ratio setting Charge pump current setting FOLD output select setting Page 8 July 2005 FS8170 Table 6: Data format for FC bit (LDS = HIGH) FC = HIGH DO fR > fV fR < fV fR = fV H L Z φR L H L φP L Z Z FOLD = fR FOLD DO L H Z FC = LOW φR H L L φP Za L Z FOLD = fV FOLD a. Z denotes high impedance state Phase/Frequency Detector (PFD) The PFD compares an internal input frequency divider output signal, fV, with an internal reference frequency divider output signal, fR, and generates an error signal, DO, which is proportional to the phase error between fV and fR. The DO output is intended for use with a passive filter as shown in Fig. 2 (a). The polarity of DO is selectable by setting the bit FC to high or low. The setting should depend on the frequency-voltage characteristic of external VCO as depicted in Fig. 2 (b). The input/output waveforms for the PFD are shown in Fig. 3. Fig. 2 – Low-pass filter and external VCO frequency-voltage characteristic DO VCO (1) fVCO (2) VDO (a) Passive low-pass filter (b) VCO frequency-voltage characteristic Note: If VCO has a positive tuning curve similiar to trace (1), set FC = “H,” otherwise if the VCO has a negative tuning curve similar to trace (2), set FC = “L.” Page 9 July 2005 FS8170 Fig. 3 – Phase comparator output waveforms fR fV LD [FC=”H”] DO [FC=”L”] DO 1. 2. 3. Pulses of finite width on DO output are generated during locked state to prevent dead zone. A “locked” condition (LD is HIGH) is indicated when the phase error is less than t1 or t2 at least for 3 consecutive comparison cycles, otherwise an “unlocked” condition (LD is LOW) is indicated. The values of t1 and t2 depend on the XIN input frequency: t1 > 2/fosc (e.g. t1 > 250 ns, if fXIN = 8 MHz) t2 > 2/fosc (e.g. t2 > 250 ns, if fXIN = 8 MHz) LD becomes HIGH during power-down mode (when EN is set LOW). 4. Charge Pump (CP) The phase error signal, DO, generated from the PFD will pump charge into an external loop filter, which then converts the charge to produce the VCO’s tuning voltage. With a constant pumping rate, the shift of the VCO’s tuning voltage will be directly proportional to the phase error signal DO. Two pumping rates, 1.5 mA and 6 mA, are provided by the chip and are selectable through the bit CS as defined previously in Table 5. Also, the charge pump characteristics corresponding to both modes are shown in the Typical Characteristics section. The internal charge pump may be turned off by the pin ZC. When ZC is set low, the internal charge pump will stay in its high-impedance state and will not pump any charge into the external LPF. In this case, the user is allowed to utilize one’s own charge pump by two control pins φP and φR which are defined in Table 6. φP and φR are the error signals directly proportional to the positive/negative phase error when FC = “H.” When FC = “L,” the relation becomes negative/positive. Table 7: Setting for the pin ZC ZC H L Do Output Normal output High impedance Page 10 July 2005 FS8170 Multi-function Lock Detect Output (FOLD) A digital lock detect function is included with the phase detector through an internal digital filter to produce a logic level output which is available on the FOLD output pin. The criterion of lock indication depends on the period of the crystal oscillator reference. The lock dectect output is HIGH whenever the phase error between phase detector inputs is less than 2 times of the crystal period for more than three consecutive comparison cycles, otherwise is low. Note that LD becomes HIGH during the power saving mode. The LD output is depicted in Fig. 3 as well. Power-down Control (EN) By setting the pin EN to LOW, the chip enters into power-down mode, reducing the current consumption. During the power-down mode, the phase detector output, DO, is set to its high impedance. Normal operation mode resumes when EN is switched to HIGH. To prove a smooth start-up condition, an intermittent control circuit is activated when the device returns to normal operation. Due to the unknown relationship between fV and fR after returning from power-down, the PFD output is unpredictable and may give rise to a significant jump in the VCO’s frequency which will result in an increased lock-up time. To prevent this, the FS8170 employs an intermittent control circuit to limit the magnitude of the error signal generated by the phase detector when it returns to normal operation, thus ensuring a much quicker return to the fully phase-locked condition. Table 8: Setting for the pin EN EN H L Status Normal operation mode Power-down mode Page 11 July 2005 FS8170 Measurement Circuit Setup The circuit shown in Fig. 4 is used for measuring the input sensitivity of the FIN input of the PLL. Fig. 4 – FIN input sensitivity test circuit 1000pF 1000pF 50Ω FIN XFIN VSS DO VCC VP XOUT XIN 0.1µF 1000pF S.G. 50Ω S.G. 8 7 6 5 4 3 2 1 9 CLK 10 11 12 EN 13 14 15 φP 16 φR DATA LE ZC FOLD From Controller Vcc To Counter Page 12 July 2005 FS8170 Typical Characteristics FIN Input Sensitivity Fig. 5 – Input sensitivity vs. frequency 5 0 -5 FIN Input Sensitivity (Prescaler: 64/65) Sensitivity (dBm) -10 -15 -20 -25 -30 -35 -40 -45 -50 0.0 0.2 0.4 0.6 0.8 1.0 SPEC Vcc=2.4V Vcc=3.0V Vcc=3.6V 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 FIN (GHz) 5 0 -5 FIN Input Sensitivity (Prescaler: 32/33) Sensitivity (dBm) -10 -15 -20 -25 -30 -35 -40 -45 -50 0.0 0.2 0.4 0.6 0.8 1.0 SPEC Vcc=2.4V Vcc=3.0V Vcc=3.6V 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 FIN (GHz) Page 13 July 2005 FS8170 XIN Input Sensitivity Fig. 6 – XIN input sensitivity vs. frequency XIN Input Sensitivity SPEC 10 5 0 -5 -10 -15 -20 -25 -30 -35 0 50 Sensitivity (dBm) Vcc=2.4V Vcc=3.0V Vcc=3.6V 100 150 200 250 XIN (MHz) Page 14 July 2005 FS8170 Charge Pump Characteristic Fig. 7 – Charge pump current vs. VDO 2.0 1.5 1.0 Low Current Mode (Ido=1.5mA) Source State : FR>FV, FC Positive Ido (mA) 0.5 0.0 Sink State : FR>FV , FC Negative -0.5 -1.0 -1.5 -2.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Vdo (V) 8 6 4 Source State : FR>FV, FC Positive High Current Mode (Ido=6mA) Ido (mA) 2 0 -2 -4 -6 -8 0.0 Sink State : FR>FV , FC Negative 0.5 1.0 1.5 2.0 2.5 3.0 Vdo (V) Page 15 July 2005 FS8170 Supply Voltage Dependence of Charge Pump Current Fig. 8 – Charge pump current vs. supply voltage at VDO = VP/2 Low Current Mode (1.5mA mode) VDO = 1/2 VP 2.0 1.9 1.8 1.7 IDO (mA) 1.6 1.5 1.4 1.3 1.2 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 Sink Current Source Current VP (V) 7.2 7.0 6.8 6.6 6.4 VDO = 1/2 VP High Current Mode (6.0mA mode) IDO (mA) 6.2 6.0 5.8 5.6 5.4 5.2 5.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 Sink Current Source Current VP (V) Page 16 July 2005 FS8170 Appication Circuit VP 10K 12K 33pF 12K Xtal XIN XOUT φR φP FOLD ZC EN LE Lock Detect 10K 33pF VP HiMARK FS8170 VP VCC VCC 0.1µF 1µF DO 1000pF VSS XFIN FIN DATA CLK M C U 1000pF VCO Page 17 July 2005