FS8308

FS8308 Low Power PLL Frequency Synthesizer IC Advance Information Princeton Technology Corp. reserves the right to change the product described in this datasheet. All information contained in this datasheet is subject to change without prior notice. Princeton Technology Corp. assumes no responsibility for the use of any circuits shown in this datasheet. Description The FS8308 is a serial data input, phase-locked loop IC with programmable input and reference frequency dividers. When combined with a VCO, this IC becomes the core of a very low power frequency synthesizer well-suited for mobile communication applications, e.x. paging systems and family radio service (FRS). There are some features implemented in this IC, including an 18-bit programmable input frequency divider, a terminal for reference oscillator buffer output, as well as stand-by control through programming, and etc. Details are listed in the following. Features Up to 40 MHz external crystal oscillator reference frequency under normal condition Low current consumption (IDD,total typically 1.2 mA at fFIN = 500 MHz and VDD1 = 1.0 V) With Schmitt trigger added for noise-immune programming input 18-bit programmable input frequency divider (including a ÷ 64/65 prescaler) with divide ratio range from 4032 to 262143 13-bit programmable reference frequency divider (including a ÷ 8 prescaler) with divide ratio range from 40 to 65528 Optional lock detector output (LD, fR/2, fV/2) Charge pump output for passive low-pass filter Wide tuning range of charge pump output for external VCO (VSS+0.5 to VDD2-0.5) Switchover terminal for constant of loop filter or general open drain output Reference oscillator buffer output Programmable stand-by control TSSOP 16L package (0.65mm pitch) Applications Pager Family radio service (FRS) Wireless communication system Page 1 April 2003 Advance Information FS8308 Package and Pin Assignment: 16L, TSSOP XIN XOUT VDD2 NC DO VSS FIN VDD1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 BO TEST SW LE DATA CLK LD NC HiMARK FS8308 Symbols A A1 A2 b C D E E1 e L y θ Dimensions in mm MIN. --0.05 0.80 0.19 0.09 4.90 --4.30 --0.45 --0° NOM. ----1.00 ----5.00 6.40 4.40 0.65 0.60 ----MAX. 1.20 0.15 1.05 0.30 0.20 5.10 --4.50 --0.75 0.10 8° MIN. --0.002 0.031 0.007 0.004 0.193 --0.169 --0.018 --0° Dimensions in inch NOM. ----0.039 ----0.197 0.252 0.173 0.026 0.024 ----MAX. 0.048 0.006 0.041 0.012 0.008 0.201 --0.177 --0.030 0.004 8° Note: Tolerance + 0.1mm unless otherwise specified Page 2 April 2003 Advance Information FS8308 Pin Descriptions Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name XIN XOUT VDD2 NC DO VSS FIN VDD1 NC LD CLK DATA LE SW TEST BO I/O I O POWER NC O GND I POWER NC O I I I O I O Description Reference crystal oscillator or external clock input with internally biased amplifier (any external input to XIN must be ac-coupled) Reference crystal oscillator or external clock output Nominal 3.0 V supply voltage No connection Single-ended charge pump output for passive low-pass filter Ground VCO frequency input with internally biased input amplifier (any external input to FIN must be ac-coupled) Nominal 1.0 V supply voltage No connection Lock detector output (high when PLL is locked) Shift register clock input Serial data input Latch enable input Switchover terminal for constant of loop filter or a general open drain output Test mode control input with internal pull-down resistor Terminal of reference crystal oscillator buffer output Block Diagram FIN DATA CLK LE TEST BO XIN XOUT ÷ 64/65 N-COUNTER N-LATCH CHARGE PUMP DO CONTROL LOGIC SHIFT REGISTER PFD LOCK DETECTOR R-LATCH S-LATCH ÷8 R-COUNTER WINDOW GENERATOR LD SW SW Page 3 April 2003 Advance Information FS8308 Absolute Maximum Ratings VSS = 0 V Parameter Supply voltage Input voltage range Operating temperature range Storage temperature range Soldering temperature range Soldering time range Symbol VDD1 VDD2 VFIN TPS TSTG TSLD tSLD Rating VSS – 0.3 to VSS + 2.0 VSS – 0.3 to VSS + 6.0 VSS – 0.3 to VDD + 0.3 –30 to 60 –40 to 125 255 10 Unit V V V o o o C C C s Recommended Operating Conditions VSS = 0 V Value min. 0.95 2.4 –30 typ. 1.0 3.0 25 max. 2.0 3.6 60 Parameter Symbol VDD1 Unit V V o Supply voltage range VDD2 Operating temperature TA C Page 4 April 2003 Advance Information FS8308 Electrical Characteristics (VDD1 = 0.95 to 2.0 V, VDD2 = 2.4 to 3.6 V, VSS = 0 V, TA = 0 to 60°C unless otherwise noted) Value min. typ. 1.2 max. 1.5 10 20 7 -15 0.3 0.3 VDD0.3 VIL = 0 V VIH = VDD1 VIL = 0 V VIH = VDD1 VDD2 = 3.0V, VDO = 1.5V VDD2 = 3.0V, VDO = 1.5V VOL = 0.4 V VOH = VDD2 – 0.4 V SW = ’L’ VSW = VDD2 = 3.0V SW = ’H’ VSW = VDD2 = 3.0V 2 2 2 2.8 0.1 0.1 10 1.0 1.0 10 10 60 60 500 40 Parameter Symbol Condition VDD1 = 1.0 V fFIN = 500 MHz fXIN =24 MHz PS=”H” PFIN = -15dBm VDD1 = 1.0 V, PS=”L” VDD1 = 1.0 V Unit Current consumption Standby current consumption FIN operating frequency range XIN operating frequency range FIN input voltage swing XIN input voltage swing CLK, DATA, LE logic LOW input voltage CLK, DATA, LE logic HIGH input voltage XIN logic LOW input current XIN logic HIGH input current FIN logic LOW input current FIN logic HIGH input current Charge Pump Drive Current Charge Pump Sink Current LD, FV, FR logic LOW output current LD, FV, FR logic HIGH output current SW logic LOW output current SW logic HIGH output current DATA to CLK setup time CLK to LE setup time Hold time IDD,total IDD,standby fFIN fXIN PFIN VXIN VIL VIH IIL,XIN IIH,XIN IIL,FIN IIH,FIN IDO IDO IOL IOH ISW,OFF ISW,ON tSU1 tSU2 tHOLD mA µA MHz MHz dBm Vpk-pk V V µA µA µA µA mA mA mA mA µA mA µs µs µs Page 5 April 2003 Advance Information FS8308 Functional Description Programmable Input Frequency Divider The VCO input to the FIN pin is divided by the programmable divider and then internally output to the phase/frequency detector (PFD) as fV. The programmable input frequency divider consists of a ÷ 64/65 (P/P+1) dual-modulus prescaler in prior to a 18-bit (N) counter, which is further comprised of a 6-bit swallow (A) counter, and a 12-bit main (B) counter. The total divide ratio, N, is related to values for P, A, and B through the relation N = (P + 1) × A + P × (B – A) = P × B + A, with B ≥ A . The minimum available programmable divisor for continuous counting is given by P × ( P – 1 ) = 64 × 63 = 4032, and the valid total divide ratio range for the input divider is M = 4032 to 262143. Take N=10000 for example, since P=64 and hence that B=156 and A=16. Therefore, the binary codes of B and A should be 0000 1001 1100 and 010000, respectively. An alternative approach is to translate the decimal N into binary code directly. And then just take the last 6-bit as A and the remaining 12-bit as B. By far the binary code of N=10000 is 00 0010 0111 0001 0000. One can get the same result as the former method. Programmable Reference Frequency Divider The crystal oscillator output is divided by the programmable divider and then internally output to the PFD as fR. The programmable reference frequency divider consists of a fixed ÷ 8 (S) prescaler and a 13-bit reference (R) counter. The total divide ratio, T, is related to values for S and R through the relation T = S × R = 8 × R. The usable divisior range of the reference counter is R = 5 to 8191 and therefore, the valid total divide ratio range for the reference divider is T = 40 to 65528 (in steps of 8.) Page 6 April 2003 Advance Information FS8308 Serial Input Data Format The divsors of the input and reference dividers are input using a 20-bit serial interface consisting of separate clock (CLK), data (DATA), and latch enable (LE) lines. The format of the serial data is shown in Fig. 1. The data on the DATA line is written to the shift register on the rising edge of the CLK signal and is input with MSB first. The last two bits are recognized as the latch select control bits. Data on the DATA line should be changed on the falling edge of CLK, and LE should be held low while data is being written to the shift register. Data is transferred from the shift register to either one of the frequency divider latches or the optional control latch when LE is set high. When the latch select control bits are set high-low or low-low, data is loaded to the 18-bit N-counter latch, and when the latch select control bits are set high-high, the 2 MSBs are ignored, the next 13 data bits are loaded to the 13-bit R-counter latch and the remaining 3 LSBs are used to control testing modes and should be set as follows for normal operation: R14 = high, R15 = low, R16 = low. To disable LD output (i.e. set LD low), R14 should be set low. When the latch select control bits are set low-high, the 2 MSBs are recognized as PS and SW, which are used as stand-by control and open drain output control, respectively. The detail of two control bits setting is summarized in Table 1. In normal work condition, PS is set to low. When PS is programmed to high, it will enter stand-by mode. Serial input data timing waveforms are shown in Fig. 2. Fig. 1 – Serial input data format 18-bit data for N-counter 2ND CONTROL BIT 1ST CONTROL BIT R16 R15 R14 13-bit data for R-counter ignored ignored MSB optionalcontrol SW PS Fetching Target of Serial Data Input N-counter PS and SW R-counter LSB Table 1: Control Bit Setting 1st CB X 0 1 2nd CB 0 1 1 Page 7 April 2003 Advance Information Fig. 2 – Serial input data timing waveforms FS8308 DATA tSU1 tSU2 tHOLD CLK LE 1ST CB DATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK LE Page 8 2ND CB MSB LSB April 2003 Advance Information FS8308 Phase/Frequency Detector (PFD) The PFD compares an internal input frequency divider output signal, fV, with an internal reference frequency divider output signal, fR, and generates an error signal, DO, which is proportional to the phase error between fV and fR. The DO output is intended for use with a passive filter as shown in Fig. 2. Lock Detector (LD) When phase comparator detects phase difference, LD terminal outputs “L”. When phase comparator locks, LD terminal outputs “H”. On standby, outputs “H”. The criteria for lock condition is that the phase difference between fV and fR is less than 2/xin and continues for more than three consecutive times. The input/output waveforms for the PFD and LD are shown in Fig. 3. Fig. 2 – Passive low-pass filter circuit DO R1 to VCO C2 C1 Fig. 3 – PFD input/output waveforms 2/xin fR fV high-Z DO high-Z high-Z LD < 2/xin < 2/xin < 2/xin Page 9 April 2003 Advance Information FS8308 Stand-by Mode The stand-by mode for the PLL is entered by programming the PS bit to high. In the standby mode, the XIN and FIN amplifiers, N-counter, and R-counter are stopped, as well as the internal current bias for charge pump block, the N- and R-counters are also reset, and the DO and DB outputs are set to the high impedance state. As long as voltage is supplied to VDD2, data loaded to the latches is kept. To exit from stand-by mode to normal operation, the PS bit must be programmed to low. Reference Crystal Oscillator Buffer Output (BO) This IC provides a reference crystal oscillator buffer output intended to be used as a crystal local oscillator to a 2nd mixer. The terminal is represented as BO. For cases to enhance the buffer output swing, increasing VDD1 will be an efficient way. Filter Switch Control (SW) Control of SW terminal by “SW” bit. This terminal is for switching time-constant of loop filter. Output type of this terminal is open drain output. When constant of loop filter doesn’t change by this switch, general open drain output is available. Note that there is an internal 200Ω resistor connected between and drain terminal and output pin. Page 10 April 2003 Advance Information FS8308 Application Circuit LNA 1st mixer 1st IF amplifier 2nd mixer 2nd IF amplifier Discriminator Wave shaper LPF Frequency multiplier (×4,5) 2nd LO 1st LO XIN XOUT VDD2 NC DO VSS FIN VDD1 BO TEST SW LE DATA CLK LD NC LCD driver RAM ROM HiMARK FS8308 CPU Decoder Driver LCD DC/DC converter Page 11 April 2003 Advance Information FS8308 Typical Characteristics FIN Input Sensitivity vs. Input Frequency 0 -4 -8 -12 -16 -20 -24 -28 -32 -36 -40 Vdd2=3.0V fXIN=24MHz, R=5 Input Sensitivity (dBm) Vdd1=1.0V Vdd1=1.1V Vdd1=1.2V 0 100 200 300 400 500 600 fFIN (MHz) Page 12 April 2003 Advance Information Current Consumption of Idd1 vs. Operating Frequency FS8308 2.0 1.6 Idd1 (mA) 1.2 0.8 0.4 0.0 Vdd2=3.0V, Pfin=-15dBm fXIN=24MHz, R=5 Vdd1=1.0V Vdd1=1.1V Vdd1=1.2V 0 100 200 300 400 fFIN (MHz) 500 600 Current Consumption of Idd2 vs. Supply Voltage Vdd2 0.40 0.36 Idd2 (mA) 0.32 0.28 0.24 0.20 0.16 1.6 2.0 2.4 2.8 3.2 3.6 4.0 Vdd2 (V) Page 13 April 2003 Advance Information Charge Pump Output Characteristics FS8308 1.2 0.8 IDO (mA) 0.4 0.0 -0.4 -0.8 -1.2 FR < FV FR > FV Vdd2=3.0V Drive Current Sink Current 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VDO (V) Charge Pump Output Current vs. Power Supply Voltage 1.1 1.0 0.9 IDO (mA) 0.8 0.7 0.6 0.5 0.4 1.5 Charge Pump Output Current VDO = 1 Vdd2 2 Drive Current Sink Current 2.0 2.5 3.0 Vdd2 (V) 3.5 4.0 Page 14 April 2003 Advance Information FS8308 Single Voltage Operation This IC requires two separate power supplies to operate. If only one voltage source is available, ex. use battery to serve as power source, the user can apply the configuration as shown in the following which is referred to as single voltage operation. POWER SUPPLY VDD2 HiMARK FS8308 R VDD1 Since there is only one voltage source provided in the so-called single voltage configuration, which is directly connected to Vdd2, one needs to choose a reasonable R value to set Vdd1 to operate within the safe region, whose requirement is Vdd1 > 0.95V. Keep in mind that the lower Vdd1 is, the less current this IC will consume, but the poorer crystal buffer output it drives. In order to balance the trade-off between the current consumption and crystal buffer driving capability, Vdd1 is suggested to be about 1.1V. Vdd1 vs. Vdd2 for various R at fin=470MHz is plotted in the following figure. Note that although smaller resistor R makes this IC consume more current, the reward is with wider power supply input range. Typical value of R is recommended to be around 1.6KΩ.. Single Voltage Characteristic: Vdd1 vs. Vdd2 for Various R 1.5 1.4 1.3 Vdd1 (V) 1.2 1.1 1.0 0.9 0.8 1.5 R=1.2K R=1.6K R=1.8K R=2.0K Safe Operation Region fin=470MHz, Pfin=-10dBm xin=24MHz, N=4032, R=5 2.0 2.5 3.0 Vdd2 (V) 3.5 4.0 Page 15 April 2003