ASM2I9940L

April 2007 rev 1.2 Low Voltage 1:18 Clock Distribution Chip Features • • LVPECL or LVCMOS Clock Input 2.5V LVCMOS Outputs for Pentium II Microprocessor Support* • • • • • 150pS Maximum Output-to-Output Skew Maximum Output Frequency of 250MHz 32 Lead LQFP & TQFP Packaging Dual or Single Supply Device Dual VCC Supply Voltage, 3.3V Core and 2.5V Output • • • Single 3.3V VCC Supply Voltage for 3.3V Outputs Single 2.5V VCC Supply Voltage for 2.5V I/O Pin and Function compatible to MPC940L, MPC9109, CY29940 and CY29940-1 ASM2I9940L With low output impedance (≈20Ω), in both the HIGH and LOW logic states, the output buffers of the ASM2I9940L are ideal for driving series terminated transmission lines. With 20Ω output impedance the ASM2I9940L has the capability of driving two series terminated lines from each output. This gives the device an effective fanout of 1:36. The differential LVPECL inputs of the ASM2I9940L allow the device to interface directly with a LVPECL fanout buffer to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS input provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH on the LVCMOS_CLK_Sel pin will select the LVCMOS level clock input. All inputs of the ASM2I9940L have internal open if unused. The ASM2I9940L is a single or dual supply device. The device power supply offers a high degree of flexibility. The device can operate with a 3.3V core and 3.3V output, a 3.3V core and 2.5V outputs as well as a 2.5V core and 2.5V outputs. The 32-lead LQFP and TQFP Packages were chosen to optimize performance, board space and cost of the device. The 32-lead LQFP and TQFP Packages have a 7x7mm2 body size with conservative 0.8mm pin spacing. pullup/pulldown resistor, so they can be left Functional Description The ASM2I9940L is a 1:18 low Voltage Clock distribution chip with 2.5V or 3.3V LVCMOS output capabilities. The device features the capability to select either a differential LVPECL or LVCMOS compatible input. The 18 outputs are 2.5V or 3.3V LVCMOS compatible and feature the drive strength to drive 50Ω series or parallel terminated transmission lines. With output-to-output skews of 150pS, the ASM2I9940L is ideal as a clock distribution chip for the most demanding of Synchronous systems. The 2.5V outputs also make the device ideal for supplying clocks for a high performance microprocessor based design. * Pentium II is a trademark of Intel Corporation PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. April 2007 rev 1.2 Block Diagram PECL_CLK PECL_CLK 0 ASM2I9940L Q0 LVCMOS_CLK LVCMOS_CLK_Sel (Internal Pulldown) Q17 1 16 Q1-Q16 Pin Diagram GNDO 17 16 15 14 ASM2I9940L 13 12 11 10 9 1 2 3 4 5 6 7 8 VCCO Q12 Q13 Q14 GNDO Q15 Q16 Q17 VCCO Q10 19 PECL_CLK Q6 Q7 GNDO Q5 Q4 Q3 VCC0 Q2 Q1 Q0 24 25 26 27 28 29 30 31 32 23 22 Q8 21 20 18 GNDO GNDI LVCMOS_CLK Table 1. Function Table LVCMOS_CLK_Sel 0 1 Input PECL_CLK LVCMOS_CLK LVCMOS_CLK_S l PECL_CLK Table 2. Power Supply Voltages Supply Pin VCCI VCCO VCCI Q11 VCCI Q9 Voltage Level 2.5V or 3.3V ± 5% 2.5V or 3.3V ± 5% Low Voltage 1:18 Clock Distribution Chip Notice: The information in this document is subject to change without notice. 2 of 13 April 2007 rev 1.2 Table 3. Pin Configuration Pin # 5 6 3 4 32,31,30,28,27,26,24,23,22, 20,19,18,15,14,13,11,10,9 2 1,12,17,25 7,21 8, 16,29 ASM2I9940L Pin Name PECL_CLK PECL_CLK LVCMOS_CLK LVCMOS_CLK_Sel Q0–Q17 GNDI GNDO VCCI VCCO I/O Input Input Input Output Type LVPECL LVCMOS LVCMOS LVCMOS Supply Supply Supply Supply Function LVPECL Clock Inputs LVCMOS Clock Input Selects either LVPECL or LVCMOS input as Clock Source Clock Outputs Core Negative Power Supply Output Negative Power Supply Core Positive Power Supply Output Positive Power Supply Table 4. Absolute Maximum Ratings1 Symbol VCC VI IIN TStor Ts TDV Supply Voltage Input Voltage Input Current Storage Temperature Range Max. Soldering Temperature (10 sec) Static Discharge Voltage (As per JEDEC STD22- A114-B) -40 Parameter Min -0.3 -0.3 Max 3.6 VCC + 0.3 ±20 125 260 2 Unit V V mA °C °C KV Note:1. These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Low Voltage 1:18 Clock Distribution Chip Notice: The information in this document is subject to change without notice. 3 of 13 April 2007 rev 1.2 Table 5. DC Characteristics (TA =-40° to +85°C, VCCI = 3.3V ± 5%, VCCO = 3.3V ± 5%) Symbol VIH VIL VPP VCMR VOH VOL IIN CIN Cpd ZOUT ICC ASM2I9940L Characteristic Input HIGH Voltage Input LOW Voltage Peak–to–Peak Input Voltage Common Mode Range Output HIGH Voltage Output LOW Voltage Input Current Input Capacitance Power Dissipation Capacitance Output Impedance Maximum Quiescent Supply Current CMOS_CLK CMOS_CLK PECL_CLK PECL_CLK Min 2.0 Typ Max VCCI 0.8 Unit V V mV V V Condition 500 VCC-1.4 2.4 1000 VCC-0.6 IOH = –20mA IOH = 20mA 0.5 ±200 4.0 10 18 23 0.5 28 1.0 V µA pF pF Ω mA per output Table 6. AC Characteristics (TA = -40° to +85°C, VCCI = 3.3V ± 5%, VCCO = 3.3V ± 5%) Symbol Fmax tPLH tPLH tsk(o) tsk(pp) tsk(pp) tsk(pp) DC tr, tf Characteristic Maximum Input Frequency Propagation Delay Propagation Delay Output-to-output Skew Part-to-Part Skew Part-to-Part Skew Part-to-Part Skew Output Duty Cycle Output Rise/Fall Time PECL_CLK < 150MHz CMOS_CLK < 150MHz PECL_CLK > 150MHz CMOS_CLK > 150MHz PECL_CLK CMOS_CLK PECL_CLK < 150MHz CMOS_CLK < 150MHz PECL_CLK > 150MHz CMOS_CLK > 150MHz PECL_CLK CMOS_CLK fCLK < 134 MHz fCLK 150MHz CMOS_CLK > 150MHz PECL_CLK CMOS_CLK PECL_CLK < 150MHz CMOS_CLK < 150MHz PECL_CLK > 150MHz CMOS_CLK > 150MHz PECL_CLK CMOS_CLK fCLK < 134 MHz fCLK 150MHz CMOS_CLK > 150MHz PECL_CLK CMOS_CLK PECL_CLK < 150MHz CMOS_CLK < 150MHz PECL_CLK > 150MHz CMOS_CLK > 150MHz PECL_CLK CMOS_CLK fCLK < 134 MHz fCLK