ASM3I2508AF-08SR

February 2007 rev 1.4 Peak EMI Reducing Solution Features • • • • • • • • • • • Generates an EMI optimized clocking signal at output. Input frequency – 14.31818MHz. Frequency outputs: 120MHz (modulated) - default. 72MHz (modulated) or 48MHz (modulated) selectable via I2C ± 1% Centre spread. Modulation rate: 40KHz. Byte Write via I2C Supply voltage range 3.3V ± 0.3V. Available in 8-pin SOIC Package. Available in Commercial and Industrial Temperature ranges. ASM3P2508A The ASM3P2508A allows significant system cost savings by reducing the number of circuit board layers and shielding that are required to pass EMI regulations. The ASM3P2508A modulates the output of PLL in order to spread the bandwidth of a synthesized clock, thereby decreasing the peak amplitudes of its harmonics. This results in significantly lower system EMI compared to the typical narrow band signal produced by oscillators and most clock generators. Lowering EMI by increasing a signal’s bandwidth is called spread spectrum clock generation. The ASM3P2508A has a feature to power down the 72MHz/48MHz output by writing data into specific registers in the device via I2C. By writing a ‘0’ into bit 1 of Byte 0, the PLL block generating 72MHz / 48MHz can be powered down. Writing ‘0’ into bit ‘7’ of Byte 1 selects an output of 72 MHz on FOUT2CLK while a ‘1’ at the same Product Description The ASM3P2508A is a versatile spread spectrum frequency modulator. The ASM3P2508A reduces electromagnetic interference (EMI) at the clock source. location selects a 48 MHz clock output. However, the I2C block, crystal oscillator, and the PLL block generating 120MHz would be always running. Block Diagram VDD XIN XOUT Crystal Oscillator PLL 1 FOUT1CLK (120MHz) SCL SDA I2C Interface PLL 2 FOUT2CLK (72 MHz / 48MHz) VSS PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. February 2007 rev 1.4 Pin Configuration XIN XOUT VDD FOUT1CLK 1 2 8 7 ASM3P2508A VSS SCL SDA FOUT2CLK ASM3P2508A 3 4 6 5 Pin Description Pin Name XIN XOUT VDD FOUT1CLK FOUT2CLK SDA SCL VSS Type I O P O O I/O I P Connection to crystal Connection to crystal Description Power supply for the analog and digital blocks Clock output-1 (120MHz) - default Clock output-2 ( 72MHz / 48MHz) I2C Data I2C Clock Ground to entire chip Absolute Maximum Ratings Symbol VDD, VIN TSTG TA Ts TJ TDV Storage temperature Operating temperature Max. Soldering Temperature (10 sec) Junction Temperature Static Discharge Voltage (As per JEDEC STD22- A114-B) Parameter Voltage on any pin with respect to Ground Rating -0.5 to +4.6 -40 to +85 0 to 70 260 150 2 Unit V °C °C °C °C KV Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Operating Conditions Symbol VDD TA FXIN CL Parameter Supply Voltage Ambient Operating Temperature Range Crystal Resonator Frequency Serial Data Transfer Rate Output Driver Load Capacitance Condition / Description 3.3V ± 10% Min 3 -10 10 Typ 3.3 Max Unit V °C MHz Kb/s pF Standard Mode 3.6 +70 14.31818 100 15 Peak EMI Reducing Solution Notice: The information in this document is subject to change without notice. 2 of 9 February 2007 rev 1.4 DC Electrical Characteristics (Test Condition : All the parameters are measured at room temperature (25°C) , unless otherwise stated) ASM3P2508A Parameter Symbol Conditions / Description Min Typ Max Unit Overall Supply Current, VDD =3.3V, FCLK =14.31818MHz, Icc Dynamic CL=15pF Supply Current, IDD VDD = 3.3V, Software Power Down* Static All input pins High-Level Input VIH VDD=3.3V Voltage Low-Level Input VDD=3.3V VIL Voltage High-Level Input IIH Current Low-Level Input IIL Current (pull-up) Clock Outputs (FOUT1CLK, FOUT2CLK) High-Level Output VDD= 3.3V, IOH = 20mA VOH Voltage Low-Level Output VOL VDD= 3.3V, IOL = 20mA Voltage ZOH VO=0.5VDD; output driving high Output Impedance ZOL Vo=0.5VDD; output driving low * FOUT1CLK (120MHz) is functional and not loaded 40 27 49 35 60 43 mA mA 2.0 VSS-0.3 -1 -20 -36 VDD+0.3 0.8 1 -80 V V µA µA V V 2.5 0 - 29 27 3.3 0.4 - Ω AC Electrical Characteristics Parameter Rise Time Fall Time Clock Duty Cycle Frequency Deviation Jitter, Long Term Symbol tr tf tD fD Conditions/ Description FOUT1CLK FOUT2CLK FOUT1CLK VO = 2.0V to 0.8V; CL = 15pF FOUT2CLK Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period VO = 0.8V to 2.0V; CL = 15pF Output Frequency =120MHz Output Frequency =72MHz /48 MHz On rising edges 500 uS apart at 2.5 V relative to an ideal clock, PLL B inactive * On rising edges 500 uS apart at 2.5 V relative to an ideal clock, PLL B active * From rising edge to next rising edge at 2.5 V, PLL B inactive * From rising edge to next rising edge at 2.5 V, PLL B active * Output active from power up, RUN Mode via Software Power Down Min 640 440 660 460 45 - Typ 680 480 720 520 ±2.73 ±1.78 45 165 110 390 125 Max 750 600 800 570 55 - Unit pS pS % % Tj (LT) pS pS µS Jitter, peak to peak Clock Stabilization Time Tj (∆T) tSTB * CL = 15 pF, Fxin = 14.31818MHz Peak EMI Reducing Solution Notice: The information in this document is subject to change without notice. 3 of 9 February 2007 rev 1.4 Typical Crystal Oscillator Circuit ASM3P2508A Crystal R1 = 510Ω C1 = 27 pF C2 = 27 pF Typical Crystal Specifications Fundamental AT cut parallel resonant crystal Nominal Frequency Frequency Tolerance Operating temperature range Storage Temperature Load Capacitance Shunt capacitance ESR 14.31818MHz +/- 50 ppm or better at 25°C -20°C to +85°C -40°C to +85°C 18pF 7 pF maximum 25 Ω Peak EMI Reducing Solution Notice: The information in this document is subject to change without notice. 4 of 9 February 2007 rev 1.4 I2C Serial Interface Information The information in this section assumes familiarity with I2C programming. ASM3P2508A How to program ASM3P2508A through I2C: • • • • • • • • • • Master (host) sends a start bit. Master (host) sends the write address D4 (H). ASM3P2508A device will acknowledge. Master (host) sends the beginning byte location (N = 0, 1). ASM3P2508A device will acknowledge. Master (host) sends a byte count (X = 1,2) ASM3P2508A device will acknowledge. Master (host) starts sending byte N through byte (N+X – 1) ASM3P2508A device will acknowledge each byte one at a time. Master (host) sends a Stop bit. How to Read from ASM3P2508A through I2C: • • • • • • • • • • • Master (host) will send start bit. Master (host) sends the write address D4 (H). ASM3P2508A device will acknowledge. Master (host) sends the beginning byte location (N = 0, 1). ASM3P2508A device will acknowledge. Master (host) will send a separate start bit. Master (host) sends the read address D5 (H). ASM3P2508A device will acknowledge. ASM3P2508A device (X = 1, 2). Master (host) acknowledges. ASM3P2508A device sends byte N through byte (N+X – 1). Master (host) will need to acknowledge each byte. Master (host) will send a stop bit. will send the byte count Controller (Host) Start Bit Slave Address D4(H) ASM3P2508A (slave/receiver) • • Controller (Host) ACK Start Bit ACK Slave Address D4(H) ASM3P2508A (slave/receiver) Beginning byte location (=N) Byte count (=X) ACK Beginning byte (Byte N) ACK Next Byte (Byte N+1) ACK ---------Last Byte (Byte N+X-1) ACK Stop Bit ACK Beginning Byte = N ACK Repeat start Slave address D5(H) ACK Byte Count (= X) ACK Beginning byte N ACK Next Byte N+1 ACK ---------Last Byte (Byte N+X-1) Not Acknowledge Stop Bit Peak EMI Reducing Solution Notice: The information in this document is subject to change without notice. 5 of 9 February 2007 rev 1.4 ASM3P2508A 57 (H). To put ASM3P2508A in ‘power down’ mode, the bit 1 of Byte 0 is to be changed to logic ‘0’. Hence writing a 55 (H) via I2C into Byte 0 would put the device in partial ‘power down’ mode where the PLL block generating 72 MHz / 48 MHz would be powered down while I2C block, crystal oscillator, and the PLL block generating 120 MHz would still be active. The organization of the register bits is as below: An example of a Byte Write via I2C to partially ‘power down’ the device: ASM3P2508A can be partially ‘powered down’ using bit 1 of Byte 0. The organization of the register bits for Byte ‘0’ is given with default values below: 7 6 5 4 Bit 3 2 1 PLL2 1 0 PLL1 1 Resv Resv Resv Resv Resv Resv 0 1 0 1 0 1 7 Resv 0 6 Resv 1 5 Resv 0 4 Resv 1 Bit 3 Resv 0 2 Resv 1 1 PLL2 Enable 0 0 PLL1 Enable 1 Enable Enable The function of partial power down of the device is of interest to us - that is bit 1 of Byte 0. In the default mode this bit is logic ‘1’. As such, the Byte 0 default value is Byte 0 Power up default 48_MHz Mode Power down PLL with 72MHz Power down PLL with 48MHz 6F(H) 6F(H) 6D(H) 6D(H) Byte 1 3F(H) BF(H) 3F(H) BF(H) FOUT1CLK (MHz) 120 120 120 120 FOUT2CLK(MHz) 72 48 - Figure showing a complete data transfer: . Peak EMI Reducing Solution Notice: The information in this document is subject to change without notice. 6 of 9 February 2007 rev 1.4 Package Information ASM3P2508A 8-lead (150-mil) SOIC Package E H D A2 A θ e B A 1 C L D Dimensions Symbol Min A1 A A2 B C D E e H L θ Inches Max 0.010 0.069 0.059 0.020 0.010 0.004 0.053 0.049 0.012 0.007 Millimeters Min Max 0.10 1.35 1.25 0.31 0.18 4.90 BSC 3.91 BSC 1.27 BSC 6.00 BSC 0.41 0° 1.27 8° 0.25 1.75 1.50 0.51 0.25 0.193 BSC 0.154 BSC 0.050 BSC 0.236 BSC 0.016 0° 0.050 8° Peak EMI Reducing Solution Notice: The information in this document is subject to change without notice. 7 of 9 February 2007 rev 1.4 Ordering Codes Part number ASM3P2508AG-08ST ASM3P2508AG-08SR ASM3I2508AG-08ST ASM3I2508AG-08SR ASM3P2508AF-08ST ASM3P2508AF-08SR ASM3I2508AF-08ST ASM3I2508AF-08SR ASM3P2508A Marking 3P2508AG 3P2508AG 3I2508AG 3I2508AG 3P2508AF 3P2508AF 3I2508AF 3I2508AF Package Configuration 8-PIN SOIC, TUBE, Green 8-PIN SOIC, TAPE AND REEL, Green 8-PIN SOIC, TUBE, Green 8-PIN SOIC, TAPE AND REEL, Green 8-PIN SOIC, TUBE, Pb Free 8-PIN SOIC, TAPE AND REEL, Pb Free 8-PIN SOIC, TUBE, Pb Free 8-PIN SOIC, TAPE AND REEL, Pb Free Temperature Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Device Ordering Information ASM3P2508AF-08 SR R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE, LEAD FREE, and RoHS U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved PulseCore Semiconductor Mixed Signal Product Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. Peak EMI Reducing Solution Notice: The information in this document is subject to change without notice. 8 of 9 February 2007 rev 1.4 ASM3P2508A PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 Copyright © PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: ASM3P2508A Document Version: v1.3 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 © Copyright 2007 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use Peak EMI Reducing Solution Notice: The information in this document is subject to change without notice. 9 of 9