ASM5I2308AG-2-16-TT

November 2006 rev 1.5 3.3V Zero-Delay Buffer General Features • Zero input - output propagation delay, adjustable by capacitive load on FBK input. • Multiple configurations - Refer “ASM5P2308A Configurations “ Table. • • Input frequency range: 15MHz to 133MHz Multiple low-skew outputs. • • • Output-output skew less than 200 pS. Device-device skew less than 700 pS. Two banks of four outputs, three-stateable by two select inputs. • Less than 200 pS cycle-to-cycle jitter (-1, -1H, -2, -3, -4, -5H). • • • • Available in 16-pin SOIC and TSSOP packages. 3.3V operation. Advanced 0.35µ CMOS technology. Industrial temperature available. The ASM5P2308A is ASM5P2308A the Select Input Decoding Table. If all the output clocks are not required, Bank B can be three-stated. The select input also allows the input clock to be directly applied to the outputs for chip and system testing purposes. Multiple ASM5P2308A devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guaranteed to be less than 700 pS. available in five different configurations(Refer “ASM5P2308A Configurations” Table). The ASM5P2308A-1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The ASM5P2308A-1H is the high-drive version of the -1 and the rise and fall times on this device are much faster. Functional Description ASM5P2308A is a versatile, 3.3V zero-delay buffer designed to distribute high-speed clocks. It is available in a 16-pin package. The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback is required to be driven to FBK pin, and can be obtained from one of the outputs. The input-to-input propagation delay is guaranteed to be less than 350 pS, and the output-to-output skew is guaranteed to be less than 250 pS. The ASM5P2308A-2 allows the user to obtain 2X and 1X frequencies on each output bank. The exact configuration and output frequencies depends on which output drives the feedback pin. The ASM5P2308A-3 allows the user to obtain 4X and 2X frequencies on the outputs. The ASM5P2308A-4 enables the user to obtain 2X clocks on all outputs. The ASM5P2308A-5H is a high-drive version with REF/2 on both banks. Thus, the part is extremely versatile, and The ASM5P2308A has two banks of four outputs each, which can be controlled by the select inputs as shown in can be used in a variety of applications. PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. November 2006 rev 1.5 Block Diagram ASM5P2308A /2 REF /2 FBK PLL MUX CLKA1 Extra Divider (-5H) Extra Divider (-3, -4) CLKA2 CLKA3 CLKA4 S2 Select Input Decoding S1 /2 CLKB1 Extra Divider (-2, -3) CLKB2 CLKB3 CLKB4 Select Input Decoding for ASM5P2308A S2 0 0 1 1 S1 0 1 0 1 Clock A1 - A4 Three-state Driven Driven 1 Clock B1 - B4 Three-state Three-state Driven Driven Output Source PLL PLL Reference PLL PLL Shut-Down Y N Y N Driven ASM5P2308A Configurations Device ASM5P2308A-1 ASM5P2308A-1H ASM5P2308A-2 ASM5P2308A-2 ASM5P2308A-3 ASM5P2308A-3 ASM5P2308A-4 ASM5P2308A-5H Feedback From Bank A or Bank B Bank A or Bank B Bank A Bank B Bank A Bank B Bank A or Bank B Bank A or Bank B Bank A Frequency Reference Reference Reference 2 X Reference 2 X Reference 4 X Reference 2 X Reference Reference /2 Bank B Frequency Reference Reference Reference /2 Reference Reference or Reference2 2 X Reference 2 X Reference Reference /2 Note: 1. Outputs are non- inverted on 2308A-2 and 2308A-3 in bypass mode, S2 = 1 and S1 = 0. 2. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the ASM5P2308A-2. 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 2 of 17 November 2006 rev 1.5 Zero Delay and Skew Control All outputs should be uniformly loaded to achieve Zero Delay between input and output. ASM5P2308A 1500 1000 REF- Input to CLKA/CLKB Delay 500 0 -30 -500 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 -1000 -1500 Output Load Difference: FBK Load - CLKA/CLKB Load (pF) To close the feedback loop of the ASM5P2308A, the FBK pin can be driven from any of the eight available output pins. The output driving the FBK pin will be driving a total load of 7 pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input output delay. This is shown in the above graph. For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. For zero output-output skew, be sure to load outputs equally. 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 3 of 16 November 2006 rev 1.5 ASM5P2308A Pin Configuration REF 1 CLKA1 2 CLKA2 3 VDD 4 ASM5P2308A GND 5 CLKB1 6 CLKB2 7 S2 8 16 FBK 15 CLKA4 14 CLKA3 13 VDD 12 GND 11 CLKB4 10 CLKB3 9 S1 Pin Description for ASM5P2308A Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name REF 3 Description Input reference frequency, 5V tolerant input Buffered clock output, bank A Buffered clock output, bank A 3.3V supply Ground Buffered clock output, bank B Buffered clock output, bank B Select input, bit 2 Select input, bit 1 Buffered clock output, bank B Buffered clock output, bank B Ground 3.3V supply Buffered clock output, bank A Buffered clock output, bank A PLL feedback input CLKA14 CLKA2 VDD GND CLKB14 CLKB2 S2 5 S1 5 CLKB3 4 CLKB4 GND VDD CLKA3 4 CLKA4 FBK 4 4 4 4 Notes: 3. Weak pull-down. 4. Weak pull-down on all outputs. 5. Weak pull-up on these inputs. 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 16 of 16 November 2006 rev 1.5 Absolute Maximum Ratings Parameter Supply Voltage to Ground Potential DC Input Voltage (Except REF) DC Input Voltage (REF) Storage Temperature Max. Soldering Temperature (10 sec) Junction Temperature Static Discharge Voltage (As per JEDEC STD22- A114-B) ASM5P2308A Min -0.5 -0.5 -0.5 -65 Max +7.0 VDD + 0.5 7 +150 260 150 2 Unit V V V °C °C °C KV Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device reliability. Operating Conditions for ASM5P2308A Commercial Temperature Devices Parameter VDD TA CL CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100MHz Load Capacitance, from 100MHz to 133MHz Input Capacitance 6 Description Min 3.0 0 Max 3.6 70 30 10 7 Unit V °C pF pF pF Note: 6. Applies to both Ref Clock and FBK. Electrical Characteristics for ASM5P2308A Commercial Temperature Devices Parameter VIL VIH IIL IIH VOL VOH Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage 7 Output HIGH Voltage 7 VIN = 0V VIN = VDD Test Conditions Min 2.0 Max 0.8 50.0 100.0 0.4 Unit V V µA µA V V IOL = 8mA (-1, -2, -3, -4) IOH = 12mA (-1H, -5H) IOL = -8mA (-1, -2, -3, -4) IOH = -12mA (-1H, -5H) Unloaded outputs 100MHz REF (-2,-3,-4) (-1H,-5H) 2.4 49 60 34 18 mA IDD Supply Current8 Select inputs at VDD or GND Unloaded outputs, 66MHz REF (-1, -2, -3, -4) Unloaded outputs, 33MHz REF (-1, -2, -3, -4) Note: 7. Parameter is guaranteed by design and characterization. Not 100% tested in production. 8. Supply Currents are measured for PLL-Bypass Mode (S2=1, S1=0) 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 16 of 16 November 2006 rev 1.5 Switching Characteristics for ASM5P2308A Commercial Temperature Devices Parameter 1/t1 1/t1 t1/ ASM5P2308A Description Output Frequency Output Frequency Output Frequency Duty Cycle = (t2 / t1) * 100 (-1, -2, -3, -4, -1H, -5H) Duty Cycle = (t2 / t1) * 100 (-1, -2, -3, -4, -1H, -5H) Output Rise Time (-1, -2, -3, -4) Output Rise Time (-1, -2, -3, -4) Output Rise Time (-1H, -5H) Output Fall Time (-1, -2, -3, -4) Output Fall Time (-1, -2, -3, -4) Output Fall Time (-1H, -5H) Output-to-output skew on same bank (-1, -2, -3, -4) (-1H, -5H) Output bank A -to- output Bank B skew (-1, -4, -5H) Output bank A -to- output Bank B skew (-2, -3) Delay, REF Rising Edge to FBK Rising Edge 9 9 9 9 9 9 9 9 9 9 9 Test Conditions 30pF load, All devices 20pF load, -1H, -5H devices 8 Min 15 15 15 40.0 45.0 Typ Max 100 133 133 Unit MHz MHz MHz % % nS nS nS nS nS nS pS 15pF load, -1, -2, -3, -4 devices Measured at 1.4V, FOUT =