ASM5I23S08AF-1H-16-TT

November 2006 rev 1.5 ASM5P23S08A 3.3V ‘SpreadTrak’ Zero Delay Buffer General Features • • • • Zero input - output propagation delay, adjustable by capacitive load on FBK input. Multiple configurations Refer “ASM5P23S08A Configurations” Table. Input frequency range: 15MHz to 133MHz Multiple low-skew outputs. • Output-output skew less than 200pS. • Device-device skew less than 700pS. • Two banks of four outputs, tri-stateable by two select inputs. • • • • • • Less than 200pS cycle-to-cycle jitter (-1, -1H, -2, -3, -4, -5H). Available in 16 pin SOIC and TSSOP Packages. 3.3V operation. Advanced 0.35µ CMOS technology. Industrial temperature available. ‘SpreadTrak’. The ASM5P23S08A has two banks of four outputs each, which can be controlled by the select inputs as shown in the Select Input Decoding Table. The select input also allows the input clock to be directly applied to the outputs for chip and system testing purposes. Multiple ASM5P23S08A devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guaranteed to be less than 700pS. The ASM5P23S08A (Refer is available in five different configurations “ASM5P23S08A Configurations Table). The ASM5P23S08A-1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The ASM5P23S08A-1H is the high-drive version of the -1 and the rise and fall times on this device are faster. The ASM5P23S08A-2 allows the user to obtain 2X and 1X frequencies on each output bank. The exact configuration and output frequencies depends on which output drives the feedback pin. The ASM5P23S08A-3 allows the user to obtain 4X and 2X frequencies on the outputs. The ASM5P23S08A-4 enables the user to obtain 2X clocks on all outputs. Thus, the part is extremely versatile, and can be used in a variety of applications. The ASM5P23S08A-5H is a high-drive version with REF/2 on both banks Functional Description ASM5P23S08A is a versatile, 3.3V zero-delay buffer designed to distribute high-speed clocks. It is available in a 16 pin package. The part has an on-chip PLL, which locks to an input clock, presented on the REF pin. The PLL feedback is required to be driven to FBK pin, and can be obtained from one of the outputs. The input-to-output propagation delay is guaranteed to be less than 350pS, and the output-to-output skew is guaranteed to be less than 250pS. PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. November 2006 rev 1.5 Block Diagram FBK PLL MUX ASM5P23S08A /2 REF /2 CLKA1 Extra Divider (-5H) Extra Divider (-3, -4) CLKA2 CLKA3 CLKA4 S2 Select Input Decoding S1 /2 CLKB1 Extra Divider (-2, -3) CLKB2 CLKB3 CLKB4 ASM5P23S08A Select Input Decoding for ASM5P23S08A S2 0 0 1 1 S1 0 1 0 1 Clock A1 - A4 Three-state Driven Driven 1 Clock B1 - B4 Three-state Three-state Driven Driven Output Source PLL PLL Reference PLL PLL Shut-Down Y N Y N Driven ASM5P23S08A Configurations Device ASM5P23S08A-1 ASM5P23S08A-1H ASM5P23S08A-2 ASM5P23S08A-2 ASM5P23S08A-3 ASM5P23S08A-3 ASM5P23S08A-4 ASM5P23S08A-5H Feedback From Bank A or Bank B Bank A or Bank B Bank A Bank B Bank A Bank B Bank A or Bank B Bank A or Bank B Bank A Frequency Reference Reference Reference 2 X Reference 2 X Reference 4 X Reference 2 X Reference Reference /2 Bank B Frequency Reference Reference Reference /2 Reference Reference or Reference2 2 X Reference 2 X Reference Reference /2 Note: 1. Outputs are non- inverted on 23S08A-2 and 23S08A-3 in bypass mode, S2 = 1 and S1 = 0. 2. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the ASM5P23S08A-2. 3.3V ‘SpreadTrak’ Zero Delay Buffer Notice: The information in this document is subject to change without notice. 2 of 17 November 2006 rev 1.5 ASM5P23S08A ‘SpreadTrak’ Many systems being designed now utilize a technology called Spread Spectrum Frequency Timing Generation. ASM5P23S08A is designed so as not to filter off the Spread Spectrum feature of the Reference input, assuming it exists. When a zero delay buffer is not designed to pass the Spread Spectrum feature through, the result is a significant amount of tracking skew which may cause problems in the systems requiring synchronization. Zero Delay and Skew Control All outputs should be uniformly loaded to achieve Zero Delay between input and output. 1500 REF-Input to CLKA/LKB Delay (pS) 1000 500 0 -30 -500 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 -1000 -1500 Output Load Difference: FBK Load - CLKA/CLKB Load (pF) To close the feedback loop of the ASM5P23S08A, the FBK pin can be driven from any of the eight available output pins. The output driving the FBK pin will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input output delay. This is shown in the above graph. For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. For zero output-output skew, make sure to load outputs equally. 3.3V ‘SpreadTrak’ Zero Delay Buffer Notice: The information in this document is subject to change without notice. 3 of 17 November 2006 rev 1.5 Pin Configuration REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2 1 2 3 4 5 6 7 8 16 15 14 FBK CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1 ASM5P23S08A ASM5P2308A 13 12 11 10 9 Pin Description for ASM5P23S08A Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name REF3 CLKA14 CLKA24 VDD GND CLKB14 CLKB24 S25 S15 CLKB34 CLKB44 GND VDD CLKA34 CLKA44 FBK Description Input reference frequency, 5V tolerant input Buffered clock output, bank A Buffered clock output, bank A 3.3V supply Ground Buffered clock output, bank B Buffered clock output, bank B Select input, bit 2 Select input, bit 1 Buffered clock output, bank B Buffered clock output, bank B Ground 3.3V supply Buffered clock output, bank A Buffered clock output, bank A PLL feedback input Notes: 3. Weak pull-down. 4. Weak pull-down on all outputs. 5. Weak pull-up on these inputs. 3.3V ‘SpreadTrak’ Zero Delay Buffer Notice: The information in this document is subject to change without notice. 4 of 17 November 2006 rev 1.5 Absolute Maximum Ratings Parameter Supply Voltage to Ground Potential DC Input Voltage (Except REF) DC Input Voltage (REF) Storage Temperature Max. Soldering Temperature (10 sec) Junction Temperature Static Discharge Voltage (As per JEDEC STD22- A114-B) ASM5P23S08A Min -0.5 -0.5 -0.5 -65 Max +7.0 VDD + 0.5 7 +150 260 150 2000 Unit V V V °C °C °C V Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device reliability. Operating Conditions for ASM5P23S08A Commercial Temperature Devices Parameter VDD TA CL CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100MHz Load Capacitance, from 100MHz to 133MHz Input Capacitance6 Description Min 3.0 0 Max 3.6 70 30 10 7 Unit V °C pF pF pF Note: 6. Applies to both Ref Clock and FBK. 3.3V ‘SpreadTrak’ Zero Delay Buffer Notice: The information in this document is subject to change without notice. 5 of 17 November 2006 rev 1.5 Electrical Characteristics for ASM5P23S08A Commercial Temperature Devices Parameter VIL VIH IIL IIH VOL ASM5P23S08A Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage 7 VIN = 0V VIN = VDD Test Conditions Min Max 0.8 Unit V V 2.0 50.0 100.0 0.4 µA µA V IOL = 8 mA (-1, -2, -3, -4) IOH = 12 mA (-1H, -5H) IOL = -8 mA (-1, -2, -3, -4) IOH = -12 mA (-1H, -5H) Unloaded outputs 100MHz REF, Select inputs at VDD or GND (-2,-3,-4) (-1H,-5H) (-1, -2, -3, -4) (-1, -2, -3, -4) 2.4 VOH Output HIGH Voltage 7 V 49 60 34 18 IDD Supply Current8 Unloaded outputs, 66MHz REF Unloaded outputs, 33MHz REF mA Note: 7. Parameter is guaranteed by design and characterization. Not 100% tested in production. 8. Supply Currents are measured for PLL-Bypass Mode (S2=1, S1=0) 3.3V ‘SpreadTrak’ Zero Delay Buffer Notice: The information in this document is subject to change without notice. 6 of 17 November 2006 rev 1.5 Switching Characteristics for ASM5P23S08A Commercial Temperature Devices Parameter 1/t1 1/t1 1/t1 Description Output Frequency Output Frequency Output Frequency Duty Cycle = (t2 / t1) * 100 (-1, -2, -3, -4, -1H, -5H) Duty Cycle = (t2 / t1) * 100 (-1, -2, -3, -4, -1H, -5H) t3 t3 t3 t4 t4 t4 Output Rise Time ( -2, -3, -4) Output Rise Time ( -2, -3, -4) Output Rise Time ( -5H) Output Fall Time ( -2, -3, -4) Output Fall Time ( -2, -3, -4) Output Fall Time ( -5H) Output-to-output skew on same 9 bank ( -2, -3, -4) Output-to-output skew ( -5H) t5 Output bank A -to- output bank B skew ( -4, -5H) Output bank A -to- output bank B skew (-2, -3) t6 t7 Delay, REF Rising Edge to FBK 9 Rising Edge Device-to-Device Skew 9 9 9 9 9 9 9 9 9 ASM5P23S08A Test Conditions 30pF load, All devices 20pF load, -5H devices 8 Min 15 15 15 40.0 Typ Max 100 133 133 Unit MHz MHz MHz % 15pF load, -2, -3, -4 devices Measured at 1.4V, FOUT =