PCS2P3805AG-20-AT

September 2006 rev 0.3 3.3V CMOS Buffer Clock Driver Features • • • • • • • • • • • Advanced CMOS Technology Guaranteed low skew < 500pS (max.) Very low duty cycle distortion < 1.0nS (max) Very low CMOS power levels TTL compatible inputs and outputs Inputs can be driven from 3.3V or 5V components Two independent output banks with 3-state control 1:5 fanout per bank "Heartbeat" monitor output VCC = 3.3V ± 0.3V Available in SSOP, SOIC and QSOP Packages PCS2P3805A Functional Description The PCS2P3805A is a 3.3V, non-inverting clock driver built using advanced CMOS technology. The device consists of two banks of drivers, each with a 1:5 fanout and its own output enable control. The device has a "heartbeat" monitor for diagnostics and PLL driving. The MON output is identical to all other outputs and complies with the output specifications in this document. The PCS2P3805A offers low capacitance inputs. The PCS2P3805A is designed for high speed clock distribution where signal quality and skew are critical. The PCS2P3805A also allows single point-to-point transmission line driving in applications such as address distribution, where one signal must be distributed to multiple receivers with low skew and high signal quality. Block Diagram OEA INA 5 OA1 – OA5 INB OEB 5 OB1 – OB5 MON PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. September 2006 rev 0.3 Pin Diagram PCS2P3805A VCCA OA1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 VCCB OB1 OB2 OB3 GNDB OB4 OB5 MON OEB INB OA2 OA3 GNDA OA4 OA5 GNDQ OEA INA PCS2P3805A 16 15 14 13 12 11 Pin Description Pin # 9,12 10,11 2,3,4,6,7 19,18,17,15,14 1 20 5 16 8 13 Pin Names OEA, OEB ¯¯ ¯¯ INA, INB OA1-OA5 OB1-OB5 VCCA VCCB GNDA GNDB GNDQ MON Description 3-State Output Enable Inputs (Active LOW) Clock Inputs Clock Outputs Clock Outputs Power supply for Bank A Power supply for Bank B Ground for Bank A Ground for Bank B Ground Monitor Output 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 2 of 12 September 2006 rev 0.3 Function Table Inputs OEA, OEB ¯¯ ¯¯ L L H H Note: H = HIGH; L = LOW; Z = High-Impedance PCS2P3805A Outputs INA, INB L H L H OAn, OBn L H Z Z MON L H L H Capacitance (TA = +25°C, f = 1.0MHz) Symbol CIN COUT Parameter1 Input Capacitance Output Capacitance Conditions VIN= 0V VOUT = 0V Typ 4.5 5.5 Max 6 8 Unit pF pF Note: 1 This parameter is measured at characterization but not tested. Absolute Maximum Ratings1 Symbol VTERM 2 Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND DC Output Current Storage Temperature Junction Temperature Max. Soldering Temperature (10 sec) Static Discharge Voltage (As per JEDEC STD22- A114-B) Max -0.5 to +4.6 -0.5 to +7 -0.5 to VCC+0.5 -60 to +60 -65 to +150 150 260 2 Unit V V V mA °C °C °C KV VTERM3 4 VTERM IOUT TSTG TJ Ts TDV Note: 1 These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. 2. VCC terminals. 3. Input terminals. 4. Outputs and I/O terminals. 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 3 of 12 September 2006 rev 0.3 DC Electrical Characteristics over Operating Range Following Conditions Apply Unless Otherwise Specified Commercial: TA = 0°C to +70°C, VCC = 3.3V ± 0.3V; Industrial: TA = -40 0°C to +85°C, VCC = 3.3V ± 0.3V PCS2P3805A Symbol VIH Parameter Input HIGH Level (Input pins) Input HIGH Level (I/O pins) Test Conditions1 Guaranteed Logic HIGH Level Min 2 2 Typ2 Max 5.5 VCC+ 0.5 0.8 ±1 ±1 ±1 ±1 ±1 ±1 Unit V VIL IIH Input LOW Level (Input and I/O pins) Input HIGH Current (Input pins) Input HIGH Current (I/O pins) Guaranteed Logic LOW Level VCC= Max. VI = 5.5V VI = VCC VCC= Max. VI = GND VI = GND VO = VCC VO = GND -0.5 V µA IIL IOZH IOZL VIK IODH IODL VOH Input LOW Current (Input pins) Input LOW Current (I/O pins) High Impedance Output Current VCC= Max. (3-State Output Pins) Clamp Diode Voltage Output HIGH Current Output LOW Current Output HIGH Voltage µA V mA mA V VCC= Min., IIN = -18mA VCC= 3.3V, VIN = VIH or 3 VIL, VO = 1.5V VCC= 3.3V, VIN = VIH or 3 VIL, VO = 1.5V VCC= Min. VIN = VIH or VIL IOH= -0.1mA IOH= -8mA IOL= 0.1mA -36 50 VCC–0.2 2.45 -0.7 -60 90 -1.2 -110 200 3 0.2 0.2 0.3 0.4 0.5 ±1 µA mA mV 10 µA V VOL Output LOW Voltage VCC= Min. VIN = VIH or VIL IOL= 16mA IOL= 24mA IOFF IOS VH ICCL ICCH ICCZ Input Power Off Leakage Short Circuit Current Input Hysteresis Quiescent Power Supply Current 4 VCC= 0V, VIN = 4.5V VCC= Max., VO = GND 3 -60 -135 150 -240 VCC= Max. VIN = GND or VCC 0.1 Notes:1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC - 0.6V at rated current. 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 4 of 12 September 2006 rev 0.3 Power Supply Characteristics Symbol ∆ICC PCS2P3805A Parameter Quiescent Power Supply Current TTL Inputs HIGH Test Conditions1 VCC= Max. VIN = VCC –0.6V 3 Min Typ2 10 Max 30 Unit µA ICCD Dynamic Power Supply Current 4 VCC= Max. Outputs Open ¯¯ OEA = OEB= GND ¯¯ Per Output Toggling 50% Duty Cycle VIN= VCC VIN= GND 0.035 0.06 mA/ MHz VIN= VCC VCC= Max. VIN= GND Outputs Open fO= 25MHz 50% Duty Cycle OEA = OEB= VCC ¯¯ ¯¯ VIN= VCC-0.6V Mon. Output Toggling VIN= GND IC Total Power Supply Current 6 0.9 1.6 0.9 1.6 mA VCC= Max. Outputs Open fO= 50MHz 50% Duty Cycle OEA = OEB= GND Eleven Outputs Toggling VIN= VCC VIN= GND 45 62 5 VIN= VCC-0.6V VIN= GND 45 62 5 Notes: 1. For conditions shown as Max or Min, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3. Per TTL driven input (VIN = VCC -0.6V); all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. 5. Values for these conditions are examples of the IC formula. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fONO) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ∆ICC = Power Supply Current for a TTL High Input (VIN = VCC -0.6V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fO = Output Frequency NO = Number of Outputs at fO All currents are in milliamps and all frequencies are in megahertz. 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 5 of 12 September 2006 rev 0.3 Switching Characteristics Over Operating Range – Commercial3,4 Symbol tPLH tPHL tR tF tSK(O) tSK(P) PCS2P3805A Parameter Propagation Delay INA to OAn, INB to OBn Output Rise Time (0.8V to 2.0V) Output Fall Time (2.0V to 0.8V) Output skew: skew between outputs of all banks of same package (inputs tied together) Pulse skew: skew between opposite transitions of same output (|tPHL -– tPLH|) Package skew: skew between outputs of different packages at same power supply voltage, temperature, package type and speed grade Output Enable Time OEA to OAn, OEB to OBn ¯¯ ¯¯ Output Disable Time OEA to OAn, OEB to OBn ¯¯ ¯¯ Conditions1 PCS2P3805A Min 1.5 2 Max 5 2 2 0.5 Unit nS nS nS nS nS CL= 50pF RL= 500Ω 1 tSK(T) tPZL tPZH tPLZ tPHZ 1.2 nS 1.5 1.5 6 5 nS nS Switching Characteristics Over Operating Range – Industrial3,4 Symbol tPLH tPHL tR tF tSK(O) tSK(P) Parameter Propagation Delay INA to OAn, INB to OBn Output Rise Time (0.8V to 2.0V) Output Fall Time (2.0V to 0.8V) Output skew: skew between outputs of all banks of same package (inputs tied together) Pulse skew: skew between opposite transitions of same output (|tPHL -– tPLH|) Package skew: skew between outputs of different packages at same power supply voltage, temperature, package type and speed grade Output Enable Time OEA to OAn, OEB to OBn ¯¯ ¯¯ Output Disable Time OEA to OAn, OEB to OBn ¯¯ ¯¯ Conditions1 PCS2P3805A Min 1.5 2 Max 5.2 2 2 0.6 Unit nS nS nS nS nS CL= 50pF RL= 500Ω 1 tSK(T) tPZL tPZH tPLZ tPHZ 1.2 nS 1.5 1.5 6 5 nS nS Note: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested. 4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew. 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 6 of 12 September 2006 rev 0.3 Test Circuits and Waveforms VCC 6V GND 500Ω VIN Pulse Generator RT D.U.T 50pF 500Ω VOUT PCS2P3805A Switch Position Test Disable Low Enable Low Disable High Enable High Definitions: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Switch 6V GND Test Circuits for All Outputs 3V INPUT tPLH OUTPUT tR tF tPHL 2.0V 0.8V 1.5V 0V VOH 1.5V VOL INPUT tPLH1 OUTPUT 1 tSK(O) OUTPUT 2 tSK(O) tPHL1 3V VOH 1.5V VO L VO H Package Delay 3V INPUT tPLH OUTPUT tSK(P) = | tPLH - tPLH | tPHL 1.5V 0V VOH 1.5V VOL tPLH2 tPHL2 tSK(O) = | tPLH2 - tPLH1 | or | tPHL2 - tPHL1 | Output Skew – tSK(o) INPUT tPLH1 Package 1 OUTPUT tSK(t) Package 2 OUTPUT tPLH2 tPHL2 tSK(t) tPHL1 3V 1.5V 0V VOH 1.5V VOL VOH 1.5V VOL Pulse Skew ENABLE CONTROL INPUT tPZL OUTPUT NORMALLY SWITCH LOW CLOSED tPZH OUTPUT NORMALLY HIGH SWITCH OPEN 1.5V 0V 3.5V 1.5V tPHZ 0.3V VOH 0V tPLZ 0.3V DISABLE 3V 1.5V 0V 3.5V VOL tSK(t) = | tPLH2 - tPLH1 | or | tPHL2 - tPHL1 | Package Skew – tSK(t) Note: Pulse Generator for all Pulses:f ≤ 10MHz; tF ≤ 2.5nS; tR ≤ 2.5nS Enable and Disable Times Note: Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 7 of 12 September 2006 rev 0.3 Package Information 20-lead SSOP ( 209 mil ) PCS2P3805A Dimensions Symbol A A1 A2 D c E E1 L L1 b R1 a e Inches Min Max …. 0.002 0.065 0.275 0.004 0.295 0.197 0.021 0.009 0.004 0° 0.079 … 0.073 0.291 0.010 0.319 0.220 0.037 0.015 …. 8° Millimeters Min Max … 0.05 1.65 7.00 0.09 7.50 5.00 0.55 0.22 0.09 0° 2.0 ….. 1.85 7.40 0.25 8.10 5.60 0.95 0.38 …. 8° 0.050 REF 1.25 REF 0.0197 BASE 0.65 BASE 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 8 of 12 September 2006 rev 0.3 PCS2P3805A 20-lead QSOP Symbol A A1 b c D E e H h L S a Dimensions Inches Millimeters Min Max Min Max 0.060 0.004 0.009 0.007 0.337 0.150 0.230 0.010 0.016 0.056 0° 0.068 0.008 0.012 0.010 0.344 0.157 0.244 0.016 0.035 0.060 8° 1.52 0.10 0.23 0.18 8.56 3.81 5.84 0.25 0.41 1.42 0° 1.73 0.20 0.30 0.25 8.74 3.99 6.20 0.41 0.89 1.52 8° 0.025 BSC 0.64 BSC 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 9 of 12 September 2006 rev 0.3 PCS2P3805A 20L SOIC Package (300 mil) Dimensions Symbol A A1 A2 D L E1 R1 b c E e a Inches Min Max 0.093 0.004 0.088 0.496 0.016 0.291 0.003 0.013 0.009 0.394 0° 0.104 0.012 0.094 0.512 0.050 0.299 …. 0.022 0.015 0.419 8° Millimeters Min Max 2.35 0.10 2.25 12.60 0.40 7.40 0.08 0.33 0.23 10.00 0° 2.65 0.30 2.40 13.00 1.27 7.60 ….. 0.56 0.38 10.65 8° 0.050 BSC 1.27 BSC 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 10 of 12 September 2006 rev 0.3 Ordering Information Part Number PCS2P3805AG-20-AR PCS2P3805AG-20-AT PCS2P3805AG-20-DR PCS2P3805AG-20-DT PCS2P3805AG-20-SR PCS2P3805AG-20-ST PCS2I3805AG-20-AR PCS2I3805AG-20-AT PCS2I3805AG-20-DR PCS2I3805AG-20-DT PCS2I3805AG-20-SR PCS2I3805AG-20-ST PCS2P3805A Marking 2P3805AG 2P3805AG 2P3805AG 2P3805AG 2P3805AG 2P3805AG 2I3805AG 2I3805AG 2I3805AG 2I3805AG 2I3805AG 2I3805AG Package Type 20-Pin SSOP, TAPE & REEL, Green 20-Pin SSOP, TUBE, Green 20-Pin QSOP, TAPE & REEL, Green 20-Pin QSOP, TUBE, Green 20-Pin SOIC, TAPE & REEL, Green 20-Pin SOIC, TUBE, Green 20-Pin SSOP, TAPE & REEL, Green 20-Pin SSOP, TUBE, Green 20-Pin QSOP, TAPE & REEL, Green 20-Pin QSOP, TUBE, Green 20-Pin SOIC, TAPE & REEL, Green 20-Pin SOIC, TUBE, Green Temperature Commercial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Industrial Industrial Device Ordering Information PCS2P3805AG-20-DR R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved PulseCore Semiconductor Mixed Signal Product Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 11 of 12 September 2006 rev 0.3 PCS2P3805A PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright © PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: PCS2P3805A Document Version: 0.3 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 © Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 12 of 12